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Exposure mask and method for forming semiconductor device by using the same

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Title: Exposure mask and method for forming semiconductor device by using the same.
Abstract: It is the technology which forms the semiconductor device and makes the high integration possible by using the exposure mask including with the cell array having the light blocking patterns of line-shape and includes the assistant pattern assist feature, AF field of the same direction as the cell array. The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same ...


Browse recent Hynix Semiconductor Inc. patents - Icheon, KR
Inventor: Jae Seung CHOI
USPTO Applicaton #: #20120100469 - Class: 430 5 (USPTO) - 04/26/12 - Class 430 
Radiation Imagery Chemistry: Process, Composition, Or Product Thereof > Radiation Modifying Product Or Process Of Making >Radiation Mask

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The Patent Description & Claims data below is from USPTO Patent Application 20120100469, Exposure mask and method for forming semiconductor device by using the same.

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CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2009-0013004, filed on Feb. 17, 2009, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.

BACKGROUND OF THE INVENTION

The present invention relates to an exposure mask and a method for forming a semiconductor device by using the same, and more particularly, to an exposure mask used for a highly integrated semiconductor device and a method for forming a semiconductor device by using the same.

As a semiconductor technology advances, the size of a unit cell, for example, the size of a transistor becomes smaller and the degree of integration is sharply increased. The reduction of chip size is very important for high integration.

Particularly, in the field of DRAM (Dynamic Random Access Memory), significant chip size reduction was made. It was made by changing a cell structure or changing the layout of an active region.

Currently, the layout of a general active region is an 8F2 structure. Under this structure, the size of a unit cell is reduced by changing the arrangement of an active region with keeping 8F2 layout. For a 8F2 layout DRAM cell employing a folded bit line cell structure, one bit line reads data of a cell transistor through one sense amplifier (SA) by selecting one word line between two word lines.

Under an 8F2 layout, an active region is formed over 3F. Thus, overlay margin is generous, but it becomes hard to reduce unit cell area for higher integration.

Under a 6F2 layout employing an open bit line cell structure, adjacent two bit lines turn on to select one word line. The adjacent two bit lines are sensed by sense amplifiers which belong to different blocks to be read out.

When a DRAM cell is changed from an 8F2 structure into a 6F2 structure, the unit cell size reduces, the unit chip size reduces, and thus productivity increases. However, under a 6F2 structure, the design rule shrinks significantly, and thus the distance between active regions becomes short.

Therefore, according to a conventional exposure mask and a method for forming a semiconductor device using the exposure mask, it is required that an assist pattern (cell edge AF (Assist feature)) is formed on a cell edge area, and optical proximity correction (OPC) should be performed to prevent pattern distortion due to a smaller design rule.

FIGS. 1 and 2 are a photo and plan view illustrating a method for forming a semiconductor device employing a 6F2 structure using a conventional exposure mask.

FIG. 1 is a photo showing a photo resist pattern formed on a target semiconductor substrate by using an exposure mask in which the OPC pattern and the assistant pattern are formed at four corners of a cell configured of a quadrangle structure.

According to a conventional exposure mask, a light blocking pattern is formed to define a cell region in a line shape, and an assistant pattern is formed on the outer side of the cell region.

The assistant pattern is formed on the exposure mask, but is not transferred onto a target semiconductor substrate.

The light blocking pattern is formed on a quartz substrate. The OPC is individually performed location by location and the patterning is performed by a lithographic process.

An assistant pattern is formed of a plurality of line patterns. The distance between the light blocking patterns is not uniform, and the distance between the light blocking pattern and the assistant pattern is not uniform, either.

This is because OPC is made differently depending on the location of the light blocking patterns. Thus, the size of a plurality of rectangular patterns is not uniformly formed.

Referring to FIG. 1, a hard mask layer is formed on the target semiconductor substrate and a photo resist is coated on the substrate. Then, the photo resist pattern is formed by an exposure and development process using the conventional exposure mask mentioned above. The photo resist pattern is formed in a sloped shape like the light blocking pattern on the exposure mask.

A scum is formed on the sidewalls of the photo resist patterns along four sides of the cell region.

In a subsequent process, the photo resist pattern is used as a mask to pattern the hard mask layer. If a scum remains, the hard mask layer cannot be patterned as desired, and thus, an active region also cannot be defined as desired.

Then, the hard mask layer is patterned using the photo resist pattern so that the hard mask layer is left only over the active region.

A trench for isolation is formed by etching the target semiconductor substrate using the hard mask pattern as a etching mask and an isolation film is formed by filling the trench with insulating material.

FIG. 2 is a plan view which simplifies and illustrates the photograph of FIG. 1.

The same problem is found when an island type pattern is formed using a conventional exposure mask.

As described above, it is hard to properly pattern the photo resist pattern located on cell edge side due to a scum even if an OPC process is employed.

BRIEF

SUMMARY

OF THE INVENTION

Various embodiments of the invention are directed to provide an exposure mask which can be applied to the high integration of semiconductor device without OPC and a method for forming a semiconductor device using the same.

According to an embodiment of the present invention, an exposure mask comprises: light blocking patterns in which a pattern which is identical with a cell region is extended to the outer side from the cell region.

Preferably, the light blocking patterns are line-shaped, the light blocking patterns partly have a different line width according to density and line width of a micro-pattern formed in the cell region on wafer, and the light blocking patterns are formed with a width of 0.5-100 μm into the outer side of the cell region.

According to a first aspect of the present invention, a method for manufacturing a semiconductor device comprises: forming a hard mask layer on wafer; forming a hard mask layer pattern by using an exposure mask including light blocking patterns in which a pattern which is identical with a cell region is extended to the outer side from the cell region; and cutting the hard mask layer pattern by a photolithographic etching process using an exposure mask for cutting.

Preferably, the exposure mask for cutting is designed to have a light transmission region which is separated from the light blocking patterns of line-shape with a given gap and overlapped, the exposure mask for cutting may be designed in such a manner that the other region is a light transmission region, or the exposure mask for cutting may be designed in such a manner that the other region is a light blocking region.

According to a second aspect of the present invention, a method for manufacturing a semiconductor device comprises: forming a hard mask layer on wafer; forming a hard mask layer pattern by using an exposure mask including light blocking patterns in which a pattern which is identical with a cell region is extended to the outer side from the cell region; forming a spacer on the side wall of the hard mask layer pattern; removing the hard mask layer pattern; and forming a space pattern by a photolithographic etching process using an exposure mask for cutting.

Preferably, the hard mask layer and the spacer have a difference etch selectivity. The method for manufacturing a semiconductor device according to a second aspect of the present invention further comprises etching the wafer with the first hard mask layer pattern as a etching mask.

In the meantime, the technical principle of the present invention is as follows. The present invention has the shape and process margin which are identical with a cell and can implement the scheduled pattern on a wafer by constituting a region excepting cell formed with patterns having different forms and environments with patterns formed in the cell, that is, the outer side of cell, into the same shape as a cell.

That is, as usual, regions having different environments with cells exist. However, in the design of the present invention, regions different with cells are formed with a shape identical with the cell such that the scheduled pattern can be formed without a special OPC work.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are a plane photo and a plane view illustrating a method for forming a semiconductor device using a conventional exposure mask.

FIGS. 3 to 5 are a plane photo and a plane view illustrating an exposure mask according to an embodiment of the present invention and a method for forming a semiconductor device using the same.

DESCRIPTION OF EMBODIMENTS

Hereinafter, the present invention will be illustrated in detail with reference to the attached drawings.

FIGS. 3 and 4 are a plane view illustrating an exposure mask according to an embodiment of the present invention, illustrating the 6F2 cell structure. At this time, for convenience, a cell region 1000 and an other region 2000 are identically described in FIGS. 3 and 4.

Of course, like the 4F2 structure, the present invention can be applied to the cell structure of the 6F2 size or less, or can be applied to the cell structure of the 6F2 size or more.

FIG. 3 is an exposure mask 100 capable of forming a light blocking pattern 120 of line-shape, which forms a line pattern on the whole surface of wafer including the cell region 1000 and a region 2000 (hereinafter, “other region”) positioned in the outer side of cell region 1000. Here, FIG. 3 illustrates an end portion of one side of the cell region 1000 and the other region 2000 which is adjacent to that.

At this time, the light blocking pattern 120 of line-shape is formed in an active region (not shown) with a sloped shape. Of course, it can be formed to be horizontal or vertical with the active region if design and process margin approve.

Here, the light blocking pattern 120 in the other region 2000 should have the width of 0.5-100 μm from the cell region 1000.

According to the pattern size and the pattern density which is formed in the cell region 1000, the light blocking region 120 of line-shape can be formed with different sizes of line and space pattern.

FIG. 4 is an exposure mask 200 which cuts a line pattern (not shown) formed in the cell region of wafer by using the exposure mask 100 of FIG. 3 and is designed to remove the line pattern formed in the other region (refer to ‘2000’ of FIG. 3), which can be formed with a different polarity of light blocking region and transmission region according to the use of negative type photo resist or positive type photo resist. Here, it is exemplified that positive type photo resist is used.

Referring to FIG. 4, in the exposure mask 200, a light blocking pattern 220 which defines a light transmission region 210 of dot type isolated with a given distance on the light blocking pattern (‘120’ of FIG. 3) in order to form a plurality of bar types by cutting the light blocking pattern (‘120’ of FIG. 3) of line-shape on the cell region (‘1000’ of FIG. 3).

At this time, the light transmission region 210 is formed in such a manner that the other region (‘2000’ of FIG. 3) is all exposed and, if necessary, the light blocking pattern can be formed in the other region (‘2000’ of FIG. 3).

In the meantime, in case of using a negative photo resist, the light blocking region and the light transmission region can be interchanged to be formed.

FIG. 5a to 5e is a plane view illustrating a method for forming a semiconductor device using an exposure mask according to the present invention, illustrating the end of a part of wafer which is divided into a cell region 3000 and another region 4000.



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stats Patent Info
Application #
US 20120100469 A1
Publish Date
04/26/2012
Document #
13341320
File Date
12/30/2011
USPTO Class
430/5
Other USPTO Classes
International Class
03F1/00
Drawings
10



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