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Exposure mask and method for forming semiconductor device by using the same

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Title: Exposure mask and method for forming semiconductor device by using the same.
Abstract: It is the technology which forms the semiconductor device and makes the high integration possible by using the exposure mask including with the cell array having the light blocking patterns of line-shape and includes the assistant pattern assist feature, AF field of the same direction as the cell array. The present invention is the thing about exposure mask and manufacturing method of semiconductor device using the same ...


Browse recent Hynix Semiconductor Inc. patents - Icheon, KR
Inventor: Jae Seung CHOI
USPTO Applicaton #: #20120100469 - Class: 430 5 (USPTO) - 04/26/12 - Class 430 
Radiation Imagery Chemistry: Process, Composition, Or Product Thereof > Radiation Modifying Product Or Process Of Making >Radiation Mask

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The Patent Description & Claims data below is from USPTO Patent Application 20120100469, Exposure mask and method for forming semiconductor device by using the same.

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CROSS-REFERENCE TO RELATED APPLICATION

The priority of Korean patent application No. 10-2009-0013004, filed on Feb. 17, 2009, the disclosure of which is hereby incorporated in its entirety by reference, is claimed.

BACKGROUND OF THE INVENTION

The present invention relates to an exposure mask and a method for forming a semiconductor device by using the same, and more particularly, to an exposure mask used for a highly integrated semiconductor device and a method for forming a semiconductor device by using the same.

As a semiconductor technology advances, the size of a unit cell, for example, the size of a transistor becomes smaller and the degree of integration is sharply increased. The reduction of chip size is very important for high integration.

Particularly, in the field of DRAM (Dynamic Random Access Memory), significant chip size reduction was made. It was made by changing a cell structure or changing the layout of an active region.

Currently, the layout of a general active region is an 8F2 structure. Under this structure, the size of a unit cell is reduced by changing the arrangement of an active region with keeping 8F2 layout. For a 8F2 layout DRAM cell employing a folded bit line cell structure, one bit line reads data of a cell transistor through one sense amplifier (SA) by selecting one word line between two word lines.

Under an 8F2 layout, an active region is formed over 3F. Thus, overlay margin is generous, but it becomes hard to reduce unit cell area for higher integration.

Under a 6F2 layout employing an open bit line cell structure, adjacent two bit lines turn on to select one word line. The adjacent two bit lines are sensed by sense amplifiers which belong to different blocks to be read out.

When a DRAM cell is changed from an 8F2 structure into a 6F2 structure, the unit cell size reduces, the unit chip size reduces, and thus productivity increases. However, under a 6F2 structure, the design rule shrinks significantly, and thus the distance between active regions becomes short.

Therefore, according to a conventional exposure mask and a method for forming a semiconductor device using the exposure mask, it is required that an assist pattern (cell edge AF (Assist feature)) is formed on a cell edge area, and optical proximity correction (OPC) should be performed to prevent pattern distortion due to a smaller design rule.

FIGS. 1 and 2 are a photo and plan view illustrating a method for forming a semiconductor device employing a 6F2 structure using a conventional exposure mask.

FIG. 1 is a photo showing a photo resist pattern formed on a target semiconductor substrate by using an exposure mask in which the OPC pattern and the assistant pattern are formed at four corners of a cell configured of a quadrangle structure.

According to a conventional exposure mask, a light blocking pattern is formed to define a cell region in a line shape, and an assistant pattern is formed on the outer side of the cell region.

The assistant pattern is formed on the exposure mask, but is not transferred onto a target semiconductor substrate.

The light blocking pattern is formed on a quartz substrate. The OPC is individually performed location by location and the patterning is performed by a lithographic process.

An assistant pattern is formed of a plurality of line patterns. The distance between the light blocking patterns is not uniform, and the distance between the light blocking pattern and the assistant pattern is not uniform, either.

This is because OPC is made differently depending on the location of the light blocking patterns. Thus, the size of a plurality of rectangular patterns is not uniformly formed.

Referring to FIG. 1, a hard mask layer is formed on the target semiconductor substrate and a photo resist is coated on the substrate. Then, the photo resist pattern is formed by an exposure and development process using the conventional exposure mask mentioned above. The photo resist pattern is formed in a sloped shape like the light blocking pattern on the exposure mask.

A scum is formed on the sidewalls of the photo resist patterns along four sides of the cell region.

In a subsequent process, the photo resist pattern is used as a mask to pattern the hard mask layer. If a scum remains, the hard mask layer cannot be patterned as desired, and thus, an active region also cannot be defined as desired.

Then, the hard mask layer is patterned using the photo resist pattern so that the hard mask layer is left only over the active region.

A trench for isolation is formed by etching the target semiconductor substrate using the hard mask pattern as a etching mask and an isolation film is formed by filling the trench with insulating material.

FIG. 2 is a plan view which simplifies and illustrates the photograph of FIG. 1.

The same problem is found when an island type pattern is formed using a conventional exposure mask.

As described above, it is hard to properly pattern the photo resist pattern located on cell edge side due to a scum even if an OPC process is employed.

BRIEF

SUMMARY

OF THE INVENTION

Various embodiments of the invention are directed to provide an exposure mask which can be applied to the high integration of semiconductor device without OPC and a method for forming a semiconductor device using the same.



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stats Patent Info
Application #
US 20120100469 A1
Publish Date
04/26/2012
Document #
13341320
File Date
12/30/2011
USPTO Class
430/5
Other USPTO Classes
International Class
03F1/00
Drawings
10



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