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Evaluation of a temporal description within a general purpose programming languageRelated Patent Categories: Data Processing: Software Development, Installation, And Management, Software Program Development Tool (e.g., Integrated Case Tool Or Stand-alone Development Tool), Translation Of Code, Compiling Code, Analysis Of Code Form, Parsing, Syntax Analysis, And Semantic AnalysisEvaluation of a temporal description within a general purpose programming language description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060277534, Evaluation of a temporal description within a general purpose programming language. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention pertains in general to hardware functional verification and in particular to techniques for evaluating a temporal description within a general purpose programming language. [0003] 2. Background Art [0004] Using a temporal description to verify a hardware design is increasingly common. Hardware description languages such as the problem statement language (PSL) are becoming standards to verify hardware designs and various electronic design automation (EDA) tools are beginning to support the evaluation of such a temporal description. For example, a hardware description language such as System Verilog uses the temporal description mechanism to check the correctness of a hardware behavior during hardware simulation. Special purpose programming languages developed for designing hardware can adopt such a new language construct (i.e., temporal description) with an additional syntax. [0005] Another trend of hardware design is to use a general purpose programming language such as C++ to simulate a hardware behavior. In such an environment, users use a general purpose programming language with various hardware modeling support libraries to construct a simulation model to verify hardware behaviors. Because the hardware model is written in a general purpose programming language, it is easy to mix simulation codes, which are constructed using the general purpose programming language with software. [0006] In a general purpose programming language, however, the language syntax cannot be easily changed to support hardware simulation. It is desirable for the general purpose programming language to have a mechanism to evaluate a temporal description during hardware simulation. Moreover, it is desirable that such a mechanism be able to express a temporal description within the context of the general purpose programming language such that the temporal description is constructed with the general purpose programming language's native expression, and that variables used within the temporal description are taken from the name scope of the temporal description's location. [0007] In addition, because the temporal logic mechanism is useful in specifying the sequence of hardware behaviors, it is desirable to use it as an ordinal expression within a general purpose programming language. In such an expression, there will be a mixture of temporal constructs and ordinal expressions. To evaluate such a mixed expression, the ordinal expression is repeatedly evaluated over the program execution. However, the ordinal execution mechanism provided by general purpose programming language compilers cannot handle such a situation. [0008] Therefore, there is a need for a technique that effectively evaluates a temporal description within a general purpose programming language. DISCLOSURE OF INVENTION [0009] The above need is met by a translation module that translates a temporal description into a temporal expression. The translation module is adapted to translate a temporal description in the form of an extended syntax or a preprocessing macro to the temporal expression. The temporal expression includes a native expression of a general purpose programming language. The temporal expression may also include one or more construct functions. A parsing module generates a data structure that represents the temporal expression without evaluating the native expression. Particularly, the parsing module is adapted to parse the temporal expression to generate the data structure. During the parse phase, the parsing module creates a data structure, copies a return address in a stack to a data structure for future evaluation. Then it avoids evaluating the native expression during the parse phase by controlling a construct function's return value to be false. [0010] An evaluation module evaluates the data structure to execute the temporal expression including the native expression. For example, the evaluation module returns to the address stored in the data structure instead of the actual return address in the stack and evaluates the native expression by controlling the construct function's return value to be true. The evaluation module also evaluates a variable within the native expression from a name scope of the native expression's program location. According to an embodiment of the invention, the evaluation module creates one or more nondeterministic finite automata (NFA) state structures that include data to be evaluated at one or more clock cycles. The evaluation module stores the one or more NFA state structures in a queue. The evaluation module then retrieves a NFA state structure from the queue in response to the passing of clock cycles to evaluate the retrieved NFA state structure. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 is a high-level block diagram of a computing environment according to an embodiment of the present invention. [0012] FIG. 2 is a high-level block diagram illustrating modules within an execution module according to an embodiment of the present invention. [0013] FIG. 3 is a block diagram illustrating the configuration of an exemplary stack according to an embodiment of the present invention. [0014] FIGS. 4A and 4B are block diagrams illustrating the parsing of an exemplary temporal expression according to an embodiment of the present invention. [0015] FIGS. 5-8 are block diagrams illustrating the evaluation of an exemplary temporal expression according to an embodiment of the present invention. [0016] FIG. 9 is a block diagram illustrating the execution path for an exemplary temporal expression during the evaluation phase according to an embodiment of the present invention. [0017] FIG. 10 is a block diagram illustrating the execution path for an exemplary expression during the evaluation phase according to an embodiment of the present invention. [0018] FIG. 11 is a flowchart illustrating steps performed by a computing environment according to an embodiment of the present invention. [0019] The figures depict an embodiment of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0020] FIG. 1 is a high-level block diagram of a computing environment 100 according to an embodiment of the present invention. FIG. 1 illustrates that the computing environment 100 includes a transformation module 102 (generally referred to as a translation module), a preprocessing module 104 (also generally referred to as a translation module), and an execution module 106. Those of skill in the art will understand that other embodiments of the computing environment 100 can have different and/or other modules than the ones described herein. In addition, the functionalities can be distributed among the modules in a manner different than described herein. Continue reading about Evaluation of a temporal description within a general purpose programming language... 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