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  Etching methods and apparatus and substrate assemblies produced therewithUSPTO Application #: 20070077724Title: Etching methods and apparatus and substrate assemblies produced therewith Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high-aspect-ratios can be etched. (end of abstract)
Agent: Williams, Morgan & Amerson - Houston, TX, US Inventors: Kevin G. Donohoe, Rich Stocks USPTO Applicaton #: 20070077724 - Class: 438424000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Formation Of Electrically Isolated Lateral Semiconductive Structure, Grooved And Refilled With Deposited Dielectric Material The Patent Description & Claims data below is from USPTO Patent Application 20070077724. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending application Ser. No. 10/895,502, filed Jul. 20, 2004, which is a continuation of application Ser. No. 09/916,734, filed Jul. 26, 2001, now U.S. Pat. No. 6,784,111, which is a division of application Ser. No. 09/342,677, filed Jun. 29, 1999, now U.S. Pat. No. 6,635,335, which are incorporated herein by reference. TECHNICAL FIELD [0002] The invention pertains to methods and apparatus for etching silicon wafers or other substrate assemblies and to substrate assemblies. BACKGROUND OF THE INVENTION [0003] The fabrication of very large-scale integrated circuits requires processes that are compatible with small feature sizes (e.g., 0.25 .mu.m). A particular problem is the etching of a silicon wafer or other substrate assembly to produce damascene layers, self-aligned contacts (SACs), or trench isolation. These features typically require etching relatively deeply into the wafer while maintaining a small footprint on the surface of the substrate assembly, i.e., these features have a high-aspect-ratio (HAR), with a depth-to-width (on the surface of the substrate assembly) ratio of 4:1 or larger. [0004] Features to be etched into a substrate assembly are typically defined with a layer of photoresist that is spin-coated or otherwise applied onto a surface of the substrate assembly and then photolithographically patterned. After patterning, some areas of the substrate assembly surface remain covered by the photoresist layer while other areas are exposed. The covered substrate assembly is exposed to an etch, and the photoresist layer prevents etching except in the exposed areas. [0005] Etching of HAR features requires anisotropic etches that etch more rapidly in one direction than another. Conventional wet etches include dilute solutions of acids such as hydrofluoric acid. While wet etching is simple and inexpensive, wet etching is generally inadequate to produce HAR features because wet etches tend to etch isotropically. In addition, it is difficult to etch deep HAR features into a substrate assembly because the etchant does not flow freely into and out of the feature. Therefore, even if a wet etch begins to etch properly, etchant is consumed within the feature being etched and is replenished slowly. [0006] Dry etching with plasmas is also used for etching substrate assemblies. In plasma etching, a gas or gas mixture is fragmented and ionized and the ions produced are accelerated toward the substrate assembly. When the ions reach the substrate assembly, they combine chemically with the substrate assembly to form volatile compounds that are readily driven off of the substrate assembly. In some cases, the mechanical impact of the ions with the substrate assembly also serves to etch the substrate. Because of the acceleration of the ions toward the substrate assembly, etching is anisotropic and proceeds rapidly on surfaces that are perpendicular to the propagation direction of the ions. [0007] Unfortunately, dry etching with a plasma has significant limitations. While plasmas etch anisotropically, a plasma etches both the substrate assembly and the photoresist that defines the features to be produced. As a result, the total etching time is limited by the time required for the plasma etch to penetrate the photoresist. When the photoresist is penetrated, further etching is no longer limited to the intended substrate locations, but occurs in all substrate areas that are not protected by the photoresist. Photoresists typically etch four to five times more slowly than typical substrate materials to be etched (such as silicon or silicon oxide). Etching processes in which a substrate material is etched at a rate of less than about eight times the rate at which a resist etches are referred to herein as "resist-consuming." [0008] Etching deep HAR features requires thick layers of photoresist to permit long etch times, and such thick layers complicate the photolithographic patterning process. For example, to etch a HAR feature 3000 nm deep requires a photoresist thickness of as much as 750 nm. Patterning a feature as small as about 250 nm is very difficult in such a thick layer of photoresist. [0009] Other factors limiting plasma etching include the difficulty of providing a selected distribution of ions (charged particles) and neutral particles at the substrate surface and at the bottom of a feature being etched. Accordingly, improved etching methods are needed, especially for etching high-aspect-ratio features. A resist layer has a nominal thickness and a facet thickness, either or both of which are maintained, preserved, or increased in the disclosed methods and apparatus. SUMMARY OF THE INVENTION [0010] Methods and apparatus for etching substrate assemblies are disclosed in which a surface of a substrate assembly is etched while a thickness of a resist layer increases, remains constant, or decreases much more slowly than in a conventional etching process. [0011] In a representative embodiment, the substrate assembly is exposed to a plasma made in a selected gas, which may be a gas mixture, at a selected flow rate. The gas and flow rate are selected by exposing a resist layer to the plasma formed in the gas and determining a range of flow rates for which the thickness of the resist layer, including any material deposited on the resist layer by the plasma, increases, remains constant or decreases more slowly than in known approaches. The etching rate of the selected gas is then measured for this range of flow rates on a surface of a substrate assembly. A flow rate is then selected for etching the surface of the substrate assembly for which the resist thickness increases or otherwise changes in the desired manner while a surface is etched. [0012] In an alternative embodiment, the flow rate is selected so that the resist is etched much more slowly (for example ten to twenty times) than the surface of the substrate assembly. In some embodiments, the substrate assembly includes a silicon oxide layer that is etched with the selected gas at the selected flow rate. [0013] A method of plasma etching is provided in which a high-aspect-ratio feature is etched into a surface of a substrate assembly while a resist layer covering a portion of the surface thickens, remains a constant thickness, or thins by less than about 25 nm. In addition, the method may provide a controlled-etch profile so that the sides of the etched feature have taper or undercut angles of less than about ten degrees and, more specifically, in one approach less than about five degrees. [0014] A method of anisotropically etching a substrate assembly is provided that comprises forming a resist layer on a surface of a substrate assembly and defining patterns in the resist layer by removing portions of the resist layer. The resist layer and the surface of the substrate are exposed to a plasma etch. In one specific approach, an exposed portion of the surface of the substrate assembly is etched by the plasma while the plasma increases the thickness of the resist layer. In another representative embodiment, the surface of the substrate assembly is exposed to a plasma generated in a gas consisting essentially of a fluorinated, chlorinated, or hydrogenated hydrocarbon gas, or a mixture thereof. In additional embodiments, the thickness of the resist layer formed on the substrate assembly is less than about 600 nm. In a further embodiment, the resist layer has a thickness of d, and a high-aspect-ratio feature is etched into the substrate assembly to a depth D such that D/d>10. [0015] Etched substrate assemblies are disclosed that may include an etched feature having an aspect ratio of at least 10:1 or higher, such as at least 20:1. [0016] In additional embodiments, the substrate assembly includes a silicon oxide layer formed on a silicon wafer and the etched feature is etched into the silicon oxide layer. [0017] In another method, a feature is etched into a substrate assembly by forming a resist layer on a surface of the substrate assembly and defining a feature on the surface by patterning the resist layer by removing the resist layer from at least a portion of the substrate assembly. The portion of the substrate assembly that is not covered by the resist layer is etched with a plasma generated in a flow of a first halogenated hydrocarbon-containing gas or gas mixture. Simultaneously with the etching of the substrate assembly, the plasma increases the thickness of the resist layer, and the feature is etched to have an aspect ratio of at least 10:1. In a further embodiment, one or more subsequent or prior etches, including a resist-consuming etch, may be performed to etch the portion of the substrate assembly that is not covered by the resist. [0018] In another embodiment a method of etching a high-aspect-ratio feature having a controlled profile is provided. The method includes the steps of selecting a substrate assembly and selecting a surface of the substrate assembly to be etched. A depth D and width d of a high-aspect-ratio feature are selected, for example such that D/d>10. In this example, a resist layer of thickness less than about D/5 is formed on the selected surface of the substrate assembly. The high-aspect-ratio feature is then etched into the selected surface of the substrate assembly with a controlled profile. In one embodiment, the substrate assembly is a silicon wafer with a layer of silicon oxide. In other embodiments, the thickness of the resist layer is selected to be less than about D/7, D/10 or D/15. [0019] In another embodiment, a resist layer having a nominal thickness is deposited on a surface of a substrate assembly and patterned by removing selected portions of the resist layer, exposing a portion of the surface of the substrate assembly. The substrate assembly is etched to a depth of at least five times the nominal thickness at the exposed portion of the surface. [0020] An etched substrate assembly is disclosed that comprises a selected surface and a feature etched into the selected surface to a depth D and width w, wherein D/w is greater than about 10. The substrate assembly may include a resist layer covering the surface except at the high-aspect-ratio feature, the resist layer having a thickness d, wherein d/D is greater than about 1/10. Continue reading... Full patent description for Etching methods and apparatus and substrate assemblies produced therewith Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Etching methods and apparatus and substrate assemblies produced therewith patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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