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Etchant and method of useRelated Patent Categories: Etching A Substrate: Processes, Gas Phase Etching Of Substrate, Etching Inorganic Substrate, Etching Silicon Containing SubstrateEtchant and method of use description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060186087, Etchant and method of use. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 10/888,255, filed Jul. 9, 2004, pending, which application is a divisional of U.S. patent application Ser. No. 09/559,504, filed on Apr. 27, 2000, now U.S. Pat. No. 6,890,863, issued May 10, 2005, the disclosures of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. The Field of the Invention [0003] The present invention relates to semiconductor device fabrication. More particularly, the present invention relates to etch processing of semiconductor structures. In particular, the present invention relates to a contact hole etch and process therefore that operates in the subhalf-micron range, where the etchant includes a compound that is used as a selectivity enhancer. [0004] 2. State of the Art [0005] In the microelectronics industry, a "substrate" refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material including, but not limited to, bulk semiconductive material such as a semiconductive substrate, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including, but not limited to, the semiconductive substrates described above. [0006] Miniaturization is the process of crowding an ever-increasing number of microelectronic devices into the same amount of semiconductive substrate real estate while maintaining and/or improving the quality of each microelectronic device. Miniaturization also requires improving and/or maintaining the integrity of interconnects and vias. The pressure to fabricate ever-smaller microelectronic devices on the active surface of semiconductive substrates consequently requires the formation of smaller topographical features that define the components of the microelectronic devices. One feature is the contact corridor, also known as the contact hole or channel (hereinafter "contact") which typically comprises a circular depression that extends through a dielectric layer to an underlying structure that is electrically conductive or electrically semiconductive. [0007] As the miniaturization process progresses into the subhalf-micron range, structural dimension tolerances become increasingly important such that processing sensitivity must be correspondingly improved. As an example, a contact in the subhalf-micron range preferably retains a critical dimension (CD) within a defined tolerance during a high-aspect ratio anisotropic etch through a dielectric layer. The contact, therefore, must retain its initial circular cross section and constant diameter cylindrical shape within the dielectric layer in order to avoid cutting into an underlying structure outside of the CD. Additionally, the CD cannot become so small that an open circuit is created due to the inability to fill the contact, or a destructively high resistance created by too narrow of a contact. [0008] As used herein, the term "high-aspect ratio" refers to depth-to-bottom CD ratio of about five to one or more. In addition to contacts, high-aspect ratio subhalf-micron width lines or trenches within a dielectric layer must be fabricated under conditions that require similar etch tolerances. [0009] A dry, or plasma etch in an etch tool is the preferred process for etching a subhalf-micron contact. Inductively coupled, or high density etch systems are commonly referred to as etch tools. It would be desirable to etch a high-aspect ratio contact through a layer of dielectric in an etch tool while retaining the preferred CD. [0010] Dielectrics may be materials such as borophosphosilicate glass (BPSG) or other materials such as oxides, nitrides, or dielectric anti-reflective coatings (DARC) that are placed between the mask and the substrate silicon. Processing parameters for the etching of a contact require the ability to maintain a CD for about a 2.2 microns deep feature, overetched by 0.4 microns and to generate a contact profile that is preferably only slightly tapered or more preferably substantially cylindrical. At the subhalf-micron geometry, an increase in the radius of the contact caused by a re-entrant profile may be sustained up to about 0.025 microns. Contacts with a depth of about 2.2 microns and between 0.2 and 0.45 microns for a CD would be considered to have achieved the required CD profile control. [0011] Because the etching process typically involves a silicon oxide such as BPSG and an etch stop layer such as silicon nitride or other materials including doped or undoped silicon oxide, enhanced selectivity to the etch stop layer is required as fabrication proceeds into the subhalf-micron regime. [0012] Another problem that exists in the prior art is that different etch types require different chamber wall temperatures. Where a high chamber wall temperature etch must be followed by a lower chamber wall temperature etch, transfer of the semiconductive substrate from the high chamber wall temperature etch to a low chamber wall temperature etch is required because of the inability to cool the high-temperature etch chamber rapidly enough. Attempting to conduct a lower temperature etch in a hot, high-temperature etch chamber may cause the lower temperature etch to malfunction and to consequently damage or destroy the semiconductor device being fabricated. It is therefore necessary to transfer the semiconductive substrate out of the high-temperature etch chamber into a lower temperature etch chamber. Such a transfer is both time consuming and technically difficult where the necessity of maintaining the clean environment requires a transfer to an etch chamber that may be remote and thermally insulated from the high-temperature etch chamber. It would therefore be an improvement in the art to discover a method of etching for two traditionally different temperature etches with a closer temperature range or the same temperature range. [0013] Applied Materials, Inc. of Santa Clara, Calif. currently offers an inductively-coupled plasma etcher identified as the Dielectric Etch IPS Centura.RTM. system (the "IPS system") for etching high-aspect ratio contacts, among other uses. The IPS system uses an inductively-coupled, parallel plate technology that employs temperature controlled Si surfaces within the etch chamber in combination with fluorine-substituted hydrocarbon etch gases to achieve an oxide etch having a selectivity to silicon nitride in excess of ten to one. U.S. Pat. No. 5,423,945, assigned to Applied Materials, Inc., discloses the structure of operation of a predecessor apparatus to the IPS system, a schematic of which is shown in FIG. 1. The disclosure thereof is incorporated herein by specific reference. [0014] An IPS system 10 as depicted in FIG. 1 includes an etch chamber 12 primarily defined between a grounded silicon roof 14, an RF powered (bias) semiconductive substrate support 16 and a silicon ring 18 surrounding semiconductive substrate support 16, on which a semiconductive substrate 100 is disposed for processing. A plasma 20 generated over semiconductive substrate 100 is confined by magnetic fields as seen at reference numerals 22 and 24. Gases are supplied to chamber 12 through a valved manifold 26 which is connected to a plurality of gas sources (not shown). Evacuation of etch chamber 12 may be effected as desired through a valve 28, as is known in the art. [0015] An RF source power is supplied to an inner antenna 30 and an outer antenna 32 by an RF generator 34. The inner and outer antennae 30 and 32 are tuned for resonance in order to provide an efficient inductive coupling with plasma 20. Inner antenna 30, outer antenna 32, RF generator 34 and associated circuitry comprise a source network 36. Bias power is also supplied to semiconductive substrate support 16 by RF generator 34. RF generator 34, supplying power to semiconductive substrate support 16, comprises a bias network 38 with associated circuitry as shown. RF bias power is delivered at 1.7.+-.0.2 MHz, RF outer antenna power at 2.0.+-.0.1 MHz, and RF inner antenna power at 2.3.+-.0.1 MHz. Other details of IPS system 10 being entirely conventional, no further discussion thereof is required. Semiconductive substrate 100 is attached to a monopolar electrostatic chuck as a semiconductive substrate support 16. [0016] A plasma etch process that was initially developed for use with the IPS system employs a gas flow of a relatively high rate and somewhat complex chemistry, relatively high process temperatures and, most notably, CO (carbon monoxide) in the gas mixture. Specifically, the process employs 300-400 (and preferably 358) standard cubic centimeters per minute (sccm) Ar (argon), 55 sccm CO, 82 sccm CHF.sub.3 (trifluoromethane), and 26 sccm CH.sub.2F.sub.2 (difluoromethane) with a process pressure of 50 mTorr. Source power input is about 1650 watts, apportioned as 1400 watts to the outer antenna and 250 watts to the inner antenna. Bias power is about 800 watts. According to the IPS system manufacturer, the high volume of Ar is required, or at least desirable, to maintain a plasma state within the etch chamber. [0017] The IPS system employs the adjustable, dual-antenna inductive source and bias power control to adjust etch results. All high density oxide etch tools such as the IPS system can deposit from about 2,000 to about 4,000 angstroms per minute of fluorocarbon polymers on the semiconductive substrate under conditions if the bias power is set to zero. In other words, any surface that is not powered is exposed to a flux of pre-polymer material that will deposit on the surface unless conditions are altered to prevent its deposition. [0018] Capacitative coupling is often a source of difficulty during etching. The common assignee of the present invention has filed several patent applications regarding the control of this capacitative coupling, including U.S. application Ser. No. 09/012,155, now U.S. Pat. No. 6,095,159, entitled "Method of Modifying an RF Circuit of a Plasma Chamber to Increase Chamber Life and Process Capabilities"; U.S. application Ser. No. 09/031,400, now U.S. Pat. No. 6,516,742, entitled "Apparatus for Improved Low Pressure Inductively Coupled High Density Plasma Reactor"; and U.S. application Ser. No. 09/020,696, now U.S. Pat. No. 5,998,931, entitled "Method and Apparatus for Controlling Electrostatic Coupling to Plasmas." The disclosures of the aforementioned three patents are incorporated herein by reference. [0019] Some of the high density oxide etch tools have virtually no capacitative coupling between the source coil and the plasma. For example, the IPS system, as identified hereinabove has virtually no such coupling. The conducting silicon roof on the IPS system acts as an electrostatic shield which eliminates electrostatic coupling between the source coil and the plasma. Thus, roof temperature may be used to control the amount of deposition that occurs on the roof of the IPS system. Additionally, the IPS system uses a reactive surface to line the chamber walls or parts of the walls. The IPS system uses silicon which it heats to temperatures that are too high to permit deposition but that are sufficiently high to scavenge free fluorine from the etch plasma. [0020] It would be advantageous to develop a process for use with the IPS system or an equivalent system that would be simple and easy to control and optimize while still meeting manufacturing specifications for the high-aspect ratio contacts and other apertures, such as lines or trenches which may be formed in a substrate. Such a process would be expected to yield similar results in any inductively-coupled plasma etcher which employs silicon surfaces at elevated temperatures within the etch chamber. [0021] It would also be advantageous to develop a process for use with the IPS system which would be versatile enough to allow different etch types to be conducted on the same semiconductive substrate without requiring a transfer of the semiconductive substrate from one etch tool to another due to disparate temperature differences between the two etch types. SUMMARY OF THE INVENTION Continue reading about Etchant and method of use... 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