Error detection/correction and fault detection/recovery inventions

20080109675 - Remote logging mechanism: A method and system to remotely log debug information is described. A computer executing program code generates debug information upon the occurrence of an error in execution. The debug information is then sent to a remote computer using a network adaptor. In one embodiment, the computer executing the program is... Agent: Intel/blakely

20080109678 - System and method for intelligent data management: A system and method for intelligent data management enables the transport of items within a network by creating a first database defining a transport path of an item from an origin facility to a destination facility, and operations that affect the transport of items. In order to update the transport... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080109680 - Method and apparatus for testing web application, and comuter product: (A) “org.apache.struts.taglib.bean.WriteTag” written in a JAVA source segment is extracted as the tag class of a custom tag, “AddForm” in the segment is extracted as the attribute value of a name attribute, and “result” in the segment is extracted as the attribute value of a property attribute. (B) “<!--testStart expected=“5”-->... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20080109682 - Integrated circuit card with condition detector: An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal condition detector detects whether at least one operating condition of the integrated circuit card is within one of a suspend... Agent: Volentine & Whitt Pllc

20080109683 - Automated error reporting and diagnosis in distributed computing environment: An apparatus, program product and method provide a generic error reporting and diagnosis framework that is readily suited for use in a wide variety of distributed computing environments, and that supports the autonomic reporting, diagnosis, and potentially the remediation of errors. The framework supports the encapsulation of symptomatic data associated... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080109684 - Baselining backend component response time to determine application performance: Deviation of expected response times is used to characterize the health of one or more backend machines invoked by an application to process a request. Performance data generated in response to monitoring application execution is processed to select backend response time data. The selected data is processed to predict future... Agent: Vierra Magen Marcus & Deniro LLP

20080109685 - Apparatus and method for providing error notification in a wireless virtual file system: An apparatus (20) provides a dynamically-generated audio and/or video error file upon the occurrence of an error condition in a wireless virtual file system (100). According to an exemplary embodiment, the apparatus (20) includes a host interface (22) for connecting to a host device (10) and a network interface (30)... Agent: Joseph J. Laks Thomson Licensing Llc

20080109686 - Failure diagnosis for logic circuits: A failure diagnosing method of logic circuits includes generating failure candidate data for logic circuits based on failure diagnosis data obtained from the logic circuits by using a failure diagnosis tool; and inputting the failure candidate data for the logic circuits. A predetermined data is extracted from each of the... Agent: Young & Thompson

20080109676 - Processing device and storage medium: Provided is a processing device capable of utilizing important data even if a trouble occurs. The information processing device comprises a storage device for storing a first basic program and data, start means for executing a second basic program, which is stored in a second storage unit at least logically... Agent: Staas & Halsey LLP

20080109677 - System and method for validating channel transmission: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20080109679 - Administration of protection of data accessible by a mobile device: The administration of protection of data on a client mobile computing device by a server computer system such as within an enterprise network or on a separate mobile computing device is described. Security tools are described that provide different security policies to be enforced based on a location associated with... Agent: King & Schickli, Pllc

20080109681 - Apparatus for adaptive problem determination in distributed service-based applications: A technique for problem determination in a distributed application is provided. Testing results of the application are first obtained through execution of test cases of a test group in the application. The testing of the application is then adaptively refined when the testing results have one or more failures, to... Agent: Ryan, Mason & Lewis, LLP

20080109687 - Method and apparatus for correcting data errors: The illustrative embodiments provide a computer implemented method and an apparatus for correcting data errors. An error correction unit receives data from a register. Responsive to receiving the data from the register, the error correction unit determines whether an error is present in the data. Responsive to identifying the error... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080109688 - Built in self test transport controller architecture: A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely... Agent: Lsi Corporation

20080109689 - Test system improving signal integrity by restraining wave reflection: A test system that tests a plurality of memories comprises a tester, a test board coupled to the tester, and a transmission line. The test board includes the plurality of memories. A transmission line connects the memories to each other in parallel. The test board includes a compensating unit that... Agent: Mills & Onello LLP

20080109690 - Test system employing test controller compressing data, data compressing circuit and test method: A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial... Agent: Volentine & Whitt Pllc

20080109691 - Method and apparatus for executing a bist routine: During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding... Agent: Qualcomm Incorporated Patent Department

20080109692 - Reducing channel-change time: Systems and methods are disclosed herein for utilizing forward error correction (FEC) during a channel-change event. In one embodiment, among others, a method for executing a change from one communication channel to another includes receiving a channel-change indication and obtaining data and FEC that corresponds to the data. The data... Agent: Wm. Brook Lafferty Scientific-atlanta, Inc.

20080109693 - Harq transmission feedback for higher layer protocols in a communication system: A method is described for providing Hybrid Automatic Repeat Request (HARQ) transmission feedback to a higher layer protocol in a communication system. The method includes a step of detecting HARQ retransmissions in a first layer protocol. This can be used to determine a HARQ failure or an HARQ ACK after... Agent: Motorola, Inc.

20080109695 - Method and apparatus for performing multi-input multi-output transmission in a multi-input multi-output user equipment in a wireless communications system: A method for performing MIMO transmission in a UE capable of triggering at least one HARQ procedure in a wireless communications system is disclosed. The method includes selecting at least one HARQ process or at least one HARQ entity corresponding to a specified transmitter according to at least one transmission... Agent: Birch Stewart Kolasch & Birch

20080109694 - Method and apparatus for performing uplink transmission in a multi-input multi-output user equipment of a wireless communications system: A method for performing uplink transmission in a MIMO UE of a wireless communications system is disclosed. The UE is capable of triggering at least one HARQ procedure. The method includes configuring at least one receiver of the UE to receive at least one control or configuration message corresponding to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080109696 - Systems and methods for forward error correction in a wireless communication network: A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead and size.... Agent: Pulse-link, Inc.

20080109697 - Memory and method for checking reading errors thereof: A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory... Agent: Rabin & Berdo, Pc

20080109698 - Hybrid min-sum decoding apparatus with low bit resolution for ldpc code: A new, improved method for mix min-sum decoding using a LDPC code is provided. In order to reconcile the drawbacks of the belief propagation (BP) and min-sum method, but at the same to keep the benefit of same, two major improvements have been proposed in the present invention. In the... Agent: Franklin (lin) Yang

20080109699 - Method, apparatus and computer program product providing for data block encoding and decoding: Methods, apparatus and computer program products are provided for encoding and/or decoding a data block. The method for encoding a data block includes the steps of: providing an information block of size k, I=(i0,i1, . . . i(k−1); and encoding the information block into a low-density parity-check (LDPC) codeword c... Agent: Harrington & Smith, Pc

20080109700 - Semiconductor memory device and data error detection and correction method of the same: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less... Agent: F. Chau & Associates, Llc

20080109701 - Turbo interference suppression in communication systems: Disclosed is a method and communication device for suppressing interference. The method comprises performing, with a turbo decoder (314), at least one turbo decoding attempt (1106) on a received signal (1104). The turbo decoding attempt generates at least one whole word code bit therefrom (1108). The whole word code bit... Agent: Motorola, Inc.

20080109702 - Methods of modulating error correction coding: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that... Agent: Winston & Strawn, LLP

20080109703 - Nonvolatile memory with modulated error correction coding: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that... Agent: Winston & Strawn, LLP

20080109704 - Data allocation in memory chips: In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a codeword in a single internal word of the memory device.... Agent: Hewlett Packard Company

20080109705 - Memory system and method using ecc with flag bit to identify modified data: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080109706 - Error correction method and apparatus for optical information storage medium recording/reproducing apparatus: An error correction method and apparatus for use in an optical information storage medium recording/reproducing apparatus, in which an error data value is detected from the original data value stored in an external memory unit and a corrected data value for the error data value is updated to the external... Agent: Stein, Mcewen & Bui, LLP

20080109707 - Forward error correction encoding for multiple link transmission capatible with 64b/66b scrambling: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on... Agent: Ibm Microelectronics Intellectual Property Law

20080109708 - Apparatus and method for signal transmission/reception in a communication system: A method and an apparatus for transmitting a signal in a communication system are provided. An information vector is encoded according to a Low Density Parity Check (LDPC) encoding scheme, thereby generating an LDPC codeword. Minimum surviving check nodes are reserved for recovery of punctured nodes in the LDPC codeword.... Agent: The Farrell Law Firm, P.c.

20080109709 - Hardware-efficient, low-latency architectures for high throughput viterbi decoders: A low-latency, high-throughput rate Viterbi decoder implemented in a K1-nested layered look-ahead (LLA) manner, combines K1-trellis steps, with look-ahead step M, where K<K1<M, and K is the encoder constraint length. M can be an integer multiple or a non-integer multiple of one or both of K and K1. A K1-nested... Agent: Keshab K. Parhi

20080109710 - Viterbi decoding method: A decoding method relative to this application improves an error correction performance without increasing a memory. The decoding method includes obtaining a first decoded result from a first decoding path being on a trellis diagram; determining whether the first decoded result is incorrect or not; creating a second decoding path... Agent: Mcginn Intellectual Property Law Group, Pllc

20080109711 - Wireless communication system, wireless communication apparatus, wireless communication method, and computer program: A wireless communication system includes a first communication station configured to operate according to a first communication protocol, and a second communication station capable of operating according to both the first communication protocol and a second communication protocol. When the second communication station transmits a packet according to the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080104441 - Data processing system and method: A method of kernel panic recovery, comprising detecting a kernel panic of a first kernel, retrieving at least some of a state of at least one thread running on the first kernel, and restoring the state of the at least one process on a second kernel.... Agent: Hewlett Packard Company

20080104443 - Information system, data transfer method and data protection method: Availability of an information system including a storage system that performs remote copy between two or more storage apparatuses and a host computer using such storage system is improved. A third storage apparatus including a third volume is coupled to a first storage apparatus, a fourth storage apparatus including a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080104448 - Testing apparatus for semiconductor device: A testing apparatus for semiconductor device comprises test controllers 10-1, 10-2, . . . , 10-N, variable clock generators 24-1, 24-2, . . . , 24-N which are provided respectively associated with the test controllers 10-1, 10-2, . . . , 10-N and which output variable clock signals having certain... Agent: Muramatsu & Associates

20080104450 - Computer system and control method thereof: A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and... Agent: Stanzione & Kim, LLP

20080104449 - Discrete device testing: One embodiment in accordance with the invention is a method that comprises testing a first number of physical devices using a first test sequence that comprises an item. A second number of physical devices are tested using a second test sequence. It is noted that the second test sequence comprises... Agent: Hitachi C/o Wagner Blecher LLP

20080104452 - Providing policy-based application services to an application running on a computing system: Methods, apparatus, products are disclosed for providing policy-based application services to an application running on a computing system. The computing system includes at least one compute node. The compute node includes an application and a plurality of application services of a service type. Providing policy-based application services to an application... Agent: Ibm (roc-blf)

20080104454 - System and method of error reporting in a video distribution network: Method, systems and devices for error reporting in a video distribution network are disclosed. A method may include determining that a network communication error has occurred in a video distribution network. The method may also include sending an error reporting interface to a video display. The method may also include... Agent: Toler Law Group

20080104442 - Method, device and system for automatic device failure recovery: Embodiments of the present invention provide a method, devices and a system for automatic device failure recovery. The method mainly includes: sending a recovery request message to a management device or a server; obtaining a program file used for failure recovery from the management device or the server; and performing... Agent: Sughrue Mion, PLLC

20080104446 - Hard disk drive data scrub methodology: Method, system and computer program product for reporting and recovering from uncorrectable data errors in a data processing system using the Advanced Technology Attachment (ATA) or the Serial ATA (SATA) protocol. The invention utilizes the data scrubbing functionality of SCSI hard drives to provide a higher level of data integrity... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104445 - Raid array: A method of providing a RAID array, comprising providing an array of disks (202a-202f), creating an array layout (200) comprising a plurality of blocks (D1-D26, P1-P10) on each of the disks (202a-202f) and a plurality of disk stripes (204a-204j) that can be depicted in the layout (200) with the stripes... Agent: Hewlett Packard Company

20080104444 - System including a plurality of data storage devices connected via network and data storage device used therefor: Embodiments of the present invention help improve the process for updating parities accompanied by the writing process. According to one embodiment, a host controller transmits a write command and new data to a hard disk drive (HDD). The HDD reads old data at a region where the new data are... Agent: Townsend And Townsend And Crew LLP

20080104447 - Diagnostic repair system and method for computing systems: A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic application is provided with access to the file system of the failed O/S image. The diagnostic software application collects relevant configuration information from... Agent: Scully, Scott, Murphy & Presser, P.C.

20080104451 - Bootable post crash analysis environment: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104453 - System and method to detect errors and predict potential failures: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults... Agent: Kenyon & Kenyon LLP

20080104455 - Software failure analysis method and system: A software failure analysis method for use following detection of a software failure on a computing system. The method includes collecting local data from the computing system pertaining to the failure, sending a request for comparison data to at least one other computing system, the request characterizing the comparison data... Agent: Hewlett Packard Company

20080104456 - Memory system including asymmetric high-speed differential memory interconnect: A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080104457 - Semiconductor integrated circuit device for display controller: The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area, and a repair circuit capable of repairing a... Agent: Miles & Stockbridge PC

20080104458 - Semiconductor memory, system, testing method for system: A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and mounted in the same package. Therefore, when different types of memory chips are mounted... Agent: Arent Fox LLP

20080104460 - Medium defect detector and information reproducing device: A reproducing device performs error correction, detects a medium defect at an early stage and performs erasure correction. A reproducing device having an error correction circuit is provided with a medium defect detector. The medium defect detector computes a moving average value of the reproducing signal, slices this moving average... Agent: Greer, Burns & Crain

20080104459 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080104461 - Ate architecture and method for dft oriented testing: An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and... Agent: Verigy, Ltd.

20080104463 - Method and system for testing chips: Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal... Agent: North America Intellectual Property Corporation

20080104462 - Serializer/de-serializer bus controller inferface: An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed... Agent: Kathy Manke Avago Technologies Limited

20080104464 - Method and apparatus for controlling access to and/or exit from a portion of scan chain: The present invention provides a method, apparatus and program product for providing controlled access to and/or exit from a portion of a scan chain. The method, apparatus, and program product take advantage of a first controlling device placed within the scan chain prior to the portion of the scan chain... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080104465 - Failure simulation based on system level boundary scan architecture: A method and apparatus for reducing cost for the backplane and system test and for speeding up the time to market of a new product is disclosed. A failure simulation based on system level Boundary Scan architecture allows the use of an already available test infrastructure.... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20080104466 - Method and apparatus for testing embedded cores: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to... Agent: Fish & Richardson, PC

20080104467 - Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereo: A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be... Agent: Staas & Halsey LLP

20080104468 - Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.... Agent: Patentry

20080104469 - Apparatus and method for using a single bank of efuses to successively store testing data from multiple stages of testing: An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080104471 - Method and apparatus for testing an ic device based on relative timing of test signals: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC... Agent: Hewlett Packard Company

20080104470 - Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test: A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test, includes: 1) for each of the plurality of faults, and for each of a plurality of... Agent: Agilent Technologies Inc.

20080104472 - Parameter setting with error correction for analog circuits: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of... Agent: Koppel, Patrick & Heybl

20080104473 - Rendering and correcting data: Rendering and correcting data. Data is received. The data is stored at a memory. The data is rendered for presentation at an output device. Defects in the data stored at the memory are determined. The defects in the data stored at the memory are corrected, wherein at least a portion... Agent: Hewlett Packard Company

20080104474 - Low density parity check (ldpc) decoder: A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter demodulates the down-converted signal and provides a demodulated signal to the LDPC decoder. The LDPC decoder has a partially parallel architecture... Agent: Joseph J. Laks Thomson Licensing LLC

20080104475 - Method and apparatus for encoding and decoding high speed shared control channel: A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding,... Agent: Volpe And Koenig, P.C. Dept. Icc

20080104477 - Method for performing error corrections of digital information codified as a symbol sequence: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is... Agent: Stmicroelectronics, Inc.

20080104476 - Method, system, and apparatus for adjacent-symbol error correction and detection code: A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases.... Agent: Caven & Aghevli C/o Intellevate

20080104478 - Method and system for providing a contention-free interleaver for channel coding: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, {right arrow over (v)}, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave... Agent: Docket Clerk

20080104479 - Symbol error correction by error detection and logic based symbol reconstruction: Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more symbols in error and the location of such symbols in error. Methods to reconstruct symbols in error from other... Agent: Diehl Servilla LLC

20080104481 - Encoding device, decoding device, encoding/decoding device and recording/reproducing device magnetic head and method of producing the same: An encoding/decoding device corrects errors by concatenated codes of an ECC code and a parity code to prevent an increase in the circuit scale and to improve error correction performance. The device has encoders for creating a concatenation type encoded data by interleaving a data string into a plurality of... Agent: Greer, Burns & Crain

20080104480 - Method for processing noise interference: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a... Agent: Birch Stewart Kolasch & Birch

20080104482 - Turbo decoder employing arp (almost regular permutation) interleave and arbitrary number of decoding processors: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still... Agent: Garlick Harrison & Markison

20080104483 - Error corrector with a high use efficiency of a memory: An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory access. The input buffer receives and temporarily stores a coded blockcode data, and writes the... Agent: Bacon & Thomas, PLLC

20080104484 - Mass storage system and method: There is provided a system and method of mass storage. The method includes dividing storage units into standard sized blocks and upon receiving a write request from an application, generating EDC data for user application data associated with the write request. The method also includes compressing the user application data... Agent: Hewlett Packard Company

20080104485 - Data communications methods and apparatus: In an embodiment, a source device encodes source information corresponding to a frame, assembles an initial data frame that includes the encoded data blocks, and transmits the initial data frame to a destination device. The destination device decodes the encoded data blocks and assembles a restored version of the initial... Agent: Schwegman, Lundberg & Woessner, P.A.

20080104486 - Decoder and reproducing device: A reproducing device performs decoding by propagating the reliability, and detects micro medium defects to correct the reliability information. The decoder has an internal decoder, external decoder and a defect detector which calculates a moving average value of a soft-input signal, acquires a scaling factor from this, and manipulates the... Agent: Greer, Burns & Crain

20080104487 - Error detection apparatus and error detection method: When error bit position information EbP sequentially selected from a register 51 is an error bit position, such a syndrome that an LSB of an error byte position is an error bit position is output from a syndrome storage unit 52 to an adder 54 and added and stored in... Agent: Staas & Halsey LLP

20080104488 - Sliding window method and apparatus for soft input/soft output processing: In one or more embodiments, a method of processing a soft value sequence according to an iterative soft-input-soft-output (SISO) algorithm comprises carrying out sliding-window processing of the soft value sequence in a first iteration using first window placements and in a second iteration using second window placements, and varying the... Agent: Coats & Bennett, PLLC

20080104489 - Maximum likelihood detector, error correction circuit and medium storage device: A maximum likelihood decoder creates a decoding target data string and provides error candidates that are effective for an error correction circuit. The decoder has a detector for creating a decoding target data string, and an error candidate extractor for extracting the bit positions of which likelihood of each bit... Agent: Greer, Burns & Crain

20080104490 - Digital data decoding apparatus and digital data decoding method: According to one embodiment, a digital data decoding apparatus calculates branch metrics of all paths in an input data series from the path at a state of a current time to the path at a state of a next time, and obtains path metrics of all the paths up to... Agent: Knobbe Martens Olson & Bear LLP

20080104491 - Safe transmission using non-safety approved equipment: A communications method useable to safely communicate a message or a signal from a first safety approved entity (210) to a second safety approved entity (230) via a third, non-safety approved entity (220) comprising that each command is sent with the aid of a command message from the first to... Agent: Albihns Stockholm Ab

20080104492 - Data processing: A method of generating a checksum for a data message comprises processing the data message to extract data blocks therefrom and computing a checksum from the data blocks. In particular non-linear operators are applied to the data blocks. As a result improved fault-detection and speed of processing is obtained... Agent: Osha Liang L.L.P.

20080098262 - Performing diagnostic operations upon an asymmetric multiprocessor apparatus: An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10. A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a... Agent: Nixon & Vanderhye, PC

20080098263 - Test apparatus and method for testing booting and shutdown process of computer system: A test apparatus for testing a booting and shutdown process of a computer system provided. The test apparatus includes a power control unit and a test control unit. The power control unit is for receiving AC power, and selectively outputting the AC power to a power supply end of the... Agent: Bacon & Thomas, PLLC

20080098255 - Communication management apparatus and communication management method: A transmitting/receiving unit receives a SIP signal after occurrence of trouble in a SIP server and outputs a call ID of the SIP signal to a recovery-file searching unit. A session control unit once again procures a call process resource and an instance for a session corresponding to a recovery... Agent: Katten Muchin Rosenman LLP

20080098256 - Computer readable storage medium for migratable services: A migration framework provides for the migration of services in a cluster. A migratable target contains a list of servers in the cluster capable of hosting a migratable service. A migration manager can migrate the service between servers in the migratable target, and can activate an instance of the service... Agent: Fliesler Meyer LLP

20080098257 - Multiple execution-path system: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the... Agent: Quarles & Brady LLP

20080098258 - Method, system, and program for error handling in a dual adaptor system where one adaptor is a master: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098259 - Method, system, and program for error handling in a dual adaptor system where one adaptor is a master: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098260 - Methods and apparatus for handling processing errors in a multi-processing system: Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080098261 - Adaptive recovery from system failure for application instances that govern message transactions: Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication... Agent: Workman Nydegger/microsoft

20080098264 - Program debug method and apparatus: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to... Agent: George W Carr 670 Founders Square

20080098265 - System and method for embedded java memory footprint performance improvement: A system and method are provided to allow demand loading and discarding of Java executable image (JXE) files. The virtual machine allocates an address space for a requested JXE program. The read-only portion of the JXE file is memory mapped from its nonvolatile location to the allocated memory space using... Agent: Joseph T. Van Leeuwen

20080098266 - Reduced signaling interface method and apparatus: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a... Agent: Texas Instruments Incorporated

20080098267 - Semiconductor ic and testing method thereof: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit... Agent: Steptoe & Johnson LLP

20080098268 - Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.... Agent: Ibm Corporation C/o Sally Redfern

20080098269 - Mechanism for concurrent testing of multiple embedded arrays: In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to a plurality of arrays having different sizes to generate test packets targeted to an array with the most entries among... Agent: Intel/blakely

20080098270 - Method for determining time to failure of submicron metal interconnects: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080098271 - System and method for verification and generation of timing exceptions: The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing... Agent: 24ip Law Group Usa, PLLC

20080098272 - Networked test system: An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments.... Agent: Teradyne, Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080098273 - Method and apparatus for encoding and decoding data: A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block size KI is determined from a group of available non-contiguous FEC block sizes between Kmin and Kmax, and wherein... Agent: Motorola, Inc.

20080098274 - Data transmission apparatus and method: Provided are a data transmission apparatus and method which apply an appropriate coding rate according to significance of bits or bit groups included in uncompressed data and retransmit all or part of the data when a transmission error occurs in the data while the data is being transmitted over a... Agent: Sughrue Mion, PLLC

20080098275 - System and program product for error recovery while decoding cached compressed data: A system and program for decoding cached compressed data. Compressed data is received and decoded. An error is detected while decoding a first location in the compressed data. A reentry data set is accessed having a pointer to a second location in the compressed data following the first location and... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098276 - Semiconductor integrated circuit: The present invention provides a data transmission method capable of suppressing degradation in data rate while improving a bit error rate of transmission data, and transmitters and receivers employed in the data transmission method. On the transmitting side, a CRC bit is added to an input information bit sequence in... Agent: Volentine & Whitt PLLC

20080098277 - High density high reliability memory module with power gating and a fault tolerant address and command bus: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080098278 - Multiplier product generation based on encoded data from addressable location: For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that... Agent: Intel Corporation C/o Intellevate, LLC

20080098279 - Using no-refresh dram in error correcting code encoder and decoder implementations: Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC... Agent: Townsend And Townsend And Crew, LLP

20080098280 - N-dimensional iterative ecc method and apparatus with combined erasure - error information and re-read: In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error recovery procedure. The data read from the storage medium are represented as a multi-dimensional data structure, and the error... Agent: Schiff Hardin, LLP Patent Department

20080098281 - Using sam in error correcting code encoder and decoder implementations: SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder... Agent: Townsend And Townsend And Crew, LLP

20080098282 - High speed error correcting system: Disclosed is an error correcting system, which comprises: a demodulator, for receiving and demodulating data from the optical disc to generate input data; a data buffer, for storing the input data; an on the fly ECC decoder, for performing a PI error correction to the input data before the input... Agent: North America Intellectual Property Corporation

20080098283 - Outer coding methods for broadcast/multicast content and related apparatus: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by techniques that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM)... Agent: Qualcomm Incorporated

20080098284 - Systems, methods, apparatus, and computer program products for providing forward error correction with low latency: Systems, methods, apparatus and computer program products for providing forward error correction with low latency to live streams in networks are provided, including outputting source data at a rate less than the rate of a source stream, building a buffer, FEC decoding the source data; and outputting the packets at... Agent: Fitzpatrick Cella Harper & Scinto

20080098285 - Apparatus for random parity check and correction with bch code: An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in... Agent: Madson & Austin

20080098286 - Irregular systematic with serial concatenated parity codes: Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of bits using systematic bits as input, repeating the plurality of bits of the outer code a pre-determined number of times to generate at least... Agent: Fish & Richardson, PC

20080098287 - Detection and mitigation of temporary impairments in a communications channel: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses... Agent: Mcandrews Held & Malloy, Ltd

20080098288 - Forward decision aided nonlinear viterbi detector: A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal... Agent: Ropes & Gray LLP

20080091970 - Information processing system and method: In information processing between computers which perform a remote operation via a network, all or a part of process information being executed by an operation target and data for use in a process are transmitted beforehand to an operation unit, and the operation unit continues the processing by use of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080091972 - Storage apparatus: Proposed is a storage apparatus capable of alleviating the burden of maintenance work when a failure occurs in a part configuring the storage apparatus. This storage apparatus includes multiple disk drives and spare disk drives, and multiple controllers. When a failure occurs, this storage apparatus determines the operability status of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080091971 - Stored data processing apparatus, storage apparatus, and stored data processing program: A storage apparatus performs at least write processing for a storage medium. On the storage medium, data is allocated in units of a first block having a predetermined data length, the first block is allocated in units of a second block constituted by a plurality of the first blocks, and... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20080091974 - Device for controlling a multi-core cpu for mobile body, and operating system for the same: Temperatures of four CPU cores of a multi-core CPU of a mobile body are detected. If the detected temperatures of the CPU cores become high, a clock setting register in a CPU clock-forming unit is set to the highest multiplying factor, and the CPU clock multiplying factors of the other... Agent: Posz Law Group, PLC

20080091975 - Method and system for side-channel testing a computing device and for improving resistance of a computing device to side-channel attacks: Our invention presents an effective method and system which are used to perform side-channel testing of computing devices, as well as to improve resistance of computing devices against side-channel attacks.... Agent: Yevgeniy Polulyakh

20080091976 - Methods and apparatus for network re-creation in controlled environments: Methods and apparatus for network re-creation in controlled environments. In an aspect, a method for network re-creation is provided. The method includes determining a logging window, logging at least one re-creation parameter during the logging window to produce a re-creation log, and storing the re-creation log. In an aspect, an... Agent: Qualcomm Incorporated

20080091978 - Apparatus, system, and method for database management extensions: An apparatus, system, and method are disclosed for evaluating database accesses. The apparatus may comprise a computer program that causes a computer system to exchange profiling data between a client application module and a database module; execute a database access; determine a database access policy violation at a detection point... Agent: Kunzler & Mckenzie

20080091981 - Process for improving design-limited yield by localizing potential faults from production test data: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based... Agent: Patentry

20080091983 - Dynamic account provisions for service desk personnel: The present invention describes an automated process that enables dynamic provisioning (both creation and deletion) of administrative accounts based upon a real-time need as defined by service desk processes and procedures. This invention enhances current provisioning of administrative account processes that are typically handled by service desk personnel that constantly... Agent: Ibm Corporation C/o Darcell Walker, Attorney At Law

20080091969 - Semiconductor integrated circuit including memory macro: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080091973 - Configuring cache memory from a storage controller: Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first cluster including a first processor and a first cache, and a second cluster including a second processor and a second cache.... Agent: Scully, Scott, Murphy, & Presser, P.C.

20080091977 - Methods and apparatus for data analysis: Methods and apparatus for data analysis according to various aspects of the present invention identify statistical outliers in data, such as test data for components. The outliers may be identified and categorized according to the distribution of the data. In addition, outliers may be identified according to multiple parameters, such... Agent: Noblitt & Gilmore, LLC.

20080091979 - Semiconductor memory device and test method: A semiconductor device includes memory mats each including a plurality of memory cells to store information code or error correcting code. An error correcting circuit corrects an error of the information code by one correction unit of a predetermined number of information codes. A parallel test mode activates and tests... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080091980 - Method and system for validating pci/pci-x adapters: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20080091982 - Storage controller and a method for recording diagnostic information: A storage controller (104) for a storage system (100) in which there are multiple storage devices (109) and a method for recording diagnostic information are provided. The storage controller (104) includes a storage device manager (203) which has means for allocating a storage device (109) in the storage system (100)... Agent: Dillon & Yudell, LLP

20080091984 - Method and system for concurrent error identification in resource scheduling: A method and system for handling real-time indications of resource scheduling conflicts. In one embodiment, the method includes a computer system including a user interface, display, processor, and some form of memory. Contained within the memory is a resource scheduling process that analyzes resource data, scheduling criteria, and work parameters... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080091985 - System and method for capturing significant events at web portlets: System and method for logging significant events occurring at a web site portal includes a base class portlet service including a significant event catcher method having a register method and a record method, a portlet action table, and an action description table. The register method is called during portlet initialization... Agent: Shelley M Beckstrand, P.C.

20080091986 - Method and apparatus for encoding and decoding data: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K′ is determined that is related to K″, where K″ from a set of sizes; wherein the set of sizes comprise K″=ap×f, pmin≦p≦pmax; fmin≦f≦fmax,... Agent: Motorola, Inc.

20080091987 - Circuit designing program and circuit designing system having function of test point insetion: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for... Agent: Mcginn Intellectual Property Law Group, PLLC

20080091988 - Memory repair system and method: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory... Agent: Harness, Dickey & Pierce P.L.C

20080091989 - System and method for testing memory blocks in an soc design: A system and method for testing a plurality of memory blocks in a System on Chip (SOC) design uses two Test Access Ports (TAPs), a user TAP and an EDA tool TAP, to provide instructions and test data to the SOC. The system includes a glue logic block, a secured... Agent: Freescale Semiconductor, Inc. Law Department

20080091990 - Controlled reliability in an integrated circuit: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable... Agent: Freescale Semiconductor, Inc. Law Department

20080091991 - Method and apparatus for performing logical compare operation: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on... Agent: Trop Pruner & Hu, PC

20080091993 - On-board fifo memory module for high speed digital sourcing and capture to/from dut (device under test) using a clock from dut: In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater... Agent: Texas Instruments Incorporated

20080091992 - Tri-level test mode terminal in limited terminal environment: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input... Agent: Zagorin O'brien Graham LLP

20080091994 - Test system for integrated circuits: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080091995 - Progressive random access scan circuitry: A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one... Agent: Brinks Hofer Gilson & Lione

20080091996 - Single event upset test circuit and methodology: A method, involving: inputting an initial data pattern into a scan chain circuit of an integrated circuit device; applying a particle beam to the integrated circuit device, while driving the scan chain circuit with a clock signal, to generate an output data pattern; and generating a single event upset error... Agent: Bainwood Huang & Associates LLC

20080091997 - Systems and methods for improved scan testing fault coverage: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic... Agent: Law Offices Of Mark L. Berrier

20080091998 - Partial enhanced scan method for reducing volume of delay test patterns: A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells... Agent: Nec Laboratories America, Inc.

20080091999 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the... Agent: Ibm Corporation Department 417

20080092000 - Delay circuit, jitter injection circuit, and test apparatus: There is provided a delay circuit that delays and outputs a given input signal. The delay circuit includes a first delaying section that delays the input signal, a second delaying section that further delays the input signal delayed by the first delaying section, and a delay setting section that sets... Agent: Smith, Gambrell & Russell

20080092001 - Method and device for data communication: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control... Agent: GlobalIPServices, PLLC

20080092002 - Semiconductor integrated circuit and control method thereof: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node... Agent: Mcginn Intellectual Property Law Group, PLLC

20080092003 - Diagnostic information capture from logic devices with built-in self test: From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured... Agent: Agilent Technologies Inc.

20080092004 - Method and system for automated path delay test vector generation from functional tests: Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20080092005 - Scan testing interface: A system, method, and computer program product for scan testing a device under test (DUT). In one embodiment, compressed test data comprising packets are received at a serial test data input. The packets contain encoded data characterizing a test data bit stream and each includes a bucket select field and... Agent: Dillon & Yudell LLP

20080092006 - Optimizing a set of lbist patterns to enhance delay fault coverage: A method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. The method includes, but is not limited to: creating a set of customized LBIST activation patterns during IC design; propagating the activation patterns from the scan-able latches through the non-scan latches to... Agent: Dillon & Yudell LLP

20080092007 - Data communication device and method: A method is described for transferring data from an unsecured computer to a secured computer. The method includes transmitting the data and then receiving the data. Next, it is determined if errors were introduced when the data was transmitted by the unsecured computer or received by the secured computer. If... Agent: Sughrue Mion, PLLC

20080092008 - Buffer compression in automatic retransmisson request (arq) systems: A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length... Agent: Synnestvedt & Lechner, LLP

20080092010 - Error correction code decoding device: An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and... Agent: Young & Thompson

20080092011 - Turbo decoding apparatus: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation... Agent: Bingham Mccutchen LLP

20080092009 - Error correction coding apparatus and error correction decoding apparatus: An error correction coding apparatus includes a frame generating unit for buffering inputted information sequence data in frame buffers which correspond to units to be coded, respectively, a first interleaving unit for rearranging the information sequence data within two or more of the frame buffers, a first coding unit for... Agent: Birch Stewart Kolasch & Birch

20080092012 - Robust digital communication system: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust... Agent: Zenith Electronics Corporation

20080092013 - System and method for interleaving data in a communication device: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080092014 - Methods of adapting operation of nonvolatile memory: In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one... Agent: Winston & Strawn, LLP

20080092015 - Nonvolatile memory with adaptive operation: In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one... Agent: Winston & Strawn, LLP

20080092016 - Memory system and method using partial ecc to achieve low power refresh and fast access to data: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080092017 - Erasure pointer error correction: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.

20080092018 - Tail-biting turbo code for arbitrary number of information bits: Tail-biting turbo code for arbitrary number of information bits. A novel means is presented in which, for most cases, no extra symbols at all need to be padded to an input sequence to ensure that a turbo encoder operates according to tail-biting (i.e., where the beginning and ending state of... Agent: Garlick Harrison & Markison

20080092019 - Supporting a decoding of frames: For supporting a decoding of encoded frames, which belong to a sequence of frames received via a packet switched network, it is detected whether a particular encoded frame has been received after a scheduled decoding time for the particular encoded frame and before a scheduled decoding time for a next... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080092020 - Determining message residue using a set of polynomials: A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Portfolio Ip

20080092021 - System and method for performing reed-solomon encoding: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080092022 - Non-redundant multi-error correcting binary differential demodulator: An algorithm for a non-redundant multi-error correcting binary differential demodulator simplifies error detection and reduces memory requirements in circuits embodying the same. The demodulator includes a differential detectors (DD) module, an error signal generator (ESG) module, and an error detection-and-correction (EDAC) module. The DD module receives modulated binary input at... Agent: Albin H. Gess, Esq. Snell & Wilmer L.L.P.

20080092023 - Parallel convolutional encoder: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel... Agent: Stolowitz Ford Cowger LLP

20080092024 - System for identifying localized burst errors: A system for detecting one or more localized burst errors in a receiving message comprised of a plurality of codewords. The system comprises a trellis code decoder for decoding a receiving message with a plurality of codewords and calculating one or more cumulative metrics of a maximum likelihood path and... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080092025 - Method and system for improving decoding efficiency in wireless receivers: The present invention discloses a method and system for improving the decoding efficiency in a wireless receiver to obtain a correct decoded data string. The method comprises generating an active state metric matrix of a receiving codeword, calculating a