|Error detection/correction and fault detection/recovery patents - Monitor Patents|
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Error detection/correction and fault detection/recoveryBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 12/05/2013 > 61 patent applications in 37 patent subcategories.
20130326260 - Automated disaster recovery system and method: Methods and systems for recovering a host image of a client machine to a recovery machine comprise comparing a profile of a client machine of a first type to be recovered to a profile of a recovery machine of a second type different from the first type, to which the... Agent:
20130326261 - Failover of interrelated services on multiple devices: A device may include a network interface for communicating with a failover device, a memory for instructions, and a processor for executing the instructions. The processor may execute the instructions to communicate with the failover device, via the network interface, to fail over the device to the failover device in... Agent: Verizon Patent And Licensing Inc.
20130326262 - Methods and systems for automatically rerouting logical circuit data from a logical circuit failure to a dedicated backup circuit in a data network: An example method of rerouting data involves rerouting a logical circuit from a first set of switches to a second set of switches to communicate data between network devices without breaking the logical circuit. The logical circuit comprises variable communication paths. The second set of switches is to form a... Agent: At&t Intellectual Property I, L.p.
20130326269 - Apparatus, system and method for managing solid-state retirement: A storage controller is configured to determine a reliability metric of a storage division of a solid-state storage medium based on one or more test read operations. The storage division may be retired based on the reliability metric and/or the age of the data on the storage division. A storage... Agent: Fusion-io, Inc.
20130326268 - Repair control circuit and semiconductor integrated circuit using the same: A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the... Agent: Sk Hynix Inc.
20130326263 - Dynamically allocatable memory error mitigation: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The... Agent:
20130326264 - Resolution of a storage error in a dispersed storage network: A method begins by a dispersed storage (DS) processing module identifying an encoded data slice having an error, where a storage unit of a dispersed storage network (DSN) stores the encoded data slice. The method continues with the DS processing module sending a lock command to the storage unit. The... Agent: Cleversafe, Inc.
20130326270 - Maximizing use of storage in a data replication environment: Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition... Agent: International Business Machines Corporation
20130326266 - Maximizing use of storage in a data replication environment: Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition... Agent: International Business Machines Corporation
20130326267 - Semiconductor device and operating method thereof: A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when... Agent:
20130326265 - Systems and methods for disaster recovery of multi-tier applications: A computer-implemented method for disaster recovery of multi-tier applications may include 1) identifying a multi-tier application that is provisioned with a plurality of production clusters at a production site, 2) identifying a disaster recovery site including a plurality of recovery clusters, 3) identifying, at the disaster recovery site, a failure... Agent: Symantec Corporation
20130326271 - Handling of initially unexecutable instructions: According to example configurations, a monitor resource monitors hardware executing a software program. In response to detecting occurrence of a failure associated with an attempted execution of a given software instruction in the software program, the hardware generates a notification. The monitor resource receives the signal generated by the hardware.... Agent:
20130326272 - Storage system and method of operating thereof: Storage system(s) for storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include: upon start of a storage recurrence, destaging dirty data which had been accommodated in the cache memory prior to the start of... Agent: Infinidat Ltd.
20130326273 - Virtual repair of digital media: Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of... Agent: Xerox Corporation
20130326274 - Method for transferring and confirming transfer of predefined data to a device under test (dut) during a test sequence: A method for testing a device under test (DUT) during a test sequence. In accordance with one embodiment, during a regular, pre-defined test sequence, data packets are transferred from a tester to a device under test (DUT) containing data related to at least one of an identification parameter of the... Agent: Litepoint Corporation
20130326275 - Hardware platform validation: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel... Agent:
20130326277 - Data lifecycle management: A method, system and computer program product for data lifecycle management is provided. A method for managing metrics from a monitored system comprises: identifying a fault from the monitored system; identifying from the monitored system, one or more metrics are that are directly related to the fault and one or... Agent:
20130326276 - Method and apparatus for correlating input and output messages of system under test: A method and apparatus for determining correlation between input and output messages in a system under test (SUT) is provided in the present invention. The SUT is provided with preset watch-points, and the running of the SUT is detected by triggering watch-points in a test platform at its run time.... Agent: International Business Machines Corporation
20130326278 - Server and method of manipulation in relation to server serial ports: A server in communication with a remote control device and a display device includes a super input/output (SIO) microchip, a basic input/output system (BIOS), and a baseboard management controller (BMC). The SIO microchip outputs debugging commands and IPMI commands. The BMC includes a setting module, receiving module, and a transmitting... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd
20130326279 - Resource planning for data protection validation: A solution for validating a set of data protection solutions is provided. A validation scenario can be defined, which can include data corresponding to a set of attributes for the validation scenario. The attributes can include a time frame for the validation scenario. The validation scenario also can include a... Agent: International Business Machines Corporation
20130326280 - Debugging method, chip, board, and system: Embodiments of the present invention provide a debugging method, a chip, a board, and a system and relate to the communications field. Remote debugging can be performed on a board having no main control CPU without affecting hardware distribution and software performance. The method includes: receiving, by an Ethernet port,... Agent: Huawei Technologies Co., Ltd.
20130326282 - Debug in a multicore architecture: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread... Agent: Synopsys, Inc.
20130326283 - Debug in a multicore architecture: A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread... Agent: Synopsys, Inc.
20130326281 - X-tracer: a reconfigurable x-tolerance trace compressor for silicon debug: An apparatus and method for compressing trace data containing unknown (X) bits in trace-based silicon debug, wherein redundant and/or reconfigurable MISRs and a non-X signature extraction algorithm are used to produce non-X signature that contains a maximized number of known (non-X) information bits.... Agent:
20130326284 - Apparatus, system, and method for managing solid-state storage reliability: A storage controller may be configured to assess the reliability of a solid-state storage medium. The storage controller may be further configured to project, forecast, and/or estimate storage reliability at a future time. The projection may be based on a currently reliability metric of the storage and a reliability model.... Agent: Fusion-io, Inc.
20130326286 - Data transfer apparatus and data transfer method: A data transfer apparatus includes a plurality of transmitting units. The data transfer apparatus includes a detecting unit that detects a malfunction in any of the transfer paths. The data transfer apparatus includes a selecting unit that, when one or more malfunctions have been detected by the detecting unit, selects... Agent: Fujitsu Limited
20130326288 - Processor that detects when system management mode attempts to reach program code outside of protected space: A method is described that includes detecting that a memory access of system management mode program code is attempting to reach program code outside of a protected region of memory by comparing a target memory address of a memory access instruction of the system management program code again information that... Agent:
20130326287 - Programmable logic controller: A programmable logic controller of the invention comprises: a CPU unit; various kinds of units controlled by the CPU unit and coupled via common connectors, that is, input/output units, an end cover, a branch unit and an extension unit; an internal bus provided extending through the CPU unit and the... Agent: Mitsubishi Electric Corporation
20130326285 - Stress-based techniques for detecting an imminent read failure in a non-volatile memory array: A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at... Agent: Freescale Semiconductor, Inc.
20130326289 - Method and system for detection of latent faults in microcontrollers: Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with... Agent: Infineon Technologies Ag
20130326290 - System and method for execution of user-defined instrument command sequences using multiple hardware and analysis modules: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and... Agent: Litepoint Corporation
20130326291 - System and method for execution of user-defined instrument command sequences using multiple hardware and analysis modules: A system and method for the execution of a program comprises a user-defined sequence of standard hardware and analysis module commands of an instrument, in the context of a tester comprising a plurality of VSAs and VSGs, or other hardware measurement modules types, where the coordination of command execution and... Agent:
20130326294 - 3-d memory and built-in self-test circuit thereof: A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit... Agent: Industrial Technology Research Institute
20130326292 - Memories and methods for performing column repair: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell... Agent: Micron Technology, Inc.
20130326293 - Memory error test routine: An error test routine is to test for a type of memory error by changing a content of a memory module. A memory handling procedure is to isolate the memory error in response to a positive outcome of the error test routine. The error test routine and memory handling procedure... Agent:
20130326295 - Semiconductor memory device including self-contained test unit and test method thereof: A semiconductor memory device is configured to internally perform a test operation utilizing a random data pattern. The semiconductor memory device includes a random data pattern test unit that operates under control of on-board control logic that also manages normal operation of the semiconductor memory device. The control logic controls... Agent: Sk Hynix Inc.
20130326296 - Nonvolatile memory device and error correction methods thereof: A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller.... Agent: Samsung Electronics Co., Ltd.
20130326297 - Semiconductor apparatus: A semiconductor apparatus includes a control signal generation unit configured to generate a control signal in response to a set signal, a test signal and a test reset signal; a first test selection unit configured to generate a first test mode signal in response to a first select signal and... Agent: Sk Hynix Inc.
20130326298 - Boundary scan path method and system with functional and non-functional scan cell memories: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells... Agent: Texas Instruments Incorporated
20130326300 - Termination circuit, semiconductor device, and test system: A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function... Agent: Fujitsu Limited
20130326299 - Tester hardware: A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to... Agent:
20130326301 - Methods for providing for correcting data and associated apparatus: The apparatus and methods allow for correcting data from a sensor due to changes in relative speed of that sensor. The methods and apparatus described use a determined entropy from data associated with across a direction of travel of the sensor together with a determined entropy from data associated with... Agent: Senergy Technology Limited
20130326302 - Error injection for ldpc retry validation: The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data... Agent: Lsi Corporation
20130326303 - Providing capacity optimized streaming data with forward error correction: In an example embodiment, there is described herein a methodology were the Forward Error Correction (FEC) data for a data stream is distributed into a plurality of FEC sub-streams. Subscribers to the data stream indicate which of the plurality of FEC sub-streams should be provided to them. The distribution of... Agent: Cisco Technology, Inc.
20130326304 - Error detection or correction of a portion of a codeword in a memory device: Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.... Agent: Micron Technology, Inc.
20130326305 - Data format using an efficient reverse concatenated modulation code for magnetic tape recording: In one embodiment, a tape drive system includes a write channel for writing data to a magnetic tape, the write channel utilizing a rate-(232/234) reverse concatenated modulation code. The write channel includes logic adapted for receiving a data stream comprising one or more data sets, logic adapted for separating each... Agent: International Business Machines Corporation
20130326307 - Methods for partial reverse concatenation for data storage devices using composite codes: In one embodiment, a method includes writing data to a storage medium of a data storage system using a partial reverse concatenated modulation code by encoding data sets using a C2 encoding scheme, adding a header to each subunit of the data sets, encoding the headers of the data sets... Agent: International Business Machines Corporation
20130326306 - Partial reverse concatenation for data storage devices using composite codes: In one embodiment, a data storage system includes a write channel for writing data to a storage medium, the write channel configured to utilize a partial reverse concatenated modulation code. The write channel includes logic adapted for encoding data sets using a C2 encoding scheme, logic adapted for adding a... Agent: International Business Machines Corporation
20130326308 - Partial packet recovery in wireless networks: Systems and methods for improved packet throughput using partial packets are provided in which data recovery of partial packets of a plurality of received coded packets is performed across the plurality of received coded packets. The plurality of received coded packets, including the received partial packets, can be buffered in... Agent: Massachusetts Institute Of Technology
20130326310 - Selective error control coding in memory devices: A method includes determining that a received data stream includes metadata and content, applying error control coding to the received metadata, disabling error control coding for the received content, and storing the metadata, the error control coding, and the content in a memory device.... Agent: Micron Technology, Inc.
20130326309 - Semiconductor device and driving method thereof: A data saving period control circuit; a power gating control circuit; and a data processing circuit including a general-purpose register, an error correction code storage register, and an error correction code circuit are included. The general-purpose register and the error correction code storage register each include a volatile memory unit... Agent: Semiconductor Energy Laboratory Co., Ltd.
20130326311 - Magnetic tape recording in data format using an efficient reverse concatenated modulation code: In one embodiment, a method for writing data to a magnetic tape utilizing a rate-(232/234) reverse concatenated modulation code includes receiving a data stream comprising one or more data sets, separating each data set into a plurality of sub data sets, encoding each sub data set with a C2 encoding,... Agent: International Business Machines Corporation
20130326312 - Storage device including non-volatile memory device and repair method: Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page... Agent:
20130326313 - Method and system to improve the performance and/or reliability of a solid-state drive: A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold,... Agent:
20130326314 - Nonvolatile memory device and related read method using hard and soft decision decoding: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a... Agent: Samsung Electronics Co., Ltd.
20130326315 - Evaluation of polynomials over finite fields and decoding of cyclic codes: An apparatus and method are disclosed for evaluating an input polynomial (p(x)) in a (possibly trivial) extension of the finite field of its coefficients, which are useful in applications such as syndrome evaluation in the decoding of cyclic codes. The apparatus comprises a decomposition/evaluation module (110) configured to iteratively decompose... Agent: Universitat Zurich
20130326317 - Methods and apparatus for temporarily storing parity information for data stored in a storage device: Methods and apparatus for temporarily storing parity information for data stored in a storage device are provided. A first data block and parity information associated with the first data block are received. The first data block is stored in a first region of the storage device. The parity information is... Agent:
20130326316 - Systems and methods for improved data detection processing: The present invention is related to systems and methods for enhancing data detection in a data processing system.... Agent: Lsi Corporation
20130326318 - Enhanced checksum system: Generating data checksum for a data object including multiple data units comprises, for each data unit, obtaining a corresponding address of the data unit, and rotating the data unit based on said corresponding address of the data unit to generate a rotated data unit. A checksum value for the data... Agent: Samsung Electronics Co., Ltd.
20130326320 - Method and apparatus for indicating a temporary block flow to which a piggybacked ack/nack field is addressed: A method and an apparatus for indicating a temporary block flow (TBF) to which a piggybacked acknowledgement/non-acknowledgement (PAN) field is addressed. A method and apparatus of performing receive processing to reduce the probability of false acceptance of erroneous PANs are also disclosed. A transmit station generates a PAN check sequence... Agent: Interdigital Technology Corporation
20130326319 - Telecommunications methods for increasing reliability of early termination of transmission: An embodiment of the invention provides a telecommunications method performed by a second telecommunications device. According to the embodiment, the second telecommunications device first tries to use a received part of a data block to decode the data block, wherein the received part is received from a first telecommunications device.... Agent: Mediatek Inc.11/28/2013 > 33 patent applications in 21 patent subcategories.
20130318392 - Information processing apparatus, control method: An information processing apparatus includes a memory, and a processor that executes a process in the memory. The process includes detecting a sign of a fault of a storage device that prohibits write access to a storage area of the storage device and permits read access to the storage area... Agent: Fujitsu Limited
20130318391 - Methods for managing failure of a solid state device in a caching storage: Techniques for managing caching use of a solid state device are disclosed. In some embodiments, the techniques may be realized as a method for managing caching use of a solid state device. Management of the caching use may include receiving, at a host device, notification of failure of a solid... Agent: Stec, Inc.
20130318394 - Embedded controller firmware management: An embedded controller includes and a microprocessor coupled to the memory. The memory includes a working area for storing embedded controller firmware and a recovery area for storing a copy of the embedded controller firmware. When the embedded controller firmware stored in the working area is corrupt, the microprocessor retrieves... Agent: Hon Hai Precision Industry Co., Ltd.
20130318395 - Reconstructing codewords using a side channel: Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for decoding codewords using a side channel. In various embodiments, a memory controller may be configured to determine that m of n die of non-volatile memory (“NVM”) have failed iterative decoding. In various embodiments, the memory controller... Agent:
20130318393 - Solid-state mass storage device and methods of operation: A volatile memory-based solid-state mass storage device adapted for use in a host system as a storage tier. The storage device includes a substrate on which is mounted a system interface, a control circuitry, and a plurality of substantially identical random access memory components that define at least one memory... Agent: Ocz Technology Group Inc.
20130318396 - Runtime configuration checks for composite applications: The embodiments provide a data processing apparatus including a runtime check identifier configured to determine, in response to a request to execute a function of the application, whether a runtime check descriptor corresponding to the function is stored in a database and select the runtime check descriptor if the runtime... Agent: Sap Ag
20130318397 - Automated build, deploy, and testing environment for firmware: Systems and methods for automating the building, deployment, and testing of firmware are disclosed. An exemplary system includes a build-deploy-testing environment. The build-deploy-testing environment can access a hardware testing profile that includes hardware specifications for a test server, an operating system for a test server, an application for the test... Agent:
20130318400 - Electronic device, system, and method for testing exception handling mechanism: A method for testing exception handling mechanism of an electronic device, the method includes: establishing a connection between the electronic device and another electronic device when the electronic device is booting up. Obtaining parameters of a timer of the electronic device in response to an operation of a user, and... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
20130318398 - Method and system for leveraging page fault and page reclaim capabilities in debugging: An exemplary system may include debug capabilities. In one embodiment, the system obtains a debug address. For a process associated with the system, the system determines whether a memory page used by the process includes the debug address. Upon determining that the memory page used by the process includes the... Agent: Red Hat, Inc.
20130318401 - Register error protection through binary translation: Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than... Agent:
20130318399 - Validation of a system using a design of experiments processing technique: A validation system includes a test block that operates to apply a set of inputs to a system under test, such as a test system or an executable test algorithm, and receive from said system under test a first set of outputs produced by operation of the system under test... Agent: Stmicroelectronics, Inc.
20130318403 - Integrated circuit including clock controlled debugging circuit and system-on-chip including the same: An integrated circuit includes a processor core, a clock control circuit and a debugging circuit. The processor core processes target software. The clock control circuit determines whether an electrical connection exists between the processor core and an external debugger and generates a determination result. The clock control circuit generates an... Agent: Samsung Electronics Co., Ltd.
20130318402 - Software systems testing interface: A system includes a manager module that oversees execution of a business process by a test module. The business process includes a plurality of process steps, and the test module comprises a plurality of test cases, a plurality of software test tools, and a plurality of parameters. The test module... Agent: Sap Ag
20130318404 - Dynamic administration of component event reporting in a distributed processing system: Methods, systems and products are provided for dynamic administration of component event reporting in a distributed processing system including receiving, by an events analyzer from an events queue, a plurality of events from one or more components of the distributed processing system; determining, by the events analyzer in dependence upon... Agent: International Business Machines Corporation
20130318405 - Early fabric error forwarding: An embodiment includes a processor, included in a first die, detecting a first hardware error (e.g., memory corruption error). The processor formulates a first error message based on the detected first error. The processor may forward the first error message, via a first fabric included on the first die, to... Agent:
20130318406 - Communication device using plurality of communication paths: There are included an opposite-side transmitter unit for transmitting the same messages to plural communication paths, respectively; and a host-side receiver unit for receiving the messages flowing through the plural communication paths, respectively; wherein, the receiver unit, compares the plural received messages to perform verification using error-detection code on any... Agent: Mitsubishi Electric Corporation
20130318407 - Test mode signal generation circuit: A test mode signal generation circuit includes a pre-decoder block configured to output first and second control signals and test address signals in response to first and second address signals, and a signal generation block configured to decode the test address signals in response to the first control signal and... Agent: Sk Hynix Inc.
20130318408 - Processor device with instruction trace capabilities: A processor device with debug capabilities has a central processing unit, debug circuitry including a trace module and an external interface, wherein the trace module generates a trace stream including information about executed instructions, wherein the trace stream is output through the external interface, and wherein the trace module is... Agent: Microchip Technology Incorporated
20130318409 - Core circuit test architecture: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each... Agent: Texas Instruments Incorporated
20130318413 - Dual mode test access port method and apparatus: Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE)... Agent: Texas Instruments Incorporated
20130318410 - Removing scan channel limitation on semiconductor devices: A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit... Agent: Cisco Technology, Inc.
20130318411 - Scan test method and apparatus: The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures... Agent: Texas Instruments Incorporated
20130318412 - Test access port with address and command capability: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses... Agent: Texas Instruments Incorporated
20130318414 - System, method and computer-accessible medium for design for testability support for launch and capture of power reduction in launch-off-capture testing: Exemplary system, method and computer accessible medium that can transform a circuit by selecting at least one scan cell as an interface register and inserting a shadow register into each interface register. Operations can be shifted to load and unload at least one scan cell in the circuit. An operation... Agent: New York University
20130318415 - Test system having a sub-system to sub-system bridge: A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and... Agent: At&t Intellectual Property I, L.p.
20130318416 - Rate matching and channel interleaving for a communications system: A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated... Agent:
20130318417 - Modification of error statistics behind equalizer to improve inter-working with different fec codes: This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which... Agent: Cisco Technology, Inc.
20130318418 - Adaptive error correction for phase change memory: Subject matter disclosed herein relates to memory operations regarding error correction or error detection.... Agent: Micron Technology, Inc.
20130318420 - Code modulation encoder and decoder, memory controller including them, and flash memory system: Disclosed is a bit-state mapping method of a flash memory system which maps m-bit data (m being a natural number more than 2) onto one of 2m states (voltage threshold distributions). The bit-state mapping method includes performing a subset partitioning operation during first to (m−1)th levels under a condition that... Agent:
20130318419 - Flash memory system including read counter logic: A flash memory system which includes a flash memory and a memory controller. The flash memory is configured to perform a read operation using a plurality of read levels. The memory controller is configured to recover original data using a counter value provided from the flash memory. The flash memory... Agent:
20130318421 - Method and apparatus for a parameterized interleaver design process: A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined,... Agent: Hughes Network Systems. LLC
20130318422 - Read level adjustment using soft information: A method for calibrating read levels in a flash memory device is provided. The method includes receiving read information from flash memory in response to a read command, assigning soft information to the received read information, determining an error signal based on the assigned soft information, determining a read level... Agent: Stec, Inc.
20130318423 - Mis-correction and no-correction rates for error control: An embodiment is a method for encoding data with an error correction code. The method includes receiving a first number of data symbols by a memory controller, receiving a second number of meta-data sub-symbols, generating a third number of check symbols using an ECC, where the third number includes a... Agent: International Business Machines Corporation11/21/2013 > 39 patent applications in 27 patent subcategories.
20130311820 - Forecasting workload transaction response time: Reliability testing can include determining a transaction time for each of a plurality of transactions to a system under test during the reliability test, wherein the plurality of transactions are of a same type. Forecasts of transaction times can be calculated for the transaction type. The forecasts can be compared... Agent: International Business Machines Corporation
20130311821 - Virtual device sparing: Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line.... Agent:
20130311822 - System and method for failure protection in a storage array: In accordance with embodiments of the present disclosure, a system comprising may include a storage controller and a plurality of storage resources communicatively coupled to the storage controller. At least one storage resource of the storage resources may be capable of performing storage resource-level failure protection and configured to disable... Agent: Dell Products L.p.
20130311824 - Method and system for cluster resource management in a virtualized computing environment: Methods and systems for cluster resource management in virtualized computing environments are described. VM spares are used to reserve (or help discover or otherwise obtain) a set of computing resources for a VM. While VM spares may be used for a variety of scenarios, particular uses of VM spares include... Agent: Vmware, Inc.
20130311823 - Resiliency to memory failures in computer systems: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then... Agent:
20130311825 - Call restoration in response to application failure: A communication system, method, and components are described. Specifically, the method described herein provides the ability for an application sequence of a communication session to be reconstructed during the communication session and even though SIP standards dictate that the reconstruction of the application sequence should be denied and the session... Agent: Avaya Inc.
20130311826 - Transparent checkpointing and process migration in a distributed system: A distributed system for creating a checkpoint for a plurality of processes running on the distributed system. The distributed system includes a plurality of compute nodes with an operating system executing on each compute node. A checkpoint library resides at the user level on each of the compute nodes, and... Agent:
20130311830 - Generating test data: A method of generating test data is provided herein. The method includes generating a schema comprising a database table. The method also includes receiving a selection of the database table. Additionally, the method includes receiving one or more rule definitions for populating the database table. The method further includes generating... Agent:
20130311828 - Information distribution apparatus, information distribution system and information distribution method: According to one embodiment, an information distribution apparatus includes a receiver, an obtaining module, a determination module, and a transmitter. The receiver receives a request for an application from an electronic apparatus. The obtaining module obtains identification information from the request. The determination module determines whether the identification information is... Agent:
20130311827 - Method and apparatus for automatic testing of automation software: A computer-implemented method and apparatus, the method comprising: receiving a test script indicating actions to be performed by automation software with regard to one or more elements of one or more processes; creating a simulation of the elements of the processes; activating the automation software; and testing activity of the... Agent: International Business Machines Corporation
20130311829 - Performance testing of web components using identity information: Performance testing of web components using identity information includes providing a web component for testing having business logic code and an associated authorization layer code, locating, using a processor, branches in the authorization layer code and the business logic code which are dependent on identity information, and creating, using the... Agent: International Business Machines Corporation
20130311832 - Cross-layer troubleshooting of application delivery: Techniques for cross-layer troubleshooting of application delivery are disclosed. In some embodiments, cross-layer troubleshooting of application delivery includes collecting test results from a plurality of distributed agents for a plurality of application delivery layers; and generating a graphical visualization of an application delivery state based on the test results for... Agent:
20130311831 - Virtual fail address generation system, redundancy analysis simulation system, and method thereof: A fault distribution generation system is provided. The fault distribution generation system comprises: a fail address mapping module which receives a fail bit map representing failures included in a semiconductor device as a plurality of pixels having a plurality of different failure levels and fail addresses for the failures included... Agent: Samsung Electronics Co., Ltd.
20130311833 - Computing device and method for testing components of the computing device: A method of testing components of a computing device by obtaining a serial number of the computing device, and searching a database for test results of the computing device by using the serial number. The method determines whether the computing device has passed an electronic circuitry test when the electronic... Agent: Hong Fu Jin Precision Industry (shenzhen) Co., Ltd.
20130311834 - Preventing cascade failures in computer systems: A computer hardware-implemented method, system, and/or computer program product prevents a cascading failure in a complex stream computer system causing an untrustworthy output from the complex stream computer system. Multiple upstream subcomponents in a complex stream computer system generate multiple outputs, which are used as inputs to a downstream subcomponent.... Agent: International Business Machines Corporation
20130311835 - Forecasting workload transaction response time: Reliability testing can include determining a transaction time for each of a plurality of transactions to a system under test during the reliability test, wherein the plurality of transactions are of a same type. Forecasts of transaction times can be calculated for the transaction type. The forecasts can be compared... Agent: International Business Machines Corporation
20130311836 - System, method, apparatus, and computer program product for providing mobile device support services: A method is provided for providing mobile device support services. The method may include monitoring a mobile device status. The method may additionally include performing device diagnostics based at least in part on captured deice status data to identify potential faults that may affect mobile device functionality. A corresponding system,... Agent:
20130311838 - Information processing apparatus, information processing system and data forwarding method: An information processing apparatus connected to an inputting/outputting apparatus includes a storage apparatus configured to store data, a calculation processing apparatus configured to issue an order, and a data forwarding apparatus configured to generate, upon receiving a data forwarding order issued by the calculation processing apparatus, based on data stored... Agent: Fujitsu Limited
20130311837 - Program-disturb management for phase change memory: Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.... Agent: Micron Technology, Inc.
20130311839 - Generation of error messages and progress information messages via a common interface: The present description refers to a technique for receiving a client instruction, performing an action in response to the client instruction, generating an instance of a progress information message by the business object calling a first method of an API and identifying the progress information message to be generated, determining... Agent: Sap Ag
20130311840 - Method and device for estimating input bit error ratio: An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines... Agent: Mitsubishi Electric Corporation
20130311841 - Scan topology discovery in target systems: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each... Agent: Texas Instruments Incorporated
20130311842 - Test compression in a jtag daisy-chain environment: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG... Agent: Texas Instruments Incorporated
20130311843 - Scan controller configured to control signal values applied to signal lines of circuit core input interface: An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable... Agent: Lsi Corporation
20130311844 - Test card for testing one or more devices under test and tester: A test card for testing one or more devices under test includes a plurality of test resources configured to communicate with the one or more devices under test. The test card further includes a matching circuit configured to receive a test sequence of at least two matching instructions followed by... Agent: Advantest (singapore) Pte. Ltd.
20130311846 - Systems and methods for hardware flexible low density parity check conversion: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.... Agent: Lsi Corporation
20130311845 - Systems and methods for non-binary ldpc encoding: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.... Agent: Lsi Corporation
20130311847 - Error correction coding device, error correction decoding device and method therefor: Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a... Agent: Mitsubishi Electric Corporation
20130311850 - Data processing device and data processing method: A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of... Agent: Sony Corporation
20130311849 - Semiconductor device, electronic device, electronic system, and method of controlling electronic device: A storage device holds data and error correcting codes. An LUT stores a relation between a memory address and an error correction level. An error detection level processing unit calculates, based on an access address included in an access instruction to the storage device and the LUT, the error correction... Agent: Renesas Mobile Corporation
20130311848 - System and method for multi-channel fec encoding and transmission of data: A mechanism for resilient transmission of a data stream D by associating sequential data stream portions with respective elements within an array of elements, defining and FEC encoding each of a plurality of element groups comprising non-sequential data stream portions, dividing the sequence of FEC blocks into a plurality of... Agent:
20130311851 - Adjusting data dispersal in a dispersed storage network: A method begins with a processing module determining that storage of data requires updating, wherein the data is stored as a plurality of sets of encoded data slices in DSN memory. For a first type of updating, the processing module increases the total number while maintaining the decode threshold number.... Agent: Cleversafe, Inc.
20130311852 - Systems and methods for parallel dual-mode turbo decoders: According to some embodiments, a turbo decoder configured for High-Speed Packet Access (HSPA) and Long Term Evolution (LTE) is provided, comprising: a plurality of maximum a posteriori (MAP) engines; a plurality of extrinsic memory banks accessible by a MAP engine of the plurality of MAP engines; and wherein when the... Agent: Mindspeed
20130311853 - Non-volatile memory with extended error correction protection: Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed.... Agent: Micron Technology, Inc.
20130311855 - Method for processing a non-volatile memory, in particular a memory of the eeprom type, for the storage then the extraction of information, and corresponding memory device: Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word... Agent: Stmicroelectronics (rousset) Sas
20130311854 - Semiconductor storage device and control method of nonvolatile memory: A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant... Agent: Hitachi, Ltd.
20130311856 - Applying forward error correction in 66b systems: A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity blocks using the... Agent: Futurewei Technologies, Inc.
20130311857 - Encoding method, decoding method: An encoding method generates an encoded sequence by performing encoding of a given coding rate according to a predetermined parity check matrix. The predetermined parity check matrix is a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low-density parity check... Agent:
20130311858 - Iterative decoding of blocks with cyclic redundancy checks: The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a... Agent: Telefonaktiebolaget L M Ericsson (publ)11/14/2013 > 50 patent applications in 28 patent subcategories.
20130305081 - Method and system for detecting symptoms and determining an optimal remedy pattern for a faulty device: Computer-implemented systems, methods, and computer-readable media electronic for detecting symptoms and determining an optimal remedy pattern for one or more faulty components of a device is disclosed. First the symptoms of the faulty device are detected and associated faulty components of the device are identified. Different tests are performed to... Agent: Infosys Limited
20130305080 - Real-time event storm detection in a cloud environment: A method, an apparatus and an article of manufacture for detecting an event storm in a networked environment. The method includes receiving a plurality of events via a plurality of probes in a networked environment, each of the plurality of probes monitoring a monitored information technology (IT) element, aggregating the... Agent: International Business Machines Corporation
20130305083 - Cloud service recovery time prediction system, method and program: A recovery schedule storing means (81) stores a recovery schedule for a failure of a cloud service with respect to each computing resource type or each application service. A resource usage profile storing means (82) stores a resource usage profile specifying an application service or a computing resource used when... Agent: Nec Corporation
20130305082 - Recovering information: A first memory device receives session information associated with a session between a first network device and a user device. The first memory device outputs the session information associated with the session information. A second memory device receives the session information, associated with the session, from the first memory device.... Agent: Verizon Patent And Licensing Inc.
20130305085 - Network traffic routing: A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. In the event that a production server is unable to provide its service to users, the service appliance can transparently intervene to maintain... Agent:
20130305084 - Server control automation: Control over servers and partitions within a computer network may be automated to improve response to disaster events within the computer network. For example, a monitoring server may be configured to automatically monitor servers through remote communications sessions. A disaster event may be detected based on information received from the... Agent:
20130305086 - Using cache to manage errors in primary storage: An occurrence of at least one storage error is determined in an addressable portion of a primary storage storing a block of data. In response to determining the occurrence of the at least one storage error, it is determined whether the block of data is available in cache storage. In... Agent: Seagate Technology LLC
20130305087 - Method and system for real-time error mitigation: A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of... Agent: Imec
20130305088 - Electronic device and test card thereof: A testing card includes a power interface, a plurality of serial ports connected to a plurality of test instruments. The microprocessor includes a processing unit having been burnt with a plurality of test programs, the processing unit is configured to execute one of the test programs according a user selection... Agent: Hong Fu Jin Precision Industry (shenzhen) Co.,ltd. Ltd.
20130305089 - Motherboard testing apparatus and method for testing: The present disclosure provides a motherboard testing apparatus and method. The motherboard testing method includes following steps. A motherboard testing apparatus is provided. The testing computer and the testing device are electrically connected to a motherboard. The testing computer runs an operating system based on the motherboard. The testing computer... Agent: Hong Fu Jin Precision Industry (wuhan) Co., Ltd.
20130305091 - Drag and drop network topology editor for generating network test configurations: There is disclosed a method and apparatus for editing test configurations. The method includes displaying a graphical representation of a test configuration to be tested by a test system on a user interface and receiving user input identifying network topology to be added to the test configuration, the network topology... Agent:
20130305090 - Test configuration resource manager: A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion... Agent: Ixia
20130305092 - Problem determination and diagnosis in shared dynamic clouds: A method, an apparatus and an article of manufacture for problem determination and diagnosis in a shared dynamic cloud environment. The method includes monitoring each virtual machine and physical server in the shared dynamic cloud environment for at least one metric, identifying a symptom of a problem and generating an... Agent: International Business Machines Corporation
20130305093 - Problem determination and diagnosis in shared dynamic clouds: Techniques for problem determination and diagnosis in a shared dynamic cloud environment. A method includes monitoring each virtual machine and physical server in the shared dynamic cloud environment for at least one metric, identifying a symptom of a problem and generating an event based on said monitoring, analyzing the event... Agent: International Business Machines Corporation
20130305097 - Computer program testing: To centrally manage execution of tests of software in an event oriented manner, a test execution engine reads a first test case from a test case component, where the test case represents tasks that have to be run to test a first procedure of a software program under evaluation. Further,... Agent:
20130305095 - Method for generating test data for evaluating program execution performance: Test data used in evaluating the performance of a program is generated. First, a source program targeted for performance evaluation, sample data, and a generation parameter used for determining the size of the test data to be generated are received from an input device. A processor then executes the source... Agent: Hitachi, Ltd.
20130305098 - Methods, media, and systems for detecting an anomalous sequence of function calls: Methods, media, and systems for detecting an anomalous sequence of function calls are provided. The methods can include compressing a sequence of function calls made by the execution of a program using a compression model; and determining the presence of an anomalous sequence of function calls in the sequence of... Agent:
20130305094 - Observability control with observability information file: Methods of managing observability code in an application program include generating an application program including an observability point, the observability point including a location in the application at which observability code, or a call to observability code, can be inserted, loading the application program into a memory of a target... Agent: Telefonaktiebolaget L M Ericsson (publ)
20130305096 - System and method for monitoring web service: Provided are a system and a method for monitoring a web service. The web service monitoring system includes a management module configured to provide an interface for receiving an test scenario and a policy for a simulation test of a target system from an administrator and outputting the simulation test... Agent: Samsung Sds Co., Ltd.
20130305099 - Method, system, and computer program product: A method for retrieving trace data from a target device is proposed. The target device comprises a program memory, a processor, a trace unit, and a trace buffer. The processor is operable to retrieve instructions from the program memory and to execute them. The trace buffer may contain trace data... Agent: Freescale Semiconductor, Inc.
20130305100 - System and method for predicting and avoiding network downtime: This invention teaches how to use prediction software and algorithms to minimize the risk of failure, and to increase the likelihood of success of information technology (IT) and telecommunications system changes. The method identifies the systems, people, documents and other unanticipated consequences of system changes. The invention teaches how use... Agent:
20130305101 - Techniques for autonomic reverting to behavioral checkpoints: Aspect methods, systems and devices may be configured to create/capture checkpoints without significantly impacting the performance, power consumption, or responsiveness of the mobile device. An observer module of the mobile device may instrument or coordinate various application programming interfaces (APIs) at various levels of the mobile device system and constantly... Agent: Qualcomm Incorporated
20130305102 - Automated trouble ticket generation: Control over servers and partitions within a computer network may be automated to improve response to disaster events within the computer network. For example, a monitoring server may be configured to automatically monitor servers through remote communications sessions. A disaster event may be detected based on information received from the... Agent:
20130305104 - Device fault handling system and communication-compatible device: A device fault handling system includes a host device provided on a network and a communication-compatible device that enables communication with the host device through the network. The communication-compatible device is configured to send to the host device fault event information indicating an occurrence of a fault in a specific... Agent: Funai Electric Co., Ltd.
20130305103 - Relevant alert delivery in a distributed processing system with event listeners and alert listeners: Relevant alert delivery including determining, by an events listener associated with an event queue, whether one or more events in an events queue have not been assigned to any events pool by any event analyzer; and if one or more events in the events queue have not been assigned to... Agent: International Business Machines Corporation
20130305105 - Deterministic data verification in storage controller: Exemplary method, system, and computer program embodiments for performing deterministic data verification by a storage controller are provided. Each of a plurality of concurrent write tasks is configured to be placed in a plurality of overlapping data storage ranges by performing at least one of: implementing a data generation function... Agent: International Business Machines Corporation
20130305106 - Integrated circuits capable of generating test mode control signals for scan tests: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block, a counter circuit, and a control circuit. The test pattern... Agent: Texas Instruments Incorporated
20130305107 - On-chip comparison and response collection tools and techniques: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about... Agent: Mentor Graphics Corporation
20130305108 - 1149.1 tap linking modules: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4... Agent:
20130305111 - Circuit and method for simultaneously measuring multiple changes in delay: A circuit and method provide built-in measurement of delay changes in integrated circuit paths. The circuit includes a digital shift register to access multiple paths, and may be implemented in digital boundary scan to test I/O pin delays. Synchronous to a first frequency, the circuit applies an alternating signal to... Agent: Mentor Graphics Corporation
20130305109 - Hierarchical access of test access ports in embedded core integrated circuits: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one... Agent:
20130305112 - Method and apparatus for diagnosing an integrated circuit: System and method for diagnosing failures within an integrated circuit is provided. In an embodiment, the apparatus includes a diagnostic cell coupled in series with a buffer chain. The diagnostic cell includes a plurality of logic operators that when activated invert a signal received from the buffer chain. The inversion... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.
20130305110 - Reduced signaling interface method & apparatus: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a... Agent:
20130305113 - Data-processing device and data-processing method: When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits... Agent: Sony Corporation
20130305114 - Symbol flipping ldpc decoding system: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of... Agent: Lsi Corporation
20130305115 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305116 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305117 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305118 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent:
20130305119 - Method and device for correction of ternary stored binary data: The invention relates to a device and a method for storing binary data in a storage device, in which the binary data is transformed to and stored as ternary data. The storage device uses memory cells capable of storing three states. The device and method furthermore are configured to identify... Agent: Infineon Technologies Ag
20130305122 - Apparatus and method for storing and assigning error checking and correcting processing of data to storage arrays: A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks... Agent:
20130305120 - Memory controller, storage device and error correction method: According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data... Agent:
20130305121 - Method for reducing uncorrectable errors of a memory device regarding error correction code, and associated memory device and controller thereof: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any... Agent:
20130305123 - Switchable on-die memory error correcting engine: Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die.... Agent: Micron Technology, Inc.
20130305124 - Memory read-out: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system... Agent:
20130305125 - Method for transmitting and receiving signalling information: A method for protecting signalling information in a frame to be transmitted to a receiver in a communication system, comprising: encoding frame signalling information of the frame to protect the frame signalling information; and encoding Forward Error Correction FEC block signalling information of FEC blocks in the frame by using... Agent: Thomson Licensing
20130305126 - Method for transmitting and receiving signalling information: A method for protecting signalling information in a frame to be transmitted to a receiver in a communication system, comprising: encoding frame signalling information of the frame to protect the frame signalling information; and encoding Forward Error Correction FEC block signalling information of FEC blocks in the frame by using... Agent: Thomson Licensing
20130305127 - Forward error correction encoder: A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated... Agent: Texas Instruments Incorporated
20130305128 - Method and apparatus for detecting communication errors on a bus: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a... Agent:
20130305129 - Systems and methods for media defect detection: Various embodiments of the present invention provide systems and methods for media defect detection. For example, a data transfer system is disclosed that includes a data detector, a defect detector and a gating circuit. The data detector provides a soft output, and the defect detector is operable to receive the... Agent:Previous industry: Electrical computers and digital processing systems: support
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