|Error detection/correction and fault detection/recovery patents - Monitor Patents|
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Error detection/correction and fault detection/recovery April category listing, related patent applications 04/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 04/29/2010 > patent applications in patent subcategories. category listing, related patent applications
20100106998 - Robust generative features: Disclosed are systems and methods for developing robust features for representing data. In embodiments, a linear generative model is computed using data. In embodiments, based upon a robustness measure, a set of features is selected. In embodiments, the set of features may be evaluated to gauge the capacity of the... Agent: Epson Research And Development Inc Intellectual Property Dept
20100107001 - Activating correct ad-splicer profile in ad-splicer redundancy framework: In particular embodiments, method and system for detecting a failure of a primary ad-splicer, conveying a failure information for the failed primary ad-splicer to a redundant ad-splicer, dynamically forwarding one or more pre-spliced packets intended for the failed primary ad-splicer to the redundant ad-splicer, receiving one or more post-spliced packets... Agent: Cesari And Mckenna, LLP
20100107000 - Active link verification for failover operations in a storage network: Systems and methods for active link verification for failover operations in a storage network are disclosed. An exemplary method includes issuing a command from a first port of a storage device to a local network device in the storage network. The method also includes receiving a response to the command... Agent: Hewlett-packard Company Intellectual Property Administration
20100107002 - Failure notification in rendezvous federation: Systems and methods that supply a global knowledge on what nodes are available in the system, via employing routing tokens that are analyzed by a centralized management component to infer status for the nodes. When nodes fail, the routing tokens associated therewith are acquired by neighboring nodes, and the global... Agent: Turocy & Watson, LLP
20100106999 - Techniques for determining local repair paths using cspf: Techniques for computing a path for a local repair connection to be used to protect a connection traversing an original path from an ingress node to an egress node. The computed path originates at a node (start node) in the original path and terminates at another node (end node) in... Agent: Townsend And Townsend And Crew, LLP
20100107003 - Fast data recovery from hdd failure: A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives... Agent: Mattingly & Malur, P.C.
20100107004 - Method for selectively retrieving column redundancy data in memory device: Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded... Agent: Vierra Magen/sandisk Corporation
20100107005 - Processor operation inspection system and operation inspection circuit: A processor operation inspection system includes a processor and an operation inspection circuit that inspects an operation of the processor. When a program under execution changes from one predefined state to another state, the processor outputs a state switching signal indicating a transition of its state, a state signal indicating... Agent: Oliff & Berridge, PLC
20100107006 - Method and semiconductor memory with a device for detecting addressing errors: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by... Agent: Ratnerprestia
20100107007 - System recovery in a heating, ventilation and air conditioning network: The disclosure provides a system and method of retrieving data for an active subnet controller of a subnet in an HVAC network. In an embodiment, a device on said subnet reports a loss of internal memory settings to said active subnet controller. The device is recognized by the active subnet... Agent: Hitt Gaines P.C.
20100107008 - Transmission method, transmitter and data processing system comprising a transmitter: A method for transmitting data is described that includes the steps of: Producing a data frame for transmission, the data frame including a sequence number and user data, saving a copy of the data frame in a retransmission buffer, and if said step of saving a copy requires that data... Agent: Docket Clerk
20100107009 - Deterministic component model judging apparatus, judging method, program, recording medium, test system and electronic device: There is provided a deterministic component model identifying apparatus for determining a model of a deterministic component contained in a probability density function supplied thereto. The deterministic component model identifying apparatus includes a spectrum calculating section that calculates a spectrum of the probability density function on an axis of a... Agent: Jianq Chyun Intellectual Property Office
20100107011 - Device and method for outputting bios post code: A device and method for outputting BIOS POST code, applied to a computer system. The device includes a basic input output system (BIOS), a transfer module and a video graphics array (VGA) connector. The BIOS generates a power-on self-test (POST) code using a low pin count (LPC) interface format. The... Agent: Ditthavong Mori & Steiner, P.C.
20100107010 - On-line memory testing: A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is... Agent: Hewlett-packard Company Intellectual Property Administration
20100107012 - Hierarchical debug information collection: Embodiments of the invention are generally related to retrieving debug data from a plurality of nodes of a parallel computer system. To retrieve debug data, a message may be broadcast from a service node of the system to each of the plurality of nodes via a first network, the message... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20100107013 - Input/output workload analysis method and system for a storage area network: A system and method of input/output (I/O) workload analysis of the components in a storage area network (SAN) is disclosed. In one embodiment, a method for analyzing I/O workloads of components in the SAN includes determining host bus adapter (HBA) to storage port oversubscription ratios and HBA to inter-switch link... Agent: Hewlett-packard Company Intellectual Property Administration
20100107015 - Expressing fault correlation constraints: Methods, systems, and computer-readable media for expressing fault correlation constrains to a developer of a service application are provided. Initially, the fault correlation constraints are identified by inspecting an architecture of resources comprising a data center. Based on the resources, sets of nodes that become concurrently unavailable due to a... Agent: Shook, Hardy & Bacon L.L.P. (microsoft Corporation)
20100107016 - System and method for preventing errors ina storage medium: The system and method for preventing write errors in storage mediums includes detecting the presence of an early power fail (EPF) signal derived from a power supply circuit providing power to the storage device. In response to the EPF signal, a modified standby-immediate (MSI) command is issued to the Storage... Agent: Robert D. Shedd, Patent Operations Thomson Licensing LLC
20100107017 - Method to isolate crash of an embedded multi-threaded application to a shared library call without core dump files or debugger: The present disclosure relates in general to embedded information handling systems, and more particularly to systems and methods for isolating a crash of an embedded multi-threaded application to a shared library call in embedded information handling systems.... Agent: Baker Botts L.l.p
20100107019 - Remote control unit of air conditioning apparatus: A remote control unit of an air conditioning apparatus includes a display unit, a cursor-moving member, a confirmation member, and a controller. The display unit displays a menu and a cursor that indicates an item among a plurality of items inside the menu and is moved by the cursor-moving member... Agent: GlobalIPCounselors, LLP
20100107018 - User interface for projection device remote control: A projection device is provided. The projection device includes a server subsystem configured to generate a projection-device-status user interface presentable to a remote client via a webpage served by the server subsystem. The server subsystem includes: a projection control module configured to adjust a projection setting of the projection device... Agent: Alleman Hall Mccoy Russell & Tuttle LLP
20100107020 - Calculation apparatus, calculation method, program, recording medium, test system and electronic device: Provided is a calculating apparatus that calculates a characteristic of a target signal, comprising a designating section that receives a designation of either a bit error rate or a sampling timing; and a calculating section that calculates a range of sampling timings over which the bit error rate is less... Agent: Jianq Chyun Intellectual Property Office
20100107021 - Semiconductor memory device: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100107022 - Bad page marking strategy for fast readout in memory: A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are... Agent: Vierra Magen/sandisk Corporation
20100107023 - Protecting data on integrated circuit: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a... Agent: Brake Hughes Bellermann LLP C/o Cpa Global
20100107024 - Semiconductor device having plural clock domains which receive scan clock in common: A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits, a clock oscillator which generates a plurality of clock signals corresponding to respective... Agent: Mcginn Intellectual Property Law Group, PLLC
20100107026 - Semiconductor device having built-in self-test circuit and method of testing the same: A semiconductor device includes circuits to be tested, an input terminal for receiving a tester clock signal from outside, a built-in self-test (BIST) circuit for logically testing the circuit at every cycle of a tester clock signal, and an output terminal for outputting a test result signal representing a result... Agent: Mcginn Intellectual Property Law Group, PLLC
20100107025 - System, computer program product and method for testing a logic circuit: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The... Agent: Freescale Semiconductor, Inc. Law Department
20100107027 - Decoding apparatus, decoding method, and storage medium: A decoding apparatus acquires, from encoded data, a piece of additional bits that have been partly cut off, acquires, from the piece of the additional bits, the number of bits that are missing due to the cutting off as the number of missing bits, and restores the additional bits by... Agent: Rossi, Kimms & Mcdowell LLP.
20100107028 - Method and apparatus for h-arq scheduling in a wireless communication system: Systems and methodologies are described herein that facilitate Hybrid Automatic Repeat Request (H-ARQ) scheduling and coordination in a wireless communication system. As described herein, a network node capable of cooperation with other nodes for communication to respective users can coordinate a cooperation strategy across nodes based on a H-ARQ protocol... Agent: Qualcomm Incorporated
20100107029 - Wireless communication apparatus and wireless communication method: A wireless communication system includes a transmitting side equipped with a microcomputer for control, for transmitting data and also includes a receiving side for receiving data. To prevent the receiving side from receiving identical data more than once, a sequence number is automatically incremented every time a frame of transmit... Agent: Lerner, David, Littenberg, Krumholz & Mentlik
20100107032 - Bit labeling for amplitude phase shift constellation used with low density parity check (ldpc) codes: An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a... Agent: The Directv Group, Inc. Patent Docket Administration
20100107034 - Information processing device, program and recording medium: The present invention intends to hold safely string information such as secret information, or the like, and also to lessen user's burden of storing the information in connection to the string information. In registering the secret information, a coding section 16 synthesizes input correct secret information SD and individual characteristic... Agent: Pearne & Gordon LLP
20100107030 - Ldpc decoders using fixed and adjustable permutators: In one embodiment, the present invention is a low-density parity-check (LDPC) decoder that has a plurality of variable node units (VNUs) that generate variable node messages and a plurality of check node units (CNUs) that generate check node messages. The variable node messages and check node messages are distributed between... Agent: Mendelsohn, Drucker, & Associates, P.C.
20100107031 - Multiple-input-multiple-output transmission using non-binary ldpc coding: A wireless communication system constructed by a MIMO antenna system and transmitting information from a transmitter having Nt number of transmitting antennas to a receiver 3 having Nr number of receiving antennas. The receiver 3 of this wireless communication system 1 linking the inputs and outputs between a demodulating unit... Agent: Hanify & King Professional Corporation
20100107033 - Radio communication device and puncturing method: Provided is a radio communication device which can minimize degradation of the error ratio characteristic attributed to puncturing when an LDPC code is used as an error correction code. In this device, an LDPC encoding unit (101) performs LDPC encoding on a transmission bit string by using an inspection matrix... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.
20100107035 - Apparatus and method for detecting an end point of an information frame: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection... Agent: Freescale Semiconductor, Inc. Law Department
20100107038 - Cache controller and cache controlling method: A cache memory controlling unit includes a plurality of STBs for maintaining 8-byte store data received from an execution unit, a plurality of WBs, a DATA-RAM, an FCDR, and an ECC-RAM. The cache memory controlling unit having such a structure obtains data-not-to-be-stored from the DATA-RAM, stores the obtained data in... Agent: Staas & Halsey LLP
20100107036 - Error correction in multiple semiconductor memory units: Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the... Agent: Schwegman, Lundberg & Woessner/micron
20100107037 - Memory system with error correction and method of operation: A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at... Agent: Freescale Semiconductor, Inc. Law Department
20100107039 - Semiconductor memory with reed-solomon decoder: A semiconductor memory device with an error checking/correction system includes a memory cell array. The error checking/correction system is capable of symbolizing data to a symbol, searching errors of data read from the memory cell array by solving equations with decoders representing a solution, correcting data based on the searched... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100107040 - Apparatus and method for defect replacement: Apparatuses and methods for defect replacement when an optical storage medium is read are provided. When the defect management is LOW, a pick-up head retrieves a set of data from the optical storage medium; a defect detector detects whether there is a defect in the set; if yes, a processor... Agent: Ladas & Parry LLP
20100107041 - Method and system for reduction of decoding complexity in a communication system: Method and System for Utilization of an Outer Decoder in a Broadcast Services Communication System is described. Information to be transmitted is provided to a systematic portion of a plurality of transmit buffers and encoded by an outer decoder communicatively coupled to the transmit buffer. The resulting redundant bits are... Agent: Qualcomm Incorporated
20100107042 - Wireless communication apparatus, wireless communication method, and computer program: A wireless communication apparatus that operates in a network environment with mixed different packet formats, includes: a first format detecting unit detecting a format by executing signal processing on a preamble of a received packet before decoding; an estimating unit using the preamble to carry out multiple types of estimations;... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100107043 - Network device and method of controlling the same: A network device and a method for controlling the same. The device and method each performed the operations of transforming an input signal so as to allow the input signal to be divided according to frequency bands and resolutions, comparing the transformed input signal with abnormal signal information stored in... Agent: Drinker Biddle & Reath LLP Attn: Patent Docket Dept.04/22/2010 > patent applications in patent subcategories. category listing, related patent applications
20100100760 - Computer system and boot control method: When a primary computer is taken over to a secondary computer in a redundancy configuration computer system where booting is performed via a storage area network (SAN), a management server delivers an information collecting/setting program to the secondary computer before the user's operating system of the secondary computer is started.... Agent: Brundidge & Stanger, P.C.
20100100762 - Backup power source used in indicating that server may leave network: A server of a network of servers determines that its power source is failing. In response, the server communicates to one or more other servers of this network that it is leaving the network. This communication is powered by another power source.... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20100100761 - Maintaining a primary time server as the current time server in response to failure of time code receivers of the primary time server: A primary time server of a Coordinated Timing Network remains as current time server, even if time code information of the primary time server is unavailable. The primary time server receives the necessary or desired timing information from a secondary time server and uses that information to maintain time synchronization... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20100100765 - Estimating data availability on managed storage devices: This disclosure describes methods, systems and software that can be used to calculate the estimated mean time to data loss for a particular configuration of a disk group. For example, a system can be used to evaluate a plurality of configurations, and/or to select (and/or allow a user to select)... Agent: Townsend And Townsend And Crew LLP/oracle
20100100763 - Flash memory controller having configuring unit for error correction code (ecc) capability and method thereof: A flash memory controller having a configuring unit of error correction code (ECC) capability and method thereof are described. The flash memory controller includes a control unit, a buffer, an ECC module, and a configuring unit. The flash memory has a data area for storing the data content and a... Agent: Kirton And Mcconkie
20100100764 - Redundancy information for adjusting threshold for component failure in a multi-layer system: A first unit and a second unit are provided in a multi-layer computing system, wherein the first unit is at a higher layer than the second unit in the multi-layer computing system, and wherein the first unit is a higher level unit and the second unit is a lower level... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20100100766 - Test apparatus: A test apparatus for testing a portable communication unit. The test apparatus comprises a test unit adapted to supply test input data to the portable communication unit and retrieve test output data at least from the portable communication unit in accordance with a test schedule. The test apparatus further comprises... Agent: Ericsson Inc.
20100100767 - Automatically connecting remote network equipment through a graphical user interface: Embodiments of the present invention provide a method and system for designing a test network in an integrated application, and configuring remote network devices through a network design application to test a network design. One embodiment of the present claimed subject matter is provided as a system for automatically configuring... Agent: Accenture C/o Murabito, Hao & Barned LLP
20100100768 - Network failure detecting system, measurement agent, surveillance server, and network failure detecting method: Measurement agents in a network failure detecting system each configure a group together with other measurement agents that receive a service from the same provision server, and form a link to create a tree structure with a predetermined measurement agent in the group at its top. The measurement agent then... Agent: Katten Muchin Rosenman LLP
20100100769 - Power on self test device and computer system applying the same: A power on self test (POST) device and a computer system applying the same are disclosed, wherein the POST device comprises a micro controller and a displaying unit. The micro controller is embedded on a motherboard of the computer system for receiving a plurality of POST codes generated by the... Agent: Kirton And Mcconkie
20100100770 - Software debugger for packets in a network on a chip: A breakpoint packet is dispatched to a Network On A Chip (NOC). The breakpoint packet instructs one or more specified nodes on the NOC to place the specified nodes, or a core or hardware thread within a specified node, to execute in “single step” mode, in order to enable a... Agent: Ibm Corporation
20100100771 - Setup verification for an employee compensation system: A compensation system receives a plurality of setup parameters. The compensation system tests the setup parameters through a verification. The verification generates an error output if the setup parameters will lead to undesirable results when operating the compensation system.... Agent: Squire, Sanders & Dempsey L.L.P. Oracle International Corporation
20100100772 - System and method for verifying compatibility of computer equipment with a software product: System and method for verifying compatibility of computer equipment with a software product. A system and method are provided to verify compatibility of computer equipment with software. This verification can include gathering information about configurations of the computer equipment, and creating at least one file based on the information. The... Agent: Moore & Van Allen PLLC
20100100773 - Input/output device with configuration, fault isolation and redundant fault assist functionality: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The... Agent: Marshall, Gerstein & Borun LLP (fisher)
20100100774 - Automatic software fault diagnosis by exploiting application signatures: A method monitors non-faulty application traces of a computer application with the runtime environment during fault-free activities to create non-faulty runtime signatures for the computer application. Once obtained, the method stores the non-faulty runtime signatures. The method then detects a faulty application trace of the computer application and compares the... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20100100775 - Filtering redundant events based on a statistical correlation between events: Methods, systems, and computer-readable media for filtering redundant fault events from an event stream generated by devices on a network based on a statistical correlation between fault events are provided. Event history data is collected from the fault events generated by devices on the network over a period of time.... Agent: At&t Legal Department - Hbh Attn: Patent Docketing
20100100776 - Information processing apparatus, failure processing method, and recording medium in which failure processing program is recorded: An information processing apparatus includes partitioning mode information retaining section, hardware resource management information retaining section, failure notifying section, operation mode detecting section, shared hardware resource judging section, common failure report creating section for creating, if operation in the partitioning mode is detected and a hardware resource in which the... Agent: Staas & Halsey LLP
20100100777 - Message handling in a service-oriented architecture: A service call to a backend system is initiated by a user interface in a service-oriented architecture. Thereafter, a service answer is received from the backend system encapsulating a backend error object. The backend error object is mapped to a front end error object. A front end error message can... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.
20100100778 - System and method for hardware and software monitoring with integrated troubleshooting: A method, system, and network providing hardware and software inventorying, monitoring and support for a network of interconnected information technology devices. A user downloads and installs a local network monitoring software program from an online source onto a host computer system. The local network monitoring software system initiates an inventory... Agent: HulseyIPIntellectual Property Lawyers, P.C.
20100100779 - Data processing apparatus: A data processing apparatus includes a memory, an error detection circuit, a timing adjustment circuit and a terminal. The error detection circuit detects an error based on an output of the memory to output an error detection signal. The timing adjustment circuit enlarges a pulse width of a pulse signal... Agent: Mcginn Intellectual Property Law Group, PLLC
20100100780 - High speed interconnect circuit test method and apparatus: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan... Agent: Texas Instruments Incorporated
20100100781 - Fully x-tolerant, very high scan compression scan test systems and techniques: Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density... Agent: Bever, Hoffman & Harms, LLP
20100100782 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated
20100100783 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated
20100100784 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated
20100100785 - Integrated circuit with jtag port, tap linking module, and off-chip tap interface port: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.... Agent: Texas Instruments Incorporated
20100100786 - Serial test mode of an integrated circuit (ic): A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives... Agent: Ibm Austin Iplaw (c/o)
20100100787 - Transmission data generating apparatus and receiver: This invention proposes a transmission data generating apparatus for use in a transmitter of a communication system, which transmission data generating apparatus comprises a redundancy data obtaining unit for obtaining redundancy data of information data which was transmitted to a receiver and was not received successfully by the receiver; a... Agent: Myers Wolin, LLC
20100100789 - method and system for data transmission in a multiple input multiple output (mimo) system: A method for data transmission in a multiple input multiple output (MIMO) system. The method for data transmission includes receiving multiple input data streams and performing low density parity check (LDPC) encoding of the input data streams utilising a parity check matrix. The parity check matrix comprises a plurality of... Agent: Patterson, Thuente, Skaar & Christensen, P.A.
20100100790 - Encoding of ldpc codes: A method and apparatus are disclosed that include encoding a codeword using a systematic low density parity check matrix using an encoder, the low density parity check matrix comprising a first sub-matrix associated with information symbols, a second sub-matrix having a block triangular structure associated with a first subset of... Agent: Pillsbury Winthrop Shaw Pittman LLP (intel)
20100100788 - Programmable quasi-cyclic low-density parity check (qc ldpc) encoder for read channel: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved... Agent: Lsi Corporation C/o Suiter Swantz PC Llo
20100100791 - System and method for low complexity raptor codes for multimedia broadcast/multicast service: A system and method for encoding symbols in a wireless communication is provided. The system and method includes a transmitter configured to encode data transmissions. The transmitter includes a raptor encoder configured to perform a coding operation. The raptor encoder generates intermediate symbols without using a half-code such that the... Agent: Docket Clerk
20100100792 - Single-stage decoder for raptor codes: A system and method for recovering erased symbols in a wireless communication is provided. The system and method includes a receiver configured to receive encoded data transmissions. The receiver includes a single stage decoder configured to perform a decoding operation. The single stage decoder also is configured to determine a... Agent: Docket Clerk
20100100793 - Digital television systems employing concatenated convolutional coded data: In iterative-diversity (ID) transmission systems for signals with concatenated convolutional coding (CCC), paired iterative diversity signals each have ½ the code rate of the 8VSB DTV signals prescribed by the 1995 ATSC Digital Television Broadcast Standard. Known serial concatenated convolutional coding (SCCC) or novel parallel concatenated convolutional coding (PCCC) is... Agent: Sughrue Mion, PLLC
20100100794 - Method and controller for data access in a flash memory: A method for controlling access to data in a Flash is provided, including steps as follows: outputting at least one main data block to a buffer area of the Flash continuously, the buffer area of the Flash being adapted to buffer data to be inputted to a storage area of... Agent: Baker & Hostetler LLP
20100100795 - Method and apparatus for performing forward error correction in an orthogonal frequency division multiplexed communication network: According to some embodiments of the disclosed method and apparatus, systems and methods are provided that utilize extra payload capacity present in a symbol pad of a PHY payload to decrease the coding rate of an FEC coding scheme without increasing the symbol rate or decreasing the PHY rate of... Agent: Entropic Communications, Inc.
20100100796 - Error detecting code for multi-character, multi-lane, multi-level physical transmission: A system (e.g., Fibre Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test... Agent: Schwegman, Lundberg & Woessner, P.A.
20100100797 - Dual mode error correction code (ecc) apparatus for flash memory and method thereof: A dual mode error correction code (ECC) apparatus for the flash memory and method thereof are described. The dual mode error correction code (ECC) apparatus includes a syndrome detection unit, a first ECC unit, a second ECC unit, a switch module, and an interface module. The syndrome detection unit detects... Agent: Kirton And Mcconkie
20100100798 - Error detection: A method of error detection for a data packet, the method comprising the steps of: i) identifying a set of non-compliances (N), the non-compliances being illegal bit sequences according to a coding standard; ii) identifying a first subset (N+) of non-compliances that are to be treated as errors; iii) identifying... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing
20100100799 - Fault detection apparatus, fault detection method, and fault detection program: A comparison unit compares polarities of a plurality of redundant input signals. A comparison-result storing unit stores a comparison result of the comparison unit for each predetermined sampling cycle. A judgment unit judges whether the redundant input signals are normal using a plurality of comparison results for a predetermined number... Agent: Sughrue Mion, PLLC04/15/2010 > patent applications in patent subcategories. category listing, related patent applications
20100095147 - Reconfigurable circuit with redundant reconfigurable cluster(s): Reconfigurable circuits, methods, and systems with reconfigurable interconnect devices, clusters of reconfigurable logic devices, and a programming interface configured to receive configuration data to configure a first combination of the reconfigurable interconnect and logic devices to implement a circuit, and to remap a portion of the received configuration data, corresponding... Agent: Schwabe, Williamson & Wyatt, P.C.
20100095149 - Data storage method and device, and system therefor: A method of storing data in a data storage device including a hard disk drive (HDD) and a non-volatile memory (NVM) includes analyzing an access command to access the NVM and transmitting data included in the access command to the HDD based on the analysis result.... Agent: Stanzione & Kim, LLP
20100095148 - Link table recovery method: A link table recovery method for a flash memory having a plurality of blocks is provided. The method includes: selecting one block from the blocks; selecting a last page containing data of the selected block; checking the last page to determine whether the last page has errors; moving the correct... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100095150 - Raid-group converting apparatus and method: A RAID-group converting apparatus converts two RAID groups into one RAID group. The RAID-group converting apparatus includes: a data-reading unit that reads at least non-parity data from data including the non-parity data and parity data, for each stripe from a plurality of recording media belonging to the two RAID groups;... Agent: Staas & Halsey LLP
20100095151 - Processor apparatus for executing instructions with local slack prediction of instructions and processing method therefor: A processor predicts predicted slack which is a predicted value of local slack of an instruction to be executed and executes the instruction using the predicted slack. A slack table is referred to upon execution of an instruction to obtain predicted slack of the instruction and execution latency is increased... Agent: Wenderoth, Lind & Ponack, L.L.P.
20100095152 - Checkpointing a hybrid architecture computing system: A method, apparatus, and program product checkpoint an application in a parallel computing system of the type that includes a plurality of hybrid nodes. Each hybrid node includes a host element and a plurality of accelerator elements. Each host element may include at least one multithreaded processor, and each accelerator... Agent: Wood, Herron & Evans, L.L.P. (ibm)
20100095153 - Apparatus and method for diagnosing abnormal conditions: m
20100095154 - In-circuit debugging system and related method: An in-circuit debugging (ICD) system includes at least a first target processor, an embedded debug mode with a debug information memory (DIM), a debug host, and an ICD bridge. The first target processor has an embedded debug module (EDM) and performs a program code in normal mode, where the first... Agent: North America Intellectual Property Corporation
20100095155 - Diagnostics and error reporting for common tagging issues: Content requests are debugged in accordance with a presence of a flag in a request to a publisher. A document received from the publisher contains a script to debug requests for content to a content provider. The requests are examined to determine the presence of informational, warning and error conditions.... Agent: Fish & Richardson P.C.
20100095156 - Information processing apparatus and control method: A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the... Agent: Staas & Halsey LLP
20100095157 - Problem analysis via matching contiguous stack trace lines to symptom rules: A method and system for analyzing a problem in a computing environment. Symptom rules that include associated problem information are generated in a symptom catalog. An input file including a stack trace provided in response to detecting the problem is received. Function names included in contiguous lines in the stack... Agent: Schmeiser, Olsen & Watts
20100095158 - System and method for supply chain data mining and analysis: A method and system for supply chain data analysis. The method includes storing supply chain data including test data, genealogy data, repair data, some factors and some items, in one or more databases and selecting a portion of the factors from the stored data, and a time range for analysis.... Agent: Christie, Parker & Hale, LLP
20100095159 - Apparatus and method for automatic testing of software or digital devices: An apparatus and method for testing a digital device or software installed in the digital device are provided. According to one aspect, the apparatus for testing the digital device or software installed in the digital device includes a test agent for providing a test execution environment, and the test agent... Agent: North Star Intellectual Property Law, PC
20100095160 - Storage area network (san) link integrity tester: A tester that generates various data patterns to assure that link receivers and transmitters are functioning properly (i.e., are functioning according to a relevant network specification) across the entire storage area network. In various embodiments, this tester may be used in Fibre Channel type SANs or in fiber connectivity (FICON)... Agent: Hamilton & Terrile, LLP IBM Tucson
20100095162 - Method and apparatus for performance bottleneck analysis: Provided is a method for outputting information related to a bottleneck point in a program based on trace records that are output when a predetermined point of the program is executed. The method includes generating candidate patterns of the trace records in an array in which the trace records are... Agent: Greer, Burns & Crain
20100095161 - Test tool for concurrent web services and user interface testing: A computer-executed test tool combines testing of an application at a user interface layer and a web services layer. The computer-executed test tool comprises a capture tool that records a web services test concurrently with recording of a user interface test.... Agent: Hewlett-packard Company Intellectual Property Administration
20100095163 - Monitoring error notification function system: A system for monitoring error notification function comprising: an information processing apparatus including: a first processor including error notification function for generating error information indicative of an error occurred at least one component in the information processing apparatus; a first communication unit for sending the error information; and a management... Agent: Staas & Halsey LLP
20100095164 - File management method and hierarchy management file system: There is provided a file management method of a hierarchy management file system capable of preventing an access performance from dropping when a user accesses to a file. According to the method, a server creates file systems in high-speed and low-speed volumes and a file-sharing server virtually integrates those file... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100095165 - Method of handling a message: A method of handling a message in a messaging system is provided. The messaging system comprises a message source, a message receiver and a message service. The message service is intermediate of the message source and message receiver, wherein a compensation component is established at the message source, The method... Agent: Ibm Corporation
20100095166 - Protocol aware error ratio tester: A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with a protocol aware test and measurement system is disclosed. This system includes two major units, a General Purpose Platform (GPP) that includes a protocol awareness and is capable of traffic generation... Agent: Lecroy Corporation
20100095167 - Method and system for providing bit error rate characterization: An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to... Agent: Verizon Patent Management Group
20100095168 - Embedded processor: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure... Agent: Schwegman, Lundberg & Woessner/micron
20100095169 - Implementing isolation of vlsi scan chain using abist test patterns: A method, apparatus and computer program product are provided for implementing isolation of VLSI AC scan chain defects using structural Array Built In Self Test (ABIST) test patterns. An ABIST test pattern is applied to the device under test and multiple ABIST array algorithms are applied in a passing operating... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100095171 - Scan testing system, method and apparatus: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to... Agent: Texas Instruments Incorporated
20100095170 - Semiconductor integrated circuit device and delay fault testing method thereof: A semiconductor integrated circuit device includes a first clock domain having a plurality of first flip-flops which is configured to operate with a high-speed clock; a second clock domain having a plurality of second flip-flops, composed of a third flip-flop and a plurality of fourth flip-flops, which is configured to... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100095172 - Low power testing of very large circuits: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at... Agent: Texas Instruments Incorporated
20100095173 - Matrix system and method for debugging scan structure: An aspect of the present invention is drawn to a system comprising an automatic test engine, a decompressor, a first scan chain, a second scan chain, a compactor and a debug output. The automatic test engine is operable to output a test output, to receive a resultant input, to receive... Agent: Texas Instruments Incorporated
20100095176 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated
20100095175 - Position independent testing of circuits: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided... Agent: Texas Instruments Incorporated
20100095174 - Scan frame based test access mechanisms: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control... Agent: Texas Instruments Incorporated
20100095177 - Implementing diagnosis of transitional scan chain defects using lbist test patterns: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in... Agent: Ibm Corporation RochesterIPLaw Dept 917
20100095178 - Optimized jtag interface: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used... Agent: Texas Instruments Incorporated
20100095179 - Test pattern generation method for avoiding false testing in two-pattern testing for semiconductor integrated circuit: A test pattern generation method for determining if a combinational portion 17 is defective, by applying test patterns to a semiconductor integrated circuit 10 and comparing responses to the test patterns with expected responses, the method including: a first step of generating test patterns having logic bits for detecting defects... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100095180 - Receiving device, receiving method, program and wireless communication system: A receiving device is provided that includes a radio receiving unit to receive radio signals transmitted from multiple transmitting antennas by multiple receiving antennas and output received signals being digital signals, a frequency control unit to detect and correct a frequency error contained in the received signals, a channel estimation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100095181 - Adaptive and scalable packer error correction apparatus and method: An adaptive and scalable packet error correction apparatus and method in a wireless multicast network is provided. Each retransmission request from a receiver contains a round number and the number of repairs sent in that round. At each receiver, there are two counters for counting the rounds sent out on... Agent: Robert D. Shedd, Patent Operations Thomson Licensing LLC
20100095182 - Apparatus and method for transmitting/receiving broadcast data in a mobile communication system: A method and apparatus for transmitting a broadcast physical layer packet in a mobile communication system supporting multi-slot transmission and hybrid Automatic Repeat Request (H-ARQ) are provided. The method comprises initially transmitting the broadcast physical layer packet according to a fixed transmission format for at least one first slot interval... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20100095183 - Method of process configuration for multiple harq processes: A method of HARQ process configuration in a mobile communication system, wherein a plurality of HARQ processes are transmitted from a transmitter to a receiver including the step of configuring a plurality of HARQ processes of unrestricted use for data flows having different priorities and the step of pre-configuring at... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.
20100095184 - Obtaining erasure-coded fragments using push and pull protocols: Obtaining erasure-coded fragments using push and pull protocols, including the steps of receiving a first set of erasure-coded fragments associated with segments via a transmission using push protocol, whereby the first set is not sufficient for reconstructing some of the segments; and retrieving a second set of erasure-coded fragments using... Agent: Gil Thieberger
20100095185 - Techniques to perform forward error correction for an electrical backplane: Techniques to perform forward error correction for an electrical backplane are described. An apparatus may comprise a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header. Other embodiments are described and claimed.... Agent: Intel Corporation C/o Cpa Global
20100095187 - File server for redundant array of independent disks (raid) system: A redundant array of independent disks system includes a first storage array with a first target processing module and a first plurality of storage devices. A second storage array includes a second target processing module and a second plurality of storage devices. A data processing module receives a plurality of... Agent: Harness, Dickey & Pierce P.L.C
20100095186 - Reprogramming non volatile memory portions: A system and a method for reprogramming a non volatile memory (NVM) portion, the method includes: receiving an initial content of an NVM portion; wherein the initial content differs from an erase content of the NVM portion; processing the previously programmed content in response to input content that should be... Agent: Pearl Cohen Zedek Latzer, LLP
20100095188 - Apparatus and method for detecting and correcting errors in control characters of a multimedia interface: An apparatus and method for detecting and correcting errors in control characters of a multimedia interface. The apparatus comprises a hamming distance filter for detecting and correcting bits errors in a first subset of bits of an input control character including M bits; a glitch filter for detecting and correcting... Agent: Myers Wolin, LLC
20100095189 - Methods and systems for modified maximum-likelihood based tbcc decoding: A method and apparatus for decoding of tailbiting convolutional codes (TBCC) are disclosed. The proposed modified maximum-likelihood TBCC decoding technique preserves error correction performance of optimal maximum-likelihood based TBCC decoding, while the computational complexity is substantially decreased since a reduced number of decoding states has been evaluated. Compare to other... Agent: Qualcomm Incorporated
20100095190 - Storage device and data reading method thereof: According to one embodiment, a data reading method of a storage device for reading data from a storage module, includes: reading data from the storage module; detecting an error in the data; reading, when the error is detected, the data several times; storing each data read several times in a... Agent: Greer, Burns & Crain
20100095191 - Method and apparatus for deinterleaving in a digital communication system: A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds... Agent: Maryam Imam
20100095192 - Berger invert code encoding and decoding method: A Berger invert code encoding and decoding method is disclosed. The method includes steps: Selecting logic value 0 or 1 to represent the stable and unstable states respectively. Calculating the stable bit count and the unstable-bit count of the codeword. Checking whether the unstable bit count is larger than the... Agent: Brian M. Mcinnis
20100095193 - System and method for pre-calculating checksums: In a packet transmission system that uses checksums, partial checksum calculations may be performed during periods of processor underutilization while the data is awaiting final output processing for transport. A system wide checksum service process may coordinate checksum calculations across multiple network protocol layers. The checksum calculations for the buffered... Agent: Banner & Witcoff, Ltd.04/08/2010 > patent applications in patent subcategories. category listing, related patent applications
20100088538 - Methods and systems for computation of probabilistic loss of function from failure mode: A method for determining a probabilistic loss of function of a system includes the steps of determining a plurality of failure mode probabilities, ranking a plurality of functions pertaining to the failure mode probabilities, and identifying a likely function at least substantially lost by the system based at least in... Agent: Honeywell/ifl Patent Services
20100088539 - System and method for providing fault tolerant processing in an implantable medical device: Embodiments herein generally relate to implantable medical devices and, specifically, to a system and method for providing fault tolerant processing in an implantable medical device. In an embodiment a system for providing fault tolerant processing in an implantable medical device is provided. The system can include an implantable medical device... Agent: Pauly, Devries Smith & Deffner, L.L.C.
20100088540 - Block management and replacement method, flash memory storage system and controller using the same: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed... Agent: J C Patents
20100088541 - Failure information monitoring apparatus and failure information monitoring method: According to an aspect of the embodiment, an area control unit refers to usage information of an area management table based on a determined type of an extracted failure information, determines whether the extracted failure information can be stored in a identified lower storage areas, determines a storage location for... Agent: Fujitsu Patent Center C/o Cpa Global
20100088542 - Lockup recovery for processors: A system comprises processing logic configured to assert a lockup signal upon detection of a fault condition and a module coupled to the processing logic and configured to activate a counter upon receiving the lockup signal. After the module activates the counter and before the counter reaches a predetermined threshold,... Agent: Texas Instruments Incorporated
20100088543 - Restarting mehtod using a snapshot: The active server A101 notifies its own operating status to the administration server 106, and the administration server 106 acquires a snapshot and copies a disk according to the policy established by a user. When the active server A101 or the active disk 113 fails, the administration server 106 chooses... Agent: Townsend And Townsend And Crew, LLP
20100088544 - Arithmetic device for concurrently processing a plurality of threads: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction... Agent: Staas & Halsey LLP
20100088545 - Computer apparatus and processor diagnostic method: A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100088546 - Statistical debugging using paths and adaptive profiling: The method executes the application and if there are no errors from the execution of the application, the method ends. If errors exist, the errors are collected from the execution of the application in an error report. Labeled application paths are created by adding a unique label to individual application... Agent: Microsoft Corporation
20100088547 - Computer motherboard and power-on self-test method thereof: An exemplary computer motherboard of a computer includes a basic input output system (BIOS) chip having a detecting module, a plurality of function elements, and a control chip connected to the BIOS chip. The control chip includes a plurality of detecting pins each corresponding to a corresponding one of the... Agent: PCe Industry, Inc. Att. Steven Reiss
20100088549 - System and method for inferring traffic legitimacy through selective impairment: Described is a system and method for determining a classification of an application that includes initiating a stress test on the application, the stress test including a predetermined number of stress events, wherein the stress events are based on a network impairment. A response by the application to each stress... Agent: At & T Legal Department - Wt
20100088548 - Using constraint solving to discovering disjunctive and quantified invariants over predicate abstraction: Techniques are disclosed for generating complex invariants in a program using a Satisfiability Modulo Theories (SMT) solver. In one embodiment, the generated invariants may be used to validate assert statements in a program. Additionally or alternatively, a weakest pre-condition invariant may be generated such that parameters passed to the program... Agent: Lee & Hayes, PLLC
20100088550 - Cache memory apparatus, execution processing apparatus and control method thereof: A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register... Agent: Staas & Halsey LLP
20100088551 - Method and apparatus for risk analysis of published logs: A method and apparatus for analyzing risk associated with published logs are described. In one embodiment, the method comprises accessing a first log published to one or more logs. In one embodiment, the method may also comprise estimating a probability that an entry within the first log will not be... Agent: Blakely Sokoloff Taylor & Zafman LLP
20100088552 - Method for obstruction and capacity information unification monitoring in unification management system environment and system for thereof: Provided are a method and system for integrated monitoring of fault and performance information in an integrated management system environment including an integrated management server that interworks with a managed server having a built-in agent for the sake of integrated management of a variety of management information. The method includes... Agent: The Webb Law Firm, P.C.
20100088553 - Information system: An information system includes a housing with a plurality of units mounted thereon, a communication path built in the housing to take charge of information communication between a plurality of the units mounted on the housing, an information unit mounted on the housing to provide and process the information, a... Agent: Staas & Halsey LLP
20100088554 - Apparatus and methods for capture of flow control errors in clock domain crossing data transfers: Apparatus methods for capturing flow control errors in FIFO exchanges between producing and consuming circuits operating in different clock domains. Tag information at the start of an exchange is transferred to a synchronizing component before data of a transfer transaction is entered in the FIFO. The tag information is also... Agent: Duft Bornsen & Fishman LLP
20100088555 - Method for encoding a contactless switching system: An embodiment of the invention relates to a contactless switching system and an embodiment relates to a method for encoding same with at least one sensor and at least one signal generator, where the signal generator sends at least one data sequence and the sensor receives the data sequence. In... Agent: Harness, Dickey & Pierce, P.L.C
20100088556 - Fault management system in multistage copy configuration: A data storing system including: a first, second and third storage systems providing first, second and third logical volumes; wherein the first logical volume and the second logical volume forms a first replication pair which indicates the first logical volume is a replication source and the second logical volume is... Agent: Antonelli, Terry, Stout & Kraus, LLP
20100088557 - Systems and methods for multiple coding rates in flash devices: A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding... Agent: Pearl Cohen Zedek Latzer, LLP
20100088558 - Computer apparatus: A computer apparatus includes a main memory, a first memory diagnosis unit that determines a faulty area in the main memory by executing a first memory diagnostic program, and a storage unit that stores a relocatable second memory diagnostic program. Moreover, the computer apparatus includes a second memory diagnosis unit,... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100088559 - Computer system and memory use setting program: A computer system including: a memory configured to store various kinds of data; a use setting data memory means for storing use setting data indicating a use of each of a plurality of memory blocks into which the memory is divided by a certain length; a memory diagnosis means for... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100088560 - Method and system for selecting test vectors in statistical volume diagnosis using failed test data: A method and system for test vector selection in statistical volume diagnosis using failed test data is disclosed. A computer-implemented method receives failures representing defects detected by an integrated circuit testing apparatus from a plurality of integrated circuits. Each of the plurality of integrated circuits is tested with a set... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department
20100088561 - Functional frequency testing of integrated circuits: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.... Agent: Schmeiser, Olsen & Watts
20100088562 - Functional frequency testing of integrated circuits: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.... Agent: Schmeiser, Olsen & Watts
20100088563 - Saving debugging contexts with periodic built-in self-test execution: A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the... Agent: Texas Instruments Incorporated
20100088564 - Semiconductor ic incorporating a co-debugging function and test system: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state... Agent: Volentine & Whitt PLLC
20100088566 - Analyzing apparatus and data storage method: An analyzing apparatus includes a result-data storing unit that determines whether result data that is calculated as a result of analysis is restorable by linear interpolation. If the result data is determined to be unrestorable by the linear interpolation, the result-data storing unit stores the result data in a predetermined... Agent: Westerman, Hattori, Daniels & Adrian, LLP
20100088565 - Correction of single event upset error within sequential storage circuitry of an integrated circuit: Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output... Agent: Nixon & Vanderhye P.C.
20100088567 - Radio communication apparatus and a method of transmitting a retransmission packet: A radio communication apparatus having a retransmission function includes a pattern storing unit configured to store a correspondence between resource blocks used for a transmission packet and resource blocks used for a retransmission packet; and a packet scheduling unit configured to arrange the retransmission packet based on the correspondence.... Agent: Osha Liang L.L.P.
20100088570 - Apparatus and method for supporting hybrid automatic repeat request in wireless communication system: A wireless communication system includes an apparatus and a method for supporting Hybrid Automatic Repeat Request. A transmitting method includes when an encoding packet is bigger than a maximum encoding packet size Nep_max, generating a first codeword by encoding the encoding packet at a mother code rate t; generating a... Agent: Docket Clerk
20100088569 - Packet retransmission: Embodiments disclosed herein include systems and methods of packet retransmission. More specifically, at least one nonlimiting example of a method includes receiving data from above a γ (gamma) interface, the data being identified as protected or not protected data; and storing the protected fragment in a retransmission queue included in... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100088568 - Retransmissions in a wireless communications system: A method (800) for a communications system (100, 300), with a sender (110), which transmits data as packets to a receiver (120). The receiver transmits (805) quality values to the sender representing the reception quality of packets received with errors. The receiver stores (810) information regarding a number of received... Agent: Coats & Bennett, PLLC
20100088571 - High speed ldpc decoding: An optical probability-domain LDPC decoder suitable for implementation at 100 Gb/s and above provides large coding gains when based on large-girth LDPC codes. A basic building block, the probabilities multiplier circuit, used to implement both check node and probability node update circuits can be implemented using Mach-Zehnder delay interferometer.... Agent: Nec Laboratories America, Inc.
20100088572 - Processor and error correcting method: A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and... Agent: Staas & Halsey LLP
20100088573 - Method and apparatus for high speed structured multi rate low density parity check codes: Certain aspects of the present disclosure relate to a method for designing structured multi-rate low-density parity-check (LDPC) codes. These LDPC codes can be also adapted to support efficient encoding.... Agent: Qualcomm Incorporated
20100088574 - Data storage system and device with randomizer/de-randomizer: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control... Agent: Volentine & Whitt PLLC
20100088575 - Low density parity code (ldpc) decoding for memory with multiple log likelihood ratio (llr) decoders: Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the... Agent: Vierra Magen Marcus & Deniro LLP
20100088576 - Magnetic disk controller and method: Among other disclosed subject matter, a magnetic disk controller includes an interface that receives and transmits data to be written into a magnetic disk. The magnetic disk controller includes a first buffer and a second buffer each of which temporarily stores data that is to be written into at least... Agent: Fish & Richardson P.C.
20100088577 - Multi-mode forward error correction: According to one embodiment, a system for multi-mode forward error correction comprises a substrate, forward error correction (FEC) modules, and a controller. The FEC modules are disposed outwardly from the substrate. A first FEC module performs forward error correction according to a first FEC scheme, and a second FEC module... Agent: Baker Botts L.L.P.
20100088578 - Parity bit soft estimation method and apparatus: The systematic and parity bits of a symbol are tightly coupled to each other based on the way in which the symbol is encoded. The relationship between the systematic and parity bits can be exploited to improve the accuracy of soft bit estimation for both the systematic bits and parity... Agent: Coats & Bennett, PLLC
20100088579 - Data integrity validation in a computing environment: A method for validating data in a data storage system comprising associating a first data chunk with first check data and storing the first data chunk and the first check data on a first storage device. Additional associated data chunks of the first data and associated additional check data are... Agent: CenturyIPGroup, Inc. [ibm Us]
20100088580 - Method of transmitting and receiving data in a wireless communication system: A method for transmitting data from a network to a user equipment in a wireless communication system is provided. The network adds an error detection code, generated using a first identifier allocated to the user equipment, to scheduling information for data to be transmitted to the user equipment and transmits... Agent: Mckenna Long & Aldridge LLP04/01/2010 > patent applications in patent subcategories. category listing, related patent applications
20100083029 - Self-optimizing algorithm for real-time problem resolution using historical data: A self-optimizing algorithm for real-time problem resolution using historical data. Upon receiving failure symptom characteristics for a product or process failure, the algorithm queries historical failure data to locate historical failure symptoms and corrective actions matching the failure symptom characteristics. If a total number of the historical corrective actions identified... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20100083031 - Method for queuing message and program recording medium thereof: According to an aspect of the embodiment, a message queuing unit of the message processing apparatus stores received messages. A message reception control unit receives a notification of destinations of messages, extracts only the messages for current processes based on a process control table recording current or standby of processes,... Agent: Greer, Burns & Crain
20100083030 - Repairing high-speed serial links: A method and system for repairing high speed serial links is provided. The system includes a first electronic components, connected to at least a second electronic component via at least one link. At least one of the first or second electronic components has a link controller. The link controller is... Agent: Hewlett-packard Company Intellectual Property Administration
20100083032 - Connection broker assignment status reporting: In one embodiment a computing system comprises one or more processors, a display device coupled to the computing system, and a memory module communicatively connected to the one or more processors. The memory module comprises logic to receive, in a connection server, a service request from a user via a... Agent: Hewlett-packard Company Intellectual Property Administration
20100083033 - Device and method for automatically determining a network element for replacing a failing network element: A device (D), intended for working for at least one network (N), comprises i) an ontology agent (OA) storing at least one ontology defining representations of network elements and relations between these network elements, and ii) a processing means (PM) arranged, when a status of a network element indicates that... Agent: Fay Sharpe/lucent
20100083034 - Information processing apparatus and configuration control method: An information processing apparatus for providing a plurality of services by a plurality of software programs, includes: a plurality of hardware resources; a storage unit that stores priorities of the services; a processor that controls configuration of the hardware resources in accordance with a process including: partitioning the plurality of... Agent: Fujitsu Patent Center C/o Cpa Global
20100083035 - Method for wireless communication in wireless sensor network environment: Provided is a wireless communication method in a wireless sensor network environment. The method overhears a packet transmitted from a source sensor node to a destination sink node and determines whether the destination sink node receives the packet. A transmission node selected by using local information among a plurality of... Agent: Staas & Halsey LLP
20100083036 - Configuration of memory management techniques selectively using mitigations to reduce errors: Techniques for performing memory management to mitigate memory errors. In accordance with the principles described herein, a memory management module may be implemented that acts in different modes of operation for each of one or more software modules that are instances of applications. In one mode of operation, memory operations... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.
20100083037 - Memory repair: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.... Agent: Dickstein Shapiro LLP
20100083038 - Method and systems for restarting a flight control system: A method for rapid restarting of a flight control system, wherein the flight control system comprises a processor, is provided. The method includes storing at least one executable program on a memory device and copying the at least one executable program to a first random access memory (RAM) sector and... Agent: John S. Beulick (12729) C/o Armstrong Teasdale LLP
20100083039 - Redundant array of independent disks-related operations: In an embodiment, an apparatus is provided that may include circuitry to generate, at least in part, and/or receive, at least in part, at least one access request involving a redundant array of independent disks (RAID) storage. The storage may be capable of accessing, in response, at least in part,... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20100083040 - Expander circuit for a solid state persistent storage device that provides a plurality of interfaces to corresponding storage controllers: A system includes a solid state persistent storage device, and a plurality of storage controllers to manage access of the solid state persistent storage device. An expander circuit is connected to the solid state persistent storage device and has a plurality of computer-based bus interfaces connected to the corresponding plurality... Agent: Hewlett-packard Company Intellectual Property Administration
20100083041 - File update system and boot management system of mobile communication terminal, method of updating file in mobile communication terminal, and method of booting mobile communication terminal: Disclosed are a file update system of a mobile communication terminal which is capable of recovering Same Owner ID Error caused by damage of a file header in an EFS (Embedded File System) area of the mobile communication terminal, a boot management system of a mobile communication terminal which is... Agent: H.c. Park & Associates, PLC
20100083042 - Data processing device capable of automatically retransmitting data file deleted from server: To facilitate retransmission of a data file that has been deleted from a server, a data processing device includes a first storage section in which a management table is stored. The management table includes a list of communication histories with respect to communications with each of the servers. Each communication... Agent: Scully, Scott, Murphy &presser, P.C.
20100083043 - Information processing device, recording medium that records an operation state monitoring program, and operation state monitoring method: The device and method includes outputting a subsistence signal repeatedly that indicates that an information processing device is normally operating when the information processing unit is normally operating, executing a memory dump processing, if necessary, when a fault occurs in the information processing unit, monitoring whether another subsistence signal is... Agent: Staas & Halsey LLP
20100083044 - Information processing apparatus with resume function and information processing system: An information processing apparatus having a resume function which can maintain the security even when a plurality of users commonly use the apparatus. A work state at a power-off time of the apparatus is preserved together with a work state name including a user's ID in a different area in... Agent: Brundidge & Stanger, P.C.
20100083045 - Methods and apparatus to perform quality testing in internet protocol multimedia subsystem based communication systems: Methods and apparatus to perform quality testing in Internet Protocol (IP) Multimedia subsystem (IMS) based communication systems are disclosed. An example IMS-based system comprises a web portal to allow a user to configure quality testing for a user endpoint and to present results of the quality testing, a test server... Agent: At&t Legal Department - Hfz Attn. Patent Docketing
20100083046 - Log management method and apparatus, information processing apparatus with log management apparatus and storage medium: One system monitors components constituting an information apparatus and a program in execution. The system classifies logs outputted from the information processing apparatus for each monitor target, divides the monitor targets into categories of hardware and software, refers to relationship definition information indicating the combination of monitor targets in which... Agent: Fujitsu Patent Center C/o Cpa Global
20100083049 - Computer system, method of detecting symptom of failure in computer system, and program: Provided is a computer system comprising: a failure symptom detection unit for detecting a symptom of a failure in hardware of a computer based on a measurement of a sensor; and a plurality of the sensors each provided to a component of the hardware, for measuring a status quantity of... Agent: Mattingly & Malur, P.C.
20100083048 - Evaluating effectiveness of memory management techniques selectively using mitigations to reduce errors: A mitigation enablement module for a computer that improves application reliability. When performing memory management operations, the mitigation enablement module and associated memory manager selectively use mitigations that are intended to prevent an application bug from cause an application error. The memory manager may selectively apply mitigations for each of... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.
20100083047 - Memory management techniques selectively using mitigations to reduce errors: Techniques for performing memory management to mitigate memory errors. In accordance with the principles described herein, a memory management module may be implemented that acts in different modes of operation for each of one or more software modules issuing requests for performance of memory operations to the memory management module.... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.
20100083050 - Error detection control system: An error detection control system for a nonvolatile memory comprises: a nonvolatile memory having data areas for a plurality of addresses each including a main data area and a redundant data area for one address; memory control means for controlling on the nonvolatile memory a batch erasing process on a... Agent: Morrison & Foerster LLP
20100083051 - Gaming apparatus having memory fault detection: In the information process device 1, the fault inspection program is stored in the fault inspection program area 13b of the ROM 13 provided on the mother board 11 which is independently arranged from the hard disk 24, thereby even if a fault occurs in the hard disk 24 which... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100083052 - Apparatus, system, and method for multi-address space tracing: An apparatus, system, and method are disclosed for multi-address space tracing. A trigger module establishes a trigger event with a trace level. The trigger event occurs in at least a first address space of a plurality of address spaces. The trace level defines trace data to be stored from the... Agent: Kunzler Needham Massey & Thorpe
20100083053 - System and method for generating an orthogonal array for software testing: A system and method for generating an orthogonal array (OA) for software testing is disclosed. In one embodiment, the method for generating an OA of test cases for testing a system includes accepting a user input from a user, the user input including multiple factors and multiple levels associated with... Agent: GlobalIPServices, PLLC
20100083056 - Prognostic diagnostic capability tracking system: A universal on-board system is provided for automatic fault detection and on-the-spot repair instructions that includes a module adapted to be coupled to a wide variety of platforms and Line Replaceable Units.... Agent: Bae Systems
20100083055 - Segment based technique and system for detecting performance anomalies and changes for a computer based service: A technique includes sampling at least one performance metric of a computer-based service to form time samples of the metric(s) and detecting an occurrence of an anomaly or a performance mode change in the service. The detection includes arranging the time samples in segments based on a statistical analysis of... Agent: Hewlett-packard Company Intellectual Property Administration
20100083054 - System and method for dynamic problem determination using aggregate anomaly analysis: A system and method are provided for determining problem conditions in an IT infrastructure using aggregate anomaly analysis. The anomalies in the metrics occurring in the monitored IT infrastructure are aggregated from all resources reporting metrics as a function of time. The aggregated metric anomalies are then normalized to account... Agent: Luce, Forward, Hamilton & Scripps LLP
20100083057 - System and method for file monitoring: A file monitoring system tracks progress of data processing of a data file. Various applications and systems transmit status updates at one or more stages of processing to the file monitoring system. The file monitoring system monitors the status updates and generates reports displaying the status of the data file... Agent: Garlick, Harrison & Markison (visa)
20100083058 - Method and system of installing a program on a first computer, and dulpicating the installation on a second computer: Installing a program on a first or primary computer system, and duplicating the installation on a second or secondary computer system. At least some of the illustrative embodiments are methods comprising installing a software program on a first computer system by way of a human interacting with the first computer... Agent: Hewlett-packard Company Intellectual Property Administration
20100083059 - Storage systems and methods for distributed support ticket processing: Storage systems and methods for distributed support ticket processing are disclosed. An exemplary method may include accessing at least one storage device in a storage system by an interface manager to retrieve raw support ticket data from the at least one storage device. The method may also include analyzing the... Agent: Hewlett-packard Company Intellectual Property Administration
20100083060 - System and method for mpeg crc error based video network fault detection: Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, sending a notification to an automated fault manager which (1) analyzes the... Agent: At & T Legal Department - Ndq
20100083061 - Method to manage path failure thresholds: A failure threshold host command that provides a host with the capability to tune a storage controller path failure threshold based on the host application performance requirements. The failure threshold host command comprises path failure threshold rules that the storage controller uses to determine when a CHPid has reached a... Agent: Hamilton & Terrile, LLP IBM Tucson
20100083062 - High performance pulsed storage circuit: The application discloses state storage circuitry comprising: an operational data input for receiving input data, a diagnostic data input for receiving diagnostic data and a diagnostic select signal input; a storage element for storing a value indicative of data received from one of said operational data input and said diagnostic... Agent: Nixon & Vanderhye P.C.
20100083063 - Phase shifter with reduced linear dependency: A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs... Agent: Klarquist Sparkman, LLP
20100083064 - Scannable d flip-flop: The present invention relates to scannable D flip-flops, which are improved to solve the problem of the conventional designs and provides a small and fast scannable D flip-flop without compensating its testability. The embodiment of the present invention provides a scannable D flip-flop, comprising a source coupled logic, comprising a... Agent: Patterson & Sheridan, L.L.P.
20100083065 - Method and apparatus for error detection and correction: A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a... Agent: J. V. Myers & Associates, PC
20100083067 - Mobile communication apparatus: In a mobile communication system, when a receiving condition is deteriorated to the extent that reception does not succeed even by means of combination after retransmission to the maximum number of retransmissions, a transmission rate is restricted by reducing radio frames assignable to new data, and by setting dedicated retransmission... Agent: Hanify & King Professional Corporation
20100083066 - System and method for automatic communication lane failover in a serial link: A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may... Agent: Mhkkg/sun
20100083068 - Allocation of symbols of an erasure code across a plurality of devices: A technique is provided for determining an allocation of the symbols of an erasure code across a plurality of devices. A list of erasure patterns is provided for the erasure code and, based on the list, minimal erasures of minimal weight are identified for the code's symbols. Precedences of the... Agent: Hewlett-packard Company Intellectual Property Administration
20100083069 - Selecting erasure codes for a fault tolerant system: A technique for selecting an erasure code from a plurality of erasure codes for use in a fault tolerant system comprises generating a preferred set of erasure codes based on characteristics of the codes' corresponding Tanner graphs. The fault tolerances of the preferred codes are compared based at least on... Agent: Hewlett-packard Company Intellectual Property Administration
20100083070 - Sending and receiving method and apparatus for implementing service data recovery: A sending method, a receiving method, a sending apparatus, and a receiving apparatus for implementing service data recovery are disclosed, a channel protection method for channels which fail, and a channel protection system with the corresponding sending apparatus and receiving apparatus are disclosed. The channel protection method includes: performing in-band... Agent: Huawei Technologies Co., Ltd. C/o Darby & Darby P.C.
20100083071 - Ldpc (low density parity check) code size adjustment by shortening and puncturing: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original... Agent: Garlick Harrison & Markison
20100083072 - Data interleaver: Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix... Agent: Law Office Of Charles W. Bethards, LLP
20100083073 - Data processing apparatus, memory controlling circuit, and memory controlling method: A data processing apparatus includes a memory, an additional bit generating unit which generates an additional bit to be added to write expectation values, on a basis of the write expectation values to be written respectively to designated addresses in the memory, the additional bit and the write expectation values... Agent: Mcginn Intellectual Property Law Group, PLLC
20100083074 - Block code decoding method and device thereof: A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20100083075 - Methods and apparatus for selective data retention decoding in a hard disk drive: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in... Agent: Ryan, Mason & Lewis, LLP
20100083076 - Terminal device, time adjusting method of terminal device and communication system: A terminal device includes: a time information receiving unit which receives measured time and an estimated error of another terminal device; an estimated error calculating unit which calculates an error containing the estimated error of another terminal device received by the time information receiving unit as an updating-use estimated error;... Agent: Oliff & Berridge, PLCPrevious industry: Electrical computers and digital processing systems: support
Next industry: Data processing: presentation processing of document
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