Error detection/correction and fault detection/recovery inventions 07/09

20090193286 - Method and system for in-doubt resolution in transaction processing: A method and system are provided for in-doubt resolution in transaction processing involving at least two distributed transaction processing systems. The method includes an initial exchange of information to establish an identifier for coordinating units of recovery in distributed transaction processing systems. The method includes a first transaction processing system... Agent: Ibm Corporation

20090193287 - Memory management method, medium, and apparatus based on access time in multi-core system: A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a task to be performed by a processing core and it is possible to secure the same... Agent: Staas & Halsey LLP

20090193288 - Routing token transfer and recovery protocol in rendezvous federation: Systems and methods that provide for assignment and recovery of tokens as part of a plurality of nodes and distributed application framework/network. The assignment component assigns numbers and tasks to candidates and facilitates multiple leader election. Moreover, a recovery component can recover a token for a node that leaves the... Agent: Turocy & Watson, LLP

20090193289 - Reducing data loss and unavailability by integrating multiple levels of a storage hierarchy: A method for reducing data loss and unavailability by integrating multiple levels of a storage hierarchy is provided. The method includes receiving a read request. In addition, the method includes recognizing a data failure in response to the read request. The method further includes locating an alternate source of the... Agent: Lewis Nunnelley

20090193290 - System and method to use cache that is embedded in a memory hub to replace failed memory cells in a memory subsystem: A memory system, data processing system, and method are provided for using cache that is embedded in a memory hub device to replace failed memory cells. A memory module comprises an integrated memory hub device. The memory hub device comprises an integrated memory device data interface that communicates with a... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090193291 - Equipment controlling system and controlling method thereof: An equipment controlling system and a controlling method thereof are disclosed. The system includes a first controller connected to equipments of a first group to monitor and control operations of the equipments; and a second controller connected to equipments of a second group to monitor and control operations of the... Agent: Mckenna Long & Aldridge LLP

20090193292 - Methods and computer program products for defing synchronous replication devices in a subchannel set other than subchannel set zero: Exemplary embodiments of the present invention define PPRC devices within subchannel sets other than subchannel set zero. Further, for all PPRC paired n devices an additional N/2 PPRC primary device numbers and subchannels are provided within subchannel set zero by moving PPRC secondary devices to any subchannel set other than... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090193294 - System and method for verifying operation of a target system: A system and method for verifying operation of a target system to be inspected. The system includes an abstract binary tree generation unit and a matching unit. The abstract binary tree generation unit obtains information about a functional specification of the target system and generates one or more binary trees... Agent: Ibm Corporation, T.j. Watson Research Center

20090193293 - Systems, methods, and media for outputting data based upon anomaly detection: Systems, methods, and media for outputting data based on anomaly detection are provided. In some embodiments, methods for outputting data based on anomaly detection include: receiving a known-good dataset; storing distinct n-grams from the known-good dataset to form a binary anomaly detection model; receiving known-good new n-grams; computing a rate... Agent: Byrne Poh LLP

20090193295 - Voltage margin testing for proximity communication: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20090193296 - Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulation: A test system tests a full system integrated circuit (IC) model that includes a device under test (DUT) IC model and a support IC model. A test manager information handling system (IHS) maps the full system IC model on a hardware accelerator simulator via an interface bus. The hardware accelerator... Agent: Mark P. Kahler

20090193297 - Diagnostic context construction and comparison: A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing... Agent: Nixon & Vanderhye P.C.

20090193298 - System and method of fault detection, diagnosis and prevention for complex computing systems: A method is provided for diagnosing failures in an object-oriented software system. The method comprises collecting runtime diagnostic information; maintaining a record of the diagnostic information in a storage buffer; and dynamically updating the record of the diagnostic information to include a group of the diagnostic information collected over a... Agent: Cantor Colburn LLP - IBM Fishkill

20090193299 - Medical support control system: A medical support control device to which are connected a display manipulation device and a medical device control device connected to a medical device and controlling the medical device, comprising: a detection unit for detecting abnormality in an image signal line outputting an image signal to the display manipulation unit;... Agent: Ostrolenk Faber Gerb & Soffen

20090193300 - System and method for pseudorandom permutation for interleaving in wireless communications: wherein P is the smallest power of two not less than the number of elements in the first ordered sequence, S is an input order represented by a sequence of consecutive integers from zero to P−1 in increasing order, Y is an output order represented as a sequence of integers,... Agent: Knobbe, Martens, Olson, & Bear, LLP

20090193301 - Semiconductor memory device and refresh period controlling method: Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The... Agent: Foley And Lardner LLP Suite 500

20090193302 - Semiconducrtor device: A semiconductor device capable of reducing a memory area of a test circuit required for storing fail-information is provided. In the test circuit, for determining right/wrong of information obtained by memory access, specific fail-information among pieces of fail-information sequentially obtained in response to wrong-determination result is held in a first... Agent: Mattingly & Malur, P.C.

20090193304 - Apparatus and method for isolating portions of a scan path of a system-on-chip: The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of... Agent: Wall & Tong, LLP/ Alcatel-lucent Usa Inc.

20090193303 - Test access mechanism for multi-core processor or other integrated circuit: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090193305 - Test mode soft reset circuitry and methods: An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to... Agent: Martine Penilla & Gencarella, LLP

20090193306 - Apparatus and method for controlling dynamic modification of a scan path: The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component.... Agent: Wall & Tong, LLP/ Alcatel-lucent Usa Inc.

20090193307 - Scan chain modification for reduced leakage: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects... Agent: Stmicroelectronics, Inc.

20090193309 - Device and method for correcting a data error in communication path: There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an... Agent: Eric Robinson

20090193308 - Method and an apparatus for controlling an unreliable data transfer in a data channel: Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting... Agent: International Business Machines Corporation Richard Lau

20090193310 - Data transfer method: A data transfer method having a data retransmission function, in which a sending side saves data that was sent in memory, a receiving side uses a transmission confirmation signal to request the sending side to retransmit the data when the data was not properly received, then monitors the elapsed time,... Agent: Hanify & King Professional Corporation

20090193311 - Retransmission of erroneous data: A method for retransmission of erroneous data in a communications system includes receiving data blocks at a receiver that have been generated in a transmitter by the use of an error correcting code. The received data blocks are decoded by a linear programming algorithm. One or more symbols in the... Agent: Eschweiler & Associates LLC

20090193312 - Fixed-spacing parity insertion for fec (forward error correction) codewords: Fixed-spacing parity insertion for FEC (Forward Error Correction) codewords. Fixed spacing is employed to intersperse parity bits among information bits when generating a codeword. According to this fixed spacing, a same number of information bits is placed between each of the parity bits within the codeword. If desired, the order... Agent: Garlick Harrison & Markison

20090193314 - Forward error correction for burst and random packet loss for real-time multi-media communication: This invention relates generally to a packet recovery algorithm for real-time (live) multi-media communication over packet-switched networks, such as the Internet. Such multi-media communication includes video, audio, data or any combination thereof. More specifically, the invention comprises a forward error correction (FEC) algorithm that addresses both random and burst packet... Agent: Jackson, Demarco, Tidus & Packenpaugh

20090193313 - Method and apparatus for decoding concatenated code: i

20090193315 - System for a combined error correction code and cyclic redundancy check code for a memory channel: A memory system is provided that performs error correction at a memory device level. The memory system comprises a memory hub device integrated in the memory module and a link interface integrated in the memory hub device that provides a communication pathway between the memory hub device and an external... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090193316 - Memory subsystems with fault isolation: An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second data bus routing data groupings in an upper 72 bits to a second memory expander. A first memory module receives all of... Agent: Hewlett Packard Company

20090193318 - Forward error correction and interleaving of network frames: A network stream transmitter receives a transport stream having content packets and packets to be filtered out and is adapted to selectively encapsulate content packets into network frames.... Agent: Merchant & Gould Scientific Atlanta, A Cisco Company

20090193317 - Method and system for signal error determination and correction in a flexray communication system: A signal error determination and correction system is provided which comprises an error correction value calculation means which processes a predetermined segment of a signal to calculate an error correction value, and a signal correction means and prediction which applies the error correction value to at least part of the... Agent: Freescale Semiconductor, Inc. Law Department

20090193319 - Data bus system, its encoder/decoder and encoding/decoding method: The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication... Agent: Ibm Corporation (swp)

20090193320 - Apparatus, and associated method, for decoding convolutionally encoded data: An apparatus, and an associated method, for correcting errors in decoded data, decoded by a convolutional decoder, such as an SOVA (Soft Output Viterbi Algorithm). A CRC check is performed upon the decoded data. If the CRC check fails, a conclusion is made that the decoded data contains errors. Portions... Agent: Research In Motion Attn: Glenda Wolfe

20090193321 - Viterbi decoder and viterbi decoding method: A Viterbi decoder and a Viterbi decoding method are provided for simplifying hardware and increasing an operation speed by using a decision feedback unit selecting one of at least two levels based on at least one survivor symbol fed back from a path memory unit. The Viterbi decoder includes a... Agent: Stein Mcewen, LLP

20090193322 - Information processing apparatus including transfer device for transferring data: According to an aspect of an embodiment, an apparatus has a first storage, a read write unit for reading and writing data from/into the first storage, a first error detector for detecting an error of data read out from the first storage, an address storage for storing an address of... Agent: Fujitsu Patent Center C/o Cpa Global

20090193323 - Apparatus and method for decoding in mobile communication system: Provided are an apparatus and a method for improving the performance of a decoder by improving a decoding speed when correcting an error of a control signal in Long Term Evolution (LTE). The apparatus includes an error determination unit for performing a traceback operation on a received signal, and simultaneously... Agent: The Farrell Law Firm, LLP

20090193324 - Image data test unit, image apparatus having the same, and method of testing image data using the same: An image data test unit includes a data acquisition unit configured to acquire image data having individual frames, an image data temporary storage unit configured to receive the acquired image data from the data acquisition unit to store a certain amount of the image data, and a test calculation unit... Agent: Stanzione & Kim, LLP

20090187785 - Flash memory data correction and scrub techniques: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20090187786 - Parity data management system apparatus and method: An apparatus for parity data management receives a write command and write data from a computing device. The apparatus also builds a parity control structure corresponding to updating a redundant disk array with the write data and stores the parity control structure in a persistent memory buffer of the computing... Agent: Kunzler & Mckenzie

20090187787 - Transfer of data from positional data sources to partitioned databases in restartable environments: Method, computer program product, and system for transferring data from positional data sources to partitioned databases are provided. A record is read from a positional data source. The record is to be written to one of a plurality of partitions of a database. A position of the record in the... Agent: Patterson & Sheridan, LLP/ibm Svl

20090187790 - Generation of trace elements within a data processing apparatus: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to... Agent: Nixon & Vanderhye P.C.

20090187789 - Method and apparatus for handling shared hardware and software debug resource events in a data processing system: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment,... Agent: Freescale Semiconductor, Inc. Law Department

20090187788 - Method of automatic regression testing: A method of automatic regression testing includes loading binary code representing a first version of a program, extracting a second version of the program embedded within the binary code of the first version of the program, executing a standalone model of the second version of the program based on the... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090187791 - Failure location detection using types in assembly files: A failure identification routine uses a two pass stack trace analysis in conjunction with a list of called types. As each method is called, a call list is generated with the called type, method, and various metadata. During the first pass stack trace analysis, each stack frame is analyzed to... Agent: Microsoft Corporation

20090187792 - Circuit arrangement and method for supporting and monitoring a microcontroller: A circuit arrangement for supporting and monitoring a microcontroller, which is constructed externally of the microcontroller, comprises a watchdog circuit for monitoring the microcontroller, which circuit outputs an error signal if not reset by the microcontroller within a watchdog period, and an interrupt circuit, which feeds important system messages to... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090187793 - Effective method to perform memory test using multiple processor unit, dma, and simd instruction: To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a... Agent: Ibm Corporation (swp)

20090187795 - Network performance and reliability evaluation taking into account multiple traffic matrices: Network performability characteristics with improved accuracy are derived by taking into account, in the various analyzed network failure states, attributes of elements at the logical level other than just the capacities of edges, as well as by taking into account one or more “abstract components,” such as scheduled maintenance, and... Agent: At & T Legal Department - Slusky

20090187794 - System and method for providing a memory device having a shared error feedback pin: A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090187796 - Method and apparatus for providing intelligent error messaging: A method and apparatus for providing intelligent error messaging is disclosed wherein a user of a mobile communications device is provided with descriptive error messaging information to assist the user in overcoming errors associated with the processing of electronic messages and data. For example, when the mobile device is being... Agent: Bereskin And Parr

20090187797 - Providing collection transparency information to an end user to achieve a guaranteed quality document search and production in electronic data discovery: Full text index-ability, indexing, and container extraction status of files in a collection repository is displayed to a user in connection with content management in EDiscovery. Thus, the user knows which files failed to index and explode and which files that are not indexable. The user also knows which files... Agent: Glenn Patent Group

20090187798 - Nonvolatile memory having non-power of two memory capacity: A nonvolatile memory having a non-power of two memory capacity is disclosed. The nonvolatile memory device includes at least one plane. The plane includes a plurality of blocks with each of the blocks divided into a number of pages and each of the blocks defined along a first dimension by... Agent: Mosaid Technologies Incorporated

20090187799 - Common test logic for multiple operation modes: In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn,... Agent: Trop, Pruner & Hu, P.C.

20090187800 - Phase shifter with reduced linear dependency: A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs... Agent: Klarquist Sparkman, LLP

20090187801 - Method and system to perform at-speed testing: Herein described are at least a method and a system to perform at-speed scan testing of a digital integrated circuit chip. The digital integrated circuit chip is segmented into a plurality of segments wherein each segment comprises a signal conditioning circuitry. In a representative embodiment, the signal conditioning circuitry conditions... Agent: Mcandrews Held & Malloy, Ltd

20090187802 - Decoding device and method, program, and recording medium: A decoding device for estimating an information word before being coded, wherein a processing range is limited to a range narrower than values that can be assumed by a value used as input to the decoding device, and decoding including a process of performing an operation referring to a look-up... Agent: Robert J. Depke Lewis T. Steadman

20090187803 - Decoding of error correction code using partial bit inversion: A method includes receiving an Error Correction Code (ECC) code word, which includes multiple encoded bits that represent data and have a bit order. Multiple subsets of the encoded bits are selected using a selection criterion that does not sequentially follow the bit order. For each subset in at least... Agent: D. Kligler I.p. Services Ltd

20090187804 - Ldpc (low density parity check) coding and interleaving implemented in mimo communication systems: LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. A variety of communication device types are also presented that may employ the error correcting coding (ECC) using... Agent: Garlick Harrison & Markison

20090187805 - Turbo decoding module supporting state n metric value normalization operations: A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples... Agent: Garlick Harrison & Markison

20090187806 - System and method for error detection in a redundant memory system: A system and method is disclosed for detecting errors in memory. A memory subsystem that includes a set of parallel memory channels is disclosed. Data is saved such that a duplicate copy of data is saved to the opposite memory channel according to a horizontal mirroring scheme or a vertical... Agent: Baker Botts, LLP

20090187807 - Method for optimizing block coding parameters, a communications controller employing the method and a communications node and link employing the controller: A method of determining optimal FEC configuration parameters, a communications controller, a communications link and a communications node is disclosed. In one embodiment, the communications controller, includes: (1) a processor, (2) a communications system information collector configured to receive operational information from a communications system having a block encoder, a... Agent: Texas Instruments Incorporated

20090187808 - Systems and methods for efficient parallel implementation of burst error correction codes: The present invention provides systems and methods for an efficient, parallel implementation of burst error correction codes, such as the Fire code. The present invention includes a FEC decoder which is pipelined to simultaneously perform syndrome computation, error trapping and syndrome normalization, and error correction. The pipelined implementation can apply... Agent: Clements Bernard PLLC

20090187809 - Integrated circuit including an ecc error counter: An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether... Agent: Dicke, Billig & Czaja

20090187810 - Error correction coding method and device: An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths... Agent: Sughrue Mion, PLLC

20090187811 - Method and system for providing low density parity check (ldpc) encoding: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences... Agent: The Directv Group, Inc. Patent Docket Administration

20090187812 - Processing module, error correction decoding circuit, and processing method for error locator polynomial: A Euclid processing module for binary BCH code which have been encoded with multidimensional Galois fields, and which correct a large number of word errors. The coefficients of polynomials Ri(z) and Bi(z) are stored in registers, and they are subjected to Galois field calculations by a processing module. The results... Agent: Mcdermott Will & Emery LLP

20090187813 - Methods and apparatus for reduced complexity soft-output viterbi detection: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability... Agent: Ryan, Mason & Lewis, LLP

20090183022 - Failure response support apparatus and failure response support method: A recording medium stores a program which causes a computer to execute a process for responding to failure of a management subject apparatus, based on incident information. The program causes the computer to execute a management procedure. The procedure manages steps of the response to the failure with the incident... Agent: Greer, Burns & Crain

20090183021 - Method and system for modeling, validating and automatically resolving goals and dependencies between elements within a topology: Computer implemented method, system and computer usable program code for configuring a computing system. A system for configuring a computing system includes a mechanism for creating a model of a computing system, a validator for determining whether there are any errors in the model, and a resolver, responsive to determining... Agent: Duke W. Yee

20090183023 - Method and apparatus for time-based event correlation: A method and apparatus for fault analysis and fault isolation in a system of networked processors by using a central event correlation function and logical fault signature to provide for fault isolation of failed processing elements is presented. This central event correlation method uses asynchronous events from multiple input sources... Agent: Fay Sharpe/lucent

20090183024 - System management infrastructure for corrective actions to servers with shared resources: A corrective action method or subsystem for providing corrective actions in a for a computing domain shared among multiple customers wherein different domain resources are shared by different customers, and each customer's corrective action preferences are accommodated differently according a repository of customer preferences. A database may be queried when... Agent: Ibm Corporation (rhf)

20090183025 - Autonomous diagnosis and repair of storage components: A method for the autonomous diagnosis and repair of user-configured storage subsystem components in a storage environment is provided. The method includes monitoring the user-configured storage subsystem components to identify an error associated with a first component of the user-configured storage subsystem components, the error corresponding to an error code,... Agent: Griffiths & Seaton PLLC (ibm)

20090183026 - Thresholding hardware errors: A system is provided to protect against ill-behaved microcode by balancing between an actual occurrence of a hardware problem and a microcode bug setting a flag appearing as a hardware problem. In this method, the error recovery is performed only on a single piece of hardware and no further error... Agent: Maxvalueip Consulting LLC

20090183027 - Checkpointing and restoring user space data structures used by an application: Provided are a method, system, and article of manufacture for checkpointing and restoring user space data structures used by an application accessing a data structure maintained by an operating system for an executing application. Information in the accessed data structure is saved with checkpoint information for the application. An operation... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090183028 - Method and system for modeling, validating and automatically resolving goals and dependencies between elements within a topology: Computer implemented method, system and computer usable program code for configuring a computing system. A determination is made whether there are any errors in the model, and responsive to determining that there is at least one error in the model, a determination is made whether there is at least one... Agent: Duke W. Yee

20090183029 - Root cause analysis in a system having a plurality of inter-related elements: A method of performing root cause analysis for use in a system comprising a plurality of inter-related elements, wherein at least some of the elements experience one or more abnormal conditions, comprising defining one or more conditions for more than one element symptomatic of abnormal operation of the element; defining... Agent: Hewlett Packard Company

20090183030 - Episodic cause analysis: Managing a root cause analysis and outputting an identified root cause, for use in a system comprising a plurality of inter-related elements wherein at least some of the elements experience one or more anomalous states, comprising receiving initial indicators of system element states symptomatic of anomalous element operation, selecting an... Agent: Hewlett Packard Company

20090183031 - Engine for performing root cause and effect analysis: An engine for performing root cause analysis on a system comprising a plurality of elements in a modeled domain, the engine comprising a module loader and parser for loading modules of computer code containing computer language statements modeling elements of the system, including one or more of model type definitions,... Agent: Hewlett Packard Company

20090183032 - Data processing apparatus and method for testing stability of memory cells in a memory device: A data processing apparatus and method are provided for testing stability of memory cells in a memory device. A data processing apparatus comprises a memory device having an array of memory cells for storing data values. Test circuitry is employed in a test mode of operation to execute one or... Agent: Nixon & Vanderhye, PC

20090183033 - Fault location device, communication device, and fault location method: A fault location device detects a communication device connected to a broken communication line from among communication devices that carry out communications between each other through a two-wire communication line. The communication device, when detecting a communication error, stores communication error time and a communication error counter accumulated value indicating... Agent: Sughrue Mion, PLLC

20090183034 - Trace synchronization: A data processing apparatus having one or more trace data sources is provided in which the trace data sources operate to generate respective streams of trace data. At least one of said trace data sources comprises a trace data generator responsive to activity in monitored circuitry to generate trace data... Agent: Nixon & Vanderhye, PC

20090183035 - Processor including hybrid redundancy for logic error protection: A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090183036 - Ramped error logging system: A method for logging a repetitive error in a computer system is provided. The repetitive error is logged after each of a series of progressively increasing time periods. The logging commences when the repetitive error is first identified and concludes when the repetitive error is no longer identified.... Agent: Griffiths & Seaton PLLC (ibm)

20090183037 - Statistical processing apparatus capable of reducing storage space for storing statistical occurrence frequency data and a processing method therefor: In a network analyzer, a storage stores a set of occurrence frequencies in entire, first and final intervals. An arithmetic processor counts the value while deleting the frequency information based on the stored frequency information. The arithmetic processor determines whether to estimate the occurrence frequency in the interval next to... Agent: Rabin & Berdo, PC

20090183038 - Method for improving the integrity of communication means: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10−9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames,... Agent: Darby & Darby P.C.

20090183039 - Diagnostic interface architecture for memory device: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090183040 - Double data rate test interface and architecture: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows... Agent: Texas Instruments Incorporated

20090183042 - Adapting scan-bist architectures for low power operation: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan... Agent: Texas Instruments Incorporated

20090183041 - Continuous application and decompression of test patterns to a circuit-under-test: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan... Agent: Klarquist Sparkman, LLP

20090183043 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a digital circuit and a first-stage register circuit provided in a stage followed by the digital circuit. The digital circuit includes a logic circuit and a register circuit configured to temporarily retain a logic output from the logic circuit. The first-stage register circuit has a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090183044 - Method and circuit for implementing enhanced lbist testing of paths including arrays: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090183045 - Testing system for a device under test: A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090183046 - Programmable test clock generation responsive to clock signal characterization: Disclosed are, inter alia, methods, apparatus, mechanisms, and means for characterizing a clock signal within an application-specific integrated circuit (ASIC), and then, also on the ASIC, generating a testing clock signal based on the characterization of the operative clock signal for testing purposes. An ASIC includes a clock signal characterization... Agent: The Law Office Of Kirk D. Williams

20090183047 - Method for generating ldpc codes and apparatus using ldpc codes: A method for generating an LDPC (low density parity check) code, comprising steps of: determining the number of rows and the number of columns in a matrix for forming the LDPC code according to predetermined code rate and constraint length; dividing the matrix into a plurality of layers according to... Agent: Staas & Halsey LLP

20090183049 - Probabilistic error correction in multi-bit-per-cell flash memory: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention,... Agent: Mark M. Friedman

20090183048 - Systems and methods for ldpc coded modulation: Typical forward error correction methods employ Trellis Code Modulation. By substituting low density parity check coding in place of the convolution code as part of a combined modulation and encoding procedure, low density parity check coding and modulation can be performed. The low density parity check codes have no error... Agent: Jason H. Vick Sheridan Ross, PC

20090183050 - Forward error correction scheme for data channels using universal turbo codes: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a... Agent: The Directv Group, Inc. Patent Docket Administration

20090183051 - Memory system with cyclic redundancy check: A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to pre-store an address signal associated with at least one... Agent: Edell, Shapiro & Finnan, LLC

20090183052 - Semiconductor memory device and method of controlling the same: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090183054 - Information recording medium, recording/reproducing apparatus and recording/reproducing method: An information recording medium, a recording and/or reproducing apparatus, and a recording and/or reproducing method in which an access time and a frequency of seek operations can be reduced in the information recording medium implementing logical overwrite, thereby allowing noise and power consumption to be reduced. The information recording medium... Agent: Stein Mcewen, LLP

20090183053 - Memory apparatus and method using erasure error correction to reduce power consumption: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090183055 - Convolutional decoding: In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes. The convolutional codes may also be block convolutional codes. The lazy... Agent: Fish & Richardson PC

20090183056 - Validating objects in a data storage system: Objects stored in a storage system (such as a file server system) are protected by multiple levels of validation. Each chunk of an object is associated with a chunk validator, and an object validator is computed for the object based on the chunk validators. The object validator is stored in... Agent: Bromberg & Sunstein LLP

20090183058 - Communications channel interposer, method and program product for verifying integrity of untrusted subsystem responses to a request: In a communications channel coupled to multiple duplicated subsystems, a method, interposer and program product are provided for verifying integrity of subsystem responses. Within the communications channel, a first checksum is calculated with receipt of a first response from a first subsystem responsive to a common request, and a second... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090183057 - Offloading iscsi without toe: A ULP offload engine system, method and associated data structure are provided for performing protocol offloads without requiring a TCP offload engine (TOE). In an embodiment, the ULP offload engine provides iSCSI offload services.... Agent: Sawyer Law Group LLP

20090183059 - Lossy compression technique for video encoder bandwidth reduction using compression error data: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation... Agent: Texas Instruments Incorporated

20090177910 - Method of recovering from software failures using replanning: A method for recovering from software failures, includes: receiving failure information that identifies a failing component of a first processing graph; modifying a planning domain that includes a plurality of component descriptions according to the failure information; and composing a second processing graph by using the modified planning domain so... Agent: F. Chau & Associates, LLC

20090177911 - Apparatus, system, and method to prevent queue stalling: An apparatus, system, and method are disclosed to prevent queue stalling. The apparatus to prevent queue stalling is provided with a plurality of modules configured to functionally execute the necessary steps of detecting a connection failure on a first logical path, wherein the first logical path is associated with a... Agent: Kunzler & Mckenzie

20090177912 - Reconfigurable circuit with redundant reconfigurable cluster(s): A reconfigurable circuit having redundant reconfigurable clusters is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C.

20090177914 - Clustering infrastructure system and method: A system and method for configuring a cluster of computer nodes to save and restore state in the cluster in the event of node failures. The system and method are implemented through an application programming interface that includes a membership application, a locks application and a dataspace application. The membership... Agent: Ungaretti & Harris LLP Intellectual Property Group - Patents

20090177915 - Fault tolerant symmetric multi-computing system: A system enabled for fault-tolerant symmetric multi-computing using a group of nodes is described hereon. A symmetrical group of nodes networked using a reliable, ordered, and atomic group-to-group TCP communication system is used in providing fault-tolerance and single system image to client applications. The communication between the client and the... Agent: Fenwick & West LLP

20090177913 - Systems and methods for automated data anomaly correction in a computer network: Systems and methods for correcting an anomaly in a target computer that is part of a network of computers. An anomaly is detected in data stored on a target computer and it is determined what corrective data is needed to correct the anomaly. A donor computer with the corrective data... Agent: Edell, Shapiro & Finnan, LLC

20090177917 - Process, apparatus, and program for system management: In a system management apparatus, a failure detection unit detects a readout failure in one of blocks constituting distributed data stored in a first RAID disk array. A request unit requests a computer to supplement one of the blocks of the distributed data stored in the first RAID disk array... Agent: Greer, Burns & Crain

20090177916 - Storage system, controller of storage system, control method of storage system: A storage system includes: an interface that connects the storage system to a higher-level device; a first storage unit that stores data which is transferred from the higher-level device through the interface; a second storage unit onto which data stored in the first storage unit is copied; a management table... Agent: Fujitsu Patent Center C/o Cpa Global

20090177918 - Storage redundant array of independent drives: A computer implemented method, apparatus, and computer usable program product for managing redundant array of independent drives. In response to a failure of a hard disk in a first RAID array, the process calculates an amount of free capacity available across a set of remaining hard disks in the first... Agent: Duke W. Yee

20090177919 - Dynamic redundancy for microprocessor components and circuits placed in nonoperational modes: An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational... Agent: Cantor Colburn LLP-ibm Yorktown

20090177920 - Automated configuration of medical practice management systems: A user (e.g., medical office manager, medical office insurance administrator, doctor) utilizes a medical practice configuration interface (e.g., web page) to input information about the user's medical practice (e.g., address, insurance plans, doctors, hospitals that the doctors utilize). Based on this information and/or rules associated with the insurance plans accepted... Agent: Proskauer Rose LLP

20090177921 - Portable electronic device and control method thereof: A flag which is set to the on state when a process of writing data as a data file into a storage area which is permitted to be written only once results in failure is previously set in a data memory of an IC card. When a flag of a... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090177922 - Detection of system battery errors: In an example embodiment, a method is provided to identify an error associated with a system battery. This system battery is operably associated with a computing device and is used to power the computing device. A parameter of the system battery is tested and an error associated with the system... Agent: Schwegman, Lundberg & Woessner/apple

20090177923 - Apparatus and method for test and debug of a processor/core having advanced power management: An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have... Agent: Texas Instruments Incorporated

20090177924 - Context sensitive detection of failing i/o devices: Methods for context sensitive detection of failing I/O devices sample and record a response time of an I/O device for each of a first plurality of time intervals to generate a first plurality of sampled and recorded response times, and to determine whether or not at least one I/O error... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090177925 - Method for memory testing: A method for memory testing implemented on an embedded system, the method comprising steps of loading a booting program when the embedded system is booted; activating a RAM of the embedded system by the booting program; duplicating the booting program itself and writing the duplicated booting program into a first... Agent: Joe Mckinney Muncy

20090177927 - Determination of impact of a failure of a component for one or more services: A method and system for determining an impact of a failure of a component for one or more services that the component is supporting. A data feed received from a processing node includes data indicative of an identity and system status of a component running on the processing node. The... Agent: Schmeiser, Olsen & Watts

20090177926 - Incident simulation support environment: This disclosure describes software for supporting an application. In one aspect, software for supporting a business application receives error and dynamic context information from a remote business application in response to an incident. The dynamic context information at least partially identifies one or more business objects (BOs) associated with the... Agent: Fish & Richardson, P.C.

20090177928 - Apparatus, method and computer program product for generating trace data: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one... Agent: Nixon & Vanderhye P.C.

20090177929 - Method and apparatus for adaptive declarative monitoring: A method of and apparatus for monitoring a computer system includes defining a monitoring policy for the computer system. At least one computer is employed to determine a status of a state of the computer system relative to the monitoring policy. At least one computer is employed to determine a... Agent: Dla Piper LLP Us

20090177930 - Timing controller, error detection method of the timing controller, and display device having the timing controller: A timing controller includes a control unit, an error signal generating unit, and an operation detecting unit. The control unit transfers a plurality of input data and outputs a plurality of completion signals according to transfer states of the respective data. The error signal generating unit generates a plurality of... Agent: F. Chau & Associates, LLC

20090177931 - Memory device and error control codes decoding method: Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error... Agent: Harness, Dickey & Pierce, P.L.C

20090177932 - Method and apparatus for tracking, reporting and correcting single-bit memory errors: Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit... Agent: Schwegman, Lundberg & Woessner, P.A.

20090177933 - Decompressor/prpg for applying pseudo-random and deterministic test patterns: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under... Agent: Klarquist Sparkman, LLP

20090177934 - Apparatus for testing embedded memory read paths: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090177935 - Scan chain cell with delay testing capability: A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38... Agent: Nixon & Vanderhye, PC

20090177936 - Direct logic diagnostics with signature-based fault dictionaries: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than... Agent: Klarquist Sparkman, LLP

20090177937 - Method for resource allocation for hybrid-automatic repeat request: A resource allocation method for a HARQ is disclosed. This resource allocation method includes, transmitting an MAP message having specific information indicating whether or not a differential allocation is supported, storing MAP information contained in the MAP message during a predetermined frame, and upon receiving an NACK message during the... Agent: Birch Stewart Kolasch & Birch

20090177938 - Cognitive and universal impulse noise protection: Impulse noise from nearby or intense electrical sources can disrupt communications over digital subscriber lines. There are many methods to deal with errors produced by impulse noise sources. Forward error correction (FEC) codes such as Reed Solomon coding along with scrambling and interleaving are used to correct small errors. However,... Agent: Conexant Systems , Inc.

20090177940 - Apparatus and method for error correction in mobile wireless applications incorporating erasure table data: A receiver (120) is configured to receive data over a communications link. A decapsulator (122) is coupled to the receiver and configured to create datagrams and erasure attributes associated with the datagrams. A decoder (124) is coupled to the decapsulator and configured to store the datagrams in a frame table... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090177941 - Managing common uplink resources in a cellular radio communications system: The technology in this application provides for efficient use of a common uplink radio resource, like the common E-DCH resource. A UE lacking a valid radio network identifier, e.g., a UE in an idle mode, receives a data unit and adds error detection bits to generate a new data unit.... Agent: Nixon & Vanderhye, PC

20090177939 - Method for coding biometric data, method for controlling identity and devices for carrying out said methods: The invention relates to a coding method consisting of the following steps: biometric data associated with an individual is obtained; a word, relating to an error correction code, selected in older to correct a quantity of errors in a relation to a statistical quantity of errors between two biometric measurements... Agent: Miller, Matthias & Hull

20090177942 - Systems and methods for media container file generation: A method includes organizing a first media source block in the media container file; calculating forward error correction (FEC) redundancy data based on the first media source block; organizing the FEC redundancy data in at least one FEC reservoir in the media container file; providing, in the media container file,... Agent: Nokia, Inc.

20090177943 - Error correction coding using soft information and interleaving: Error correction coding using soft information and interleaving. A symbol interleaved ECC signal (which can be a symbol interleaved multi-level ECC signal) initially undergoes detection (e.g., such as using SOVA detection) to generate soft information. A decoder uses the soft information to generate estimates of at least one symbol (or... Agent: Garlick Harrison & Markison

20090177944 - Semiconductor memory device and its control method: A semiconductor memory device includes a temporary storage circuit configured to receive data items and store the data items in rows and columns, a detecting code generator configured to generate first detecting codes used to detect errors in the data items, respectively, a first correcting code generator configured to generate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090177945 - Polarization mode dispersion compensation using bcjr equalizer and iterative ldpc decoding: A turbo equalizer includes a Bahl-Cocke-Jelinek-Raviv (BCJR) equalizer configured to receive a transmitted signal and partially cancel inter-symbol interference (ISI) due to polarization-mode dispersion (PMD). A low-density parity check (LDPC) decoder is coupled to the BCJR equalizer to receive channel bit reliabilities therefrom. The LDPC decoder iteratively provides extrinsic soft... Agent: Nec Laboratories America, Inc.

20090177946 - Memory initialization time reduction: A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or... Agent: Robert R. Williams IBM Corporation

20090177947 - Method for appending data to tape medium, and apparatus employing the same: An information recording apparatus includes a writing system for writing the datasets to the recording medium, so that each of the datasets can be identified from a certain number indicating an order that each of the datasets was sequentially written to the recording medium, and from the number of writing... Agent: Zilka-kotab, PC- Ibm

20090177948 - System, method and apparatus for fec encoding and decoding: A system, method and apparatus are provided for encoding and decoding a source file. The source file is encoded by dividing it into a plurality of shares comprised of a plurality of packets. A bit vector is generated. For at least one share, an FEC packet is generated by XOR'ing... Agent: Fitzpatrick Cella Harper & Scinto

20090177949 - Method for protecting multimedia data using additional network abstraction layers (nal): A method for protecting multimedia data encoded by the H.264 standard, the data being encapsulated in a structure of the network abstraction layer or NAL type, characterized in that the user inserts at least one redundancy NAL containing the error-correcting code used for transmitting the data.... Agent: Lowe Hauptman & Berner, LLP

20090177950 - Rate matching method in mobile communication system: A rate matching method is provided for a mobile communication system that performs an adjustment to a code rate based on an optimal level by puncturing or repetition to respective bit streams of transport channels. The rate matching method is preferably applicable to uplink and downlink rate matching for channel... Agent: Lee, Hong, Degerman, Kang & Waimey

20090177951 - Priori decoding scheme based on map messages: A method and apparatus for decoding encoded data bits of a wireless communication transmission are provided. A set of a-priori bit values corresponding to known bit values of the encoded data bits may be generated. Decoding paths that correspond to decoded data bits that are inconsistent with the a-priori bit... Agent: Qualcomm Incorporated

20090177952 - Transcoder and receiver: An error extracting unit 7 detects that an error has occurred in a medium stream received, and determines the position of the occurrence. An error specific information adding unit 13 adds error specific information indicating that the error has occurred before the transcoding to an access unit on which the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090177953 - Method and system for updating topology changes of a computer network: A method for detecting topology changes of a computer network, includes the following steps of acquisition of the raw data from the configuration tables of the network elements during successive primary pollings, the following steps being carried out between two successive primary pollings: calculation and storage of a checksum value... Agent: Greer, Burns & Crain

20090177954 - Code error detecting device, wireless system and code error detecting method: A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090172461 - Conditional actions based on runtime conditions of a computer system environment: Conditionally performing delegated actions based on runtime conditions of the environment. A component of an Information Technology environment conditionally performs an action, such as its own recovery, based on whether the component can have such action delegated to it and/or whether that component is currently being shared by multiple business... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090172460 - Defining a computer recovery process that matches the scope of outage: Recovery processing is defined that matches the scope of an outage. A programmatic analysis of the resources that have been impacted, of implications of the failure and what degradations have occurred is performed to construct an appropriate level of recovery. This includes selecting the appropriate set of resources to be... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090172462 - Method and system for recovery of a computing environment: A method and system for recovery of a computing environment includes monitoring during a pre-boot phase and a runtime phase of a computing device for selection of a hot key sequence by a user and performing a recovery action in response to the selection of the hot key sequence by... Agent: Barnes & Thornburg, LLP

20090172463 - Method, system and machine accessible medium of a reconnect mechanism in a distributed system (cluster-wide reconnect mechanism): A method, system and machine accessible medium for validating a plurality of connections to a backend in a distributed system. A connection request requiring access to a backend is processed at a first node of a distributed system. The access to the backend enabled through a connection from a plurality... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090172464 - Method and apparatus for repairing uncorrectable drive errors in an integrated network attached storage device: In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk... Agent: Mendelsohn & Associates, P.C.

20090172465 - Semiconductor device having coupling elimination circuit: A semiconductor device including a plurality of repairable signal lines, the device including a first driver adapted to maintain a first portion of each defective one of the repairable signal lines at a first voltage level, and a second driver adapted to drive a second portion of each of the... Agent: Lee & Morse, P.C.

20090172467 - Information processing apparatus: An information processing apparatus includes: a nonvolatile memory that has a start block for storing a boot program and a spare block for storing a spare of the boot program; and a system controller that reads out the boot program from the start block and executes start-up process in accordance... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090172466 - Nand power fail recovery: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.... Agent: Caven & Aghevli LLC C/o Cpa Global

20090172468 - Method for providing deferred maintenance on storage subsystems: A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare... Agent: Ip Authority, LLC Ramraj Soundararajan

20090172469 - Method, apparatus, logic device and storage system for power-fail protection: A method, apparatus, logic device, and storage system for power-fail protection are disclosed. The method includes: when a system power supply fails, supplying, by a battery, power to a south bridge chip (SBC), a non-volatile flash storage medium, an interface conversion circuit (ICC) between the SBC and the non-volatile flash... Agent: Leydig, Voit & Mayer, Ltd (for Huawei Technologies Co., Ltd)

20090172470 - Managing processing of a computing environment during failures of the environment: Recovery processing is provided for management components of an Information Technology (IT) environment. The recovery processing recovers the components, as well as performs one or more tasks that were being performed by the components prior to recovery.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090172471 - Method and system for recovery from an error in a computing device: A method and system for supporting recovery of a computing device includes determining and storing a sub-set of firmware instructions used to establish a pre-boot environment and executing the sub-set of firmware instructions in response to an error.... Agent: Barnes & Thornburg, LLP

20090172472 - Computer, and method for error-detecting and booting of bios thereof: A computer has a first BIOS unit, a second BIOS unit, a bus, a detecting unit, and a first delay unit. The detecting unit is connected to the bus, the first BIOS unit, and the second BIOS unit operationally. In addition, the first delay unit is electrically connected to the... Agent: Jianq Chyun Intellectual Property Office

20090172474 - Network diagnostic systems and methods for light levels of optical signals: A network diagnostic system may include a network diagnostic device. The network diagnostic device may be configured to receive data indicating a light level of an optical signal and to perform at least one network diagnostic function at least partially in response to the receipt of the data. A network... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090172473 - System and method for synchronizing test runs on separate systems: A system and method provide for test automation of a process running on separated systems. The systems may be separated physically and/or logically separated. The system and method provide that all information required for a test run are made available on one system. In an embodiment, a central component is... Agent: Kenyon & Kenyon LLP

20090172475 - Remote resolution of software program problems: Method, system, and computer program product for remotely resolving problems in software programs are provided. A problem is detected in a software program. An instant message is sent to an operator to notify the operator of the problem detected in the software program. An instant message is received from the... Agent: Ibm Corp. C/o Sawyer Law Group LLP

20090172476 - Test executive system with memory leak detection for user code modules: A system and method for automatically detecting heap corruption errors and memory leak errors caused by user-supplied code modules that are called by steps of a test executive sequence. The test executive sequence may first be created by including a plurality of test executive steps in the test executive sequence... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090172477 - Remote monitoring system, terminal management server and terminal management server control program: An insulation monitoring system, functioning as a remote monitoring system, comprises a plurality of insulation monitoring terminals, functioning as remote monitoring terminals, for monitoring facilities and a terminal management server controlling the insulation monitoring terminals. The insulation monitoring terminals and terminal management server are connected each other to bidirectionally transmit... Agent: Foley And Lardner LLP Suite 500

20090172478 - Information processing apparatus, backup device and information processing method: According to an aspect of the present invention, there is provided an information processing apparatus including: a connector to which a backup device is connected; a data storing unit that stores an objective data; and a processor that is configured: to write the objective data to the backup device as... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090172479 - Semiconductor memory device and method for testing the same: A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more... Agent: Mannava & Kang, P.C.

20090172480 - System and method for testing a packetized memory device: Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20090172481 - Partial voltage read of memory: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction... Agent: Fish & Richardson P.C.

20090172482 - Methods for performing fail test, block management, erasing and programming in a nonvolatile memory device: Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for... Agent: Townsend And Townsend And Crew, LLP

20090172483 - On-chip failure analysis circuit and on-chip failure analysis method: An on-chip failure analysis circuit for analyzing a memory comprises a memory in which data is stored, a built-in self test unit which tests the memory, an failure detection unit which detects an failure of output of the memory, an fail data storage unit in which fail data is stored,... Agent: Turocy & Watson, LLP

20090172484 - method for implementing a serialization construct within an environment of parallel data flow graphs: A serialization construct is implemented within an environment of a number of parallel data flow graphs. A quiesce node is appended to every active data flow graph. The quiesce node prevents a token from passing to a next data flow graph within a chain before an execution of the active... Agent: International Business Machines Corporation Richard Lau

20090172485 - Interconnections for plural and hierarchical p1500 test wrappers: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides... Agent: Texas Instruments Incorporated

20090172486 - Testing embedded memories in an integrated circuit: Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective... Agent: Klarquist Sparkman, LLP

20090172487 - Multiple pbist controllers: A system on a single integrated circuit chip (SoC) includes a plurality of operational circuits to be tested. A plurality of programmable built-in self-test (pBIST) controllers is connected to respective ones of the plurality of operational circuits in a manner that allows the pBIST controllers to test the respective operation... Agent: Texas Instruments Incorporated

20090172488 - Semiconductor device: A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit;... Agent: Miles & Stockbridge PC

20090172489 - Circuit arrangement and method for checking the function of a logic circuit in a circuit arrangement: A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated from the input data by logic-circuit-internal combinations, such that the output data are in a predetermined relationship... Agent: Dickstein Shapiro LLP

20090172490 - Data retransmission method and wireless communication apparatus: A data retransmission method for retransmitting a data using a wireless communication, including: receiving data transmitted from a transmitting apparatus; determining whether the received data is correct or not; transmitting data including information indicating that the received data is received correctly to the transmitting apparatus upon being determined the received... Agent: Myers Wolin, LLC

20090172491 - Methods and systems for error detection of data transmission: The invention provides an error detection method for data transmission in a transmission system with a first device, a second device and a data line. The method comprises the following steps. Firstly, a clock signal is sent to synchronize the first and second devices. Secondly, at least one serial data... Agent: Birch Stewart Kolasch & Birch

20090172494 - Data processing apparatus and method, and program: In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In... Agent: Young & Thompson

20090172492 - Method and apparatus for interleaving low density parity check (ldpc) codes over mobile satellite channels: Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the... Agent: Kramer Levin Naftalis & Frankel LLP Intellectual Property Department

20090172493 - Method and device for decoding low density parity check code: An apparatus for decoding a Low Density Parity Check (LDPC) is provided. The apparatus includes a variable node message memory for storing a variable node message vector, a controller for controlling a node computing unit to read from and write to the variable node message memory and controlling an iteration... Agent: JeffersonIPLaw, LLP

20090172495 - Methods and apparatuses for parallel decoding and data processing of turbo codes: Methods and apparatuses for parallel decoding and data processing of Turbo codes are provided. The method includes: a codeword dividing step for dividing a whole codeword into Q sub-blocks to form a plurality of boundaries between adjacent sub-blocks of the Q sub-blocks so as to decode the Q sub-blocks, wherein... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090172496 - Technique for memory imprint reliability improvement: One embodiment of the present invention relates to a method of reducing imprint of a memory cell. The method comprises adding an inversion condition bit operably associated with one or more memory cells storing a memory word. The inversion condition bit indicates whether the memory word represents an actual payload... Agent: Texas Instruments Incorporated

20090172497 - Data processing system and method for processing optical information: Provided is a data processing system for recording holographic optical information. The data processing system includes: a data interface constructing a data page by using data transmitted from a host information device; a memory storing data transmitted from the data interface; an encoder ECC-encoding data that is stored in the... Agent: Williams Mullen

20090172498 - Error correction in copy back memory operations: A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a... Agent: Martin Moynihan Prtsi, Inc.

20090172499 - Patrol function used in flash storage controller to detect data errors: A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.... Agent: Haynes And Boone, LLPIPSection

20090172500 - Application of a meta-viterbi algorithm for communication systems without intersymbol interference: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed... Agent: Mcandrews Held & Malloy, Ltd

20090172501 - Multi-state symbol error correction in matrix based codes: Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols... Agent: Diehl Servilla LLC

20090172503 - Decoding apparatus and decoding method: The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit... Agent: Young & Thompson

20090172502 - Method and apparatus for turbo code decoding: A method and apparatus for turbo code decoding are provided to reduce memory consumption during calculation of state metrics. In an embodiment of a turbo code decoder, a natural recursion unit comprises a plurality of add-compare-select (ACS) units performing natural recursion operations to generate a state metric. The original state... Agent: Quintero Law Office, PC

20090172504 - Memory architecture for viterbi decoder and operating method therefor: The Viterbi decoder is an essential module in a communication system, in which the power and the decoding latency are restricted. In the present invention, a power efficient low latency survivor memory architecture and an operating method for the Viterbi decoder are disclosed by providing a plurality of trace-forward units,... Agent: Wpat, PC

20090172505 - Magnetic data processing device, magnetic data processing method, and magnetic data processing program: In a magnetic data processing device, an input part sequentially receives magnetic data output from a magnetic sensor. A storage part stores a plurality of the magnetic data as a data set of statistical population. An index derivation part derives a distribution index of the data set of the statistical... Agent: Dickstein Shapiro LLP

20090172506 - Semiconductor device and signal processing method: A semiconductor device including a first processing unit processing an input signal based on a plurality of image compression standards, a signal generation unit outputting a switching signal to the first processing unit, a first calculation unit performing an operation on the input signal in accordance with a first coefficient... Agent: Staas & Halsey LLP

20090172507 - Information processing system: According to one embodiment, an information processing system is coupled to a number of sensors for receiving information generated by the sensors. The information processing system generates records from the received information and binds the records in a multi-dimensional structure including a temporal dimension and another dimension including other records... Agent: Baker Botts LLP