Error detection/correction and fault detection/recovery inventions 06/09

20090164832 - Methods and systems for generating availability management framework (amf) configurations: Techniques for generating a system model for use by and availability management framework (AMF) are described. Inputs are received, processed and mapped into outputs which are further processed into a configuration file in an Information Model Management (IMM) Service external Markup Language (XML) format which can be used as a... Agent: Ericsson Canada Inc. Patent Department

20090164833 - Methods and systems for automated processing of fallout orders: A system and method may include receiving an order and an error identifier, indexing a database based on the error identifier to identify a rule identifier, and indexing the database based on the rule identifier to identify a rule. The system and method may further include applying the rule to... Agent: Verizon Patent Management Group

20090164834 - Soft error recoverable storage element and soft error protection technique: A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney LLP

20090164835 - Method and system for survival of data plane through a total control plane failure: A system and method for retaining routes in a control plane learned by an inter-domain routing protocol in the event of a connectivity failure between routers. Routers are classified as either route reflectors or originators. A determination is made whether the connectivity failure occurred between a route reflector and an... Agent: At & T Legal Department - Ws Attn: Patent Docketing

20090164836 - Error correction in flash memory array: Systems and/or methods that facilitate that facilitate error correction of data stored in memory components, such as flash memory devices are presented. An optimized correction component can be used to break data into two or more data blocks. The optimized correction component can facilitated creating one or two redundancy blocks... Agent: Turocy & Watson, LLP

20090164838 - Microprocessor memory management: A memory for an electronic brake control system is divided into portions that are classified as critical and non-critical. Each portion is periodically tested for faults. Upon detection of a fault, the memory is reconfigured with any operations of the brake system associated with a critical memory portion permanently disabled... Agent: Macmillan Sobanski & Todd, LLC

20090164837 - Reliable memory for memory controller with multiple channels: One embodiment of the invention includes a memory RAS mode whereby a multi-channel memory controller utilizes both memory mirroring and memory sparing to form more complete memory redundancy loss protection.... Agent: Trop, Pruner & Hu, P.C.

20090164839 - Storage control apparatus and storage control method: A storage control apparatus monitors whether or not one or more storage management apparatuses are properly operating. A recovery target extraction unit extracts a recovery target storage area when the existence of a malfunctioning storage management apparatus is detected, the recovery target storage area being a storage area that has... Agent: Greer, Burns & Crain

20090164841 - System and method for improving the yield of integrated circuits containing memory: A system and method for increasing the yield of integrated circuits containing memory partitions the memory into regions and then independently tests each region to determine which, if any, of the memory regions contain one or more memory failures. The test results are stored for later retrieval. Prior to using... Agent: Patterson & Sheridan, LLP

20090164840 - System and method for managing root file system: There is provided a system including a cluster 11, a cluster 12 and an image server 20. A host 101a constituting the cluster 11 has a root file system 111a used to operate the host 101a in a local disk. The image server 20 has a root file system 221a... Agent: International Business Machines Corporation Dept. 18g

20090164842 - Method and system for enterprise memory management of memory modules: A method and system for enterprise memory management of memory modules of a computer system. The method includes scanning memory chips of a memory module for errors, analyzing a scrub error map corresponding to a scrubbing operation of the memory module, generating a scrub map summary based upon the scrub... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090164843 - Vibration-aware data reassignment: An aspect of the present disclosure relates to implementing a temporary reassignment of data based on a vibration condition. An exemplary method includes implementing a data operation for a portion of data and detecting a data error during the data operation. The method further includes obtaining an indication of a... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.

20090164844 - Storage management apparatus and storage system: A storage management apparatus manages a plurality of storage apparatuses connected to each other over a network in a storage system that distributes data among the storage apparatuses and stores the data therein. The storage management apparatus has a patrol process executing unit configured to execute a patrol process to... Agent: Greer, Burns & Crain

20090164845 - Device testing architecture, method and system: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison... Agent: Texas Instruments Incorporated

20090164846 - Fault injection in dynamic random access memory modules for performing built-in self-tests: Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20090164848 - Intelligent test framework: A system and method for testing an application or component is disclosed. A debugging agent connects to the application or component to monitor one or more test processes on the application or component according to a template-based configuration. A test framework defines the template-based configuration for the debugging agent, creates... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.

20090164847 - System and method for testing a software engine: A software engine has a base system in communication with service subsystems and test subsystems. The base system, the service subsystems, and the test subsystems are software applications that exchange data with one another while operating within the software engine. In one exemplary mode of operation, the base system receives... Agent: Verizon Patent Management Group

20090164849 - Terminal apparatus, fault diagnosis method and program thereof: A terminal apparatus diagnoses a status of operation of software with the execution of a plurality of diagnostic programs so as to diagnose contents established for the software related to a plurality of functional blocks of the terminal apparatus. The terminal apparatus includes a storage device, a controller, and a... Agent: Carter, Deluca, Farrell & Schmidt, LLP

20090164850 - Electronic supervisor: Electronic supervision may be provided. First, a stock number may be sent to a database server. The stock number may correspond to a product comprising, for example, an electrical cable. In response to sending the database server the stock number, specification information corresponding to the product may be received from... Agent: Merchant & Gould Southwire

20090164851 - Preservation of error data on a diskless platform: Systems and articles of manufacture for preserving error data on a computing platform that lacks non-volatile storage (e.g., a “diskless” platform) are provided. In response to detecting a platform error (e.g., automatically by hardware, software, or manually by a user when a wait or loop condition is suspected), platform error... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090164852 - Preemptive thermal management for a computing system based on cache performance: Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20090164853 - Systems and methods for remote monitoring in a computer network: Systems and methods for providing automated problem reporting in elements used in conjunction with computer networks are disclosed. The system comprises a plurality of elements that perform data migration operations and a reporting manager or monitor agent which monitors the elements and data migration operations. Upon detection of hardware or... Agent: Knobbe Martens Olson & Bear LLP

20090164854 - System and method for measuring and depicting performance of a serial communications link: A system for measuring performance of a serial communications link includes a system under test including at least one transmitter and at least one receiver coupled together via a serial data communications link, wherein at least one of the transmitter and the receiver has at least one tunable parameter, at... Agent: Agilent Technologies Inc.

20090164855 - Method for scrubbing storage in a computer memory: A method for scrubbing storage in a computer memory which includes a plurality of memory modules each having plurality of memory chips. The method includes selecting a pattern that correlates with physical structures for scanning the memory chips of the memory modules for errors, scanning a memory chip of a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090164856 - System and method for input/output characterization: A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage... Agent: Texas Instruments Incorporated

20090164857 - Testing embedded circuits with the aid of a separate supply voltage: Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is... Agent: Duane Morris LLP - PhiladelphiaIPDepartment

20090164858 - Protecting an integrated circuit test mode: An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090164859 - Driving circuit of display apparatus and driving method thereof: A driving circuit of a display apparatus includes a decoder coupled to a plurality of scan lines of a display panel for decoding a plurality of input signals to output a plurality of scan line driving signals to thereby enable at least one scan line of the plurality of scan... Agent: North America Intellectual Property Corporation

20090164860 - Semiconductor integrated circuit and method for testing the same: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power... Agent: Mcdermott Will & Emery LLP

20090164861 - Method and apparatus for a constrained random test bench: A constrained random test bench methodology employing an instruction abstraction layer. The instruction abstraction layer includes an instruction streamer for generating random test instruction sequences that preserve instruction order dependencies and randomly selecting data values from a valid range of data values. Multiple instruction streamers may be employed to simulate... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney LLP

20090164862 - Method, receiver and transmitter for improved hybrid automatic repeat request: The present invention relates to methods and a transmitter and a receiver for a mobile communication system. The basic idea of the present invention is to recursively derive from previous HARQ feedback the number of HARQ transmissions that is required to be able to decode the transmitted data successfully and... Agent: Ericsson Inc.

20090164864 - Inspection matrix generation method, encoding method, communication device, communication system, and encoder: A regular qc matrix is generated in which cyclic permutation matrices with specific regularity are arranged in row and column directions. A mask matrix supporting multiple encoding rates is generated for making the regular qc matrix into irregular. A specific cyclic permutation matrix in the regular qc matrix is converted... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090164863 - Method of encoding and decoding using low density parity check matrix: A method of encoding and decoding using an LDPC code is disclosed, by which encoding and decoding performance can be enhanced and which can be effectively applied to a communication system employing a variable data rate. In encoding or decoding an input data using a parity check matrix H, the... Agent: Lee, Hong, Degerman, Kang & Waimey

20090164865 - Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs: A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the... Agent: Scully, Scott, Murphy & Presser, P.C.

20090164866 - Interleaving method and communication apparatus: An interleaving method according to the present invention is an interleaving method implemented when interleaving is performed on an encoded sequence after being error-correction encoded in a communication device on a data transmission side. This method is implemented in such a manner that an inter-carrier interleaver (6) rearranges carrier numbers... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090164867 - High speed memory error detection and correction using interleaved (8,4) lbcs: Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor... Agent: Honeywell International Inc.

20090164868 - Method and apparatus for buffering an encoded signal for a turbo decoder: A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations,... Agent: Beceem Communications, Inc.

20090164869 - Memory architecture and configuration method thereof: A memory architecture and a configuration method thereof are provided. In the memory configuration method, a data to be stored in the memory and a corresponding error correction code (ECC) are first provided. When the data is written into the memory, the ECC is stored next to the corresponding data,... Agent: J C Patents, Inc.

20090164870 - Apparatus and method for error correction of data values in a storage device: A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects... Agent: Nixon & Vanderhye, PC

20090164871 - Semiconductor memory devices that are configured to analyze read failures and related methods of operating such devices: Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured... Agent: Myers Bigel Sibley & Sajovec

20090164872 - Prediction and prevention of uncorrectable memory errors: A method for predicting and preventing uncorrectable errors that may occur while accessing memory in a computer system. The method involves detecting two or more correctable errors from two or more different physical addresses on each of two or more different bit positions from the same DIMM within a specified... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney LLP

20090164873 - System and method for improving signaling channel robustness: A system and method for improving signaling channel robustness. Additional error correction is provided for (L1) dynamic signaling that is carried in P2 symbols in such way that high time diversity can be provided. In other embodiments, transmitted services are scheduled such that services will rotate or “move” between frames,... Agent: Foley & Lardner LLP

20090164874 - Collecting failure information on error correction code (ecc) protected data: Methods and means of error correction code (ECC) debugging may comprise detecting whether a bit error has occurred; determining which bit or bits were in error; and using the bit error information for debug. The method may further comprise comparing ECC syndromes against one or more ECC syndrome patterns. The... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090158079 - Fault information processing system and method for vehicle: The present invention relates to a fault information processing system and method for a vehicle, which can satisfy a short control cycle to thereby reduce the burden applied to the CPU and enables significant fault information (freeze frame) to be frozen. To this end, this invention features that the fault... Agent: Edwards Angell Palmer & Dodge LLP

20090158080 - Storage device and data backup method: A storage device includes: a storage unit for storing data; a memory for storing management information; a local storage unit for storing differential data; a controller for controlling the storage device in accordance with a process comprising the steps of: updating data; updating management information; transmitting differential data to the... Agent: Staas & Halsey LLP

20090158081 - Failover of blade servers in a data center: Failover of blade servers in a data center including powering off a failing blade server by a system management server through a blade server management module (‘BSMM’) managing the failing blade server, the failing blade server characterized by a machine type, one or more network addresses, and one or more... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20090158083 - Cluster system and method for operating the same: Provided are a cluster system, which makes general nodes appear as if they provide seamless services without failure when seen from the outside, and a method for operating the cluster system. The cluster system for operating individual nodes in a distributed management manner includes a board server having a task... Agent: Staas & Halsey LLP

20090158082 - Failover in a host concurrently supporting multiple virtual ip addresses across multiple adapters: A host enables any adapter of multiple adapters of the host to concurrently support any VIPA of the multiple VIPAs assigned to the host. Responsive to a failure of at least one particular adapter from among the multiple adapters, the host triggers the remaining, functioning adapters to broadcast a separate... Agent: Ibm Corp (ap) C/o Amy Pattillo

20090158084 - Redundant bit patterns for column defects coding: Techniques for coding and decoding redundant coding for column defects cartography. Defective cell groups identified in a memory array are redundantly encoded with a different bit pattern than the bit pattern used for functional cell groups. The identified defective cell groups are repaired using redundant cell groups in the memory... Agent: Fish & Richardson P.C.

20090158086 - Embedded system and method of recovering flash memory: The present invention provides an embedded system and method for recovering the file system of flash memory when damage has occurred to the file system of the flash memory. The embedded system is equipped with NOR flash memory. The embedded system includes boot Programmable Read-Only Memory (PROM) and a Central... Agent: Edwards Angell Palmer & Dodge LLP

20090158085 - Power safe translation table operation in flash memory: Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check... Agent: Amin, Turocy & Calvin, LLP

20090158087 - Semiconductor integrated circuit with memory repair circuit: A semiconductor integrated circuit which can perform repair of at least one memory circuit in RAM, etc. and can promote improvement in the degree of integration is provided. The encoding circuit 3 receives the failure bit data fail [0]-fail [7], encodes these eight-bit failure bit data fail [7:0], and outputs... Agent: Miles & Stockbridge PC

20090158088 - Self-correcting computer: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for... Agent: Maxwell Technologies, Inc.

20090158090 - Data entry retrieval: The present invention provides for the recovery of characters entered into at least one data entry zone of a data entry window. A method in accordance with an embodiment includes: storing a first image of the data entry window during data entry; subtracting a reference image from the first image... Agent: Hoffman Warnick LLC

20090158089 - Method for recognizing a power failure in a data memory and recovering the data memory: To detect a power failure in a volatile data memory containing useful data units and test data units associated with the useful data units, the associated test data unit is also read when the useful data unit is read-accessed, and a decision is made as to whether the useful data... Agent: Kenyon & Kenyon LLP

20090158091 - Intelligent job functionality: A method, apparatus, and program product utilize intelligent job functionality to diagnose an error in a computer. After detecting an error in a first job processing a task, and in response to another attempt to perform the task, a job selection algorithm selects a predetermined job in which to perform... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090158092 - System and method for indicating status of an on-chip power supply system: The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates... Agent: Cantor Colburn LLP-ibm Burlington

20090158093 - Motherboard tester: An exemplary motherboard tester includes a processor comprising a pair of data terminals for transmitting data; and an interface comprising: a pair of data terminals coupled to the data terminals of the processor respectively; at least one output terminal arranged for connecting to a corresponding pin of a chipset mounted... Agent: PCe Industry, Inc. Att. Steven Reiss

20090158094 - Method and system for protocol embedded automated test control: A method and system of an embodiment may include designing two or more test cases for a network, creating one or more test records comprising data and configuration data for the two or more test cases, provisioning a user record on the network, running a first test case using the... Agent: Verizon Patent Management Group

20090158095 - Method for testing a computer device and a computer system thereof: A method performed by a software module for testing a computer device. The method first selects the computer device from a device list, and links a driver of the computer device through a program interface, in which the program interface is provided by an operating system. Next, the method sets... Agent: Joe Mckinney Muncy

20090158096 - Spatial monitoring-correlation mechanism and method for locating an origin of a problem with an iptv network: A spatial monitoring-correlation mechanism and a method are described herein for determining an origin of a problem within an Internet Protocol Television (IPTV) network by using topology information about the IPTV network and at least one error notification (e.g., packet loss notification-retransmission request) that is generated by at least one... Agent: Law Office Of William J. Tucker

20090158097 - Wake on lan (wol) test system and method thereof: The invention presents a Wake On LAN (WOL) test system and method thereof, wherein the system is applied for a client/server structure with the ILO (Integrated Lights-Out) inside server platform. The system is composed of an examiner end, an examinee end and a network domain. And through the WOL test... Agent: Joe Mckinney Muncy

20090158098 - Method and apparatus for providing a reliable fault management for a network: A method and apparatus for providing reliable fault management for a network are disclosed. For example, a method receives one or more alarms from one or more network elements (NEs) by an element management system, and determines whether the one or more alarms need to be forwarded to a fault... Agent: At & T Legal Department - Wt

20090158099 - Method and apparatus for runtime error handling: A method and an apparatus for receiving an error notification associated with a runtime error of a software application to generate a plurality of context attributes from a runtime state of the software application associated with an instant of time of the runtime error are described. One or more potential... Agent: Vincent Wen Jeng Lue Blakely, Sokoloff, Taylor & Zafman LLP

20090158100 - Jitter applying circuit and test apparatus: There is provided a jitter applying circuit that includes: a signal transmission path that transmits a signal from an input end to an output end thereof; a jitter control section that outputs, from an output terminal thereof, a jitter control voltage that is in accordance with jitter to be superposed... Agent: Jianq Chyun Intellectual Property Office

20090158101 - Adapting word line pulse widths in memory systems: Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width;... Agent: Qualcomm Incorporated

20090158102 - Methods, devices, and systems for experiencing reduced unequal testing degradation: One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input paths which do not receive test signals. Therefore, rather than being held in a fixed state during the burn-in process, the remaining inputs are toggled... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090158103 - Test apparatus and test method: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data... Agent: Osha Liang L.L.P.

20090158104 - Method and apparatus for memory ac timing measurement: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of... Agent: J C Patents, Inc.

20090158105 - In system diagnostics through scan matrix: A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090158106 - Position independent testing of circuits: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided... Agent: Texas Instruments Incorporated

20090158107 - System-on-chip with master/slave debug interface: A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC... Agent: Dickstein Shapiro LLP

20090158108 - Error detection and recovery using an asynchronous transaction journal: Illustrative embodiments provide a computer implemented method, an apparatus, and a computer program product for error detection and recovery using an asynchronous transaction journal. In an illustrative embodiment the computer implemented method receives a request message from a requester, stores the request message in the asynchronous transaction journal and determines... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090158110 - Forward and reverse shifting selective harq combining scheme for ofdma systems: A method and apparatus for combining retransmitted hybrid automatic repeat-request (HARQ) messages at different stages in an OFDM/OFDMA receiver are provided. A combination of different types of HARQ combiners may be designed into the receiver and selected on a per-channel basis. Proper selection of a HARQ combining scheme may reduce... Agent: Qualcomm Incorporated

20090158109 - Selective harq combining scheme for ofdm/ofdma systems: A method and apparatus for combining retransmitted hybrid automatic repeat-request (HARQ) messages at different stages in an orthogonal frequency-division multiplexing (OFDM)/orthogonal frequency-division multiple access (OFDMA) receiver are provided. The type of HARQ combiner used for a particular channel may depend on a number of selection criteria including the modulation order... Agent: Qualcomm Incorporated

20090158111 - Self-timed error correcting code evaluation system and method: Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090158115 - Apparatus and method for decoding signal in a communication system: A method and apparatus for decoding a signal in a communication system. The method and apparatus includes receiving a punctured codeword including information bit nodes and unpunctured parity bit nodes; analyzing the unpunctured parity bit nodes, and detecting at least one first block including the unpunctured parity bit nodes among... Agent: Docket Clerk

20090158113 - Apparatus and method for encoding ldpc code using message passing algorithm: Provided is an apparatus and method for encoding a Low Density Parity Check (LDPC) code using a message passing algorithm. The apparatus, includes: a parity calculating unit for operating a check node value on an input bit and a predetermined parity bit according to the message passing algorithm and calculating... Agent: Cantor Colburn, LLP

20090158116 - Apparatus and method for generating low density parity check codes for sequential decoding algorithm: A method for generating a Low Density Parity Check (LDPC) code is provided. The method includes generating subsets each including a same number of check nodes, connecting each of variable nodes to the check nodes of the subsets so that the each of subsets is equal in degree or a... Agent: JeffersonIPLaw, LLP

20090158114 - Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number... Agent: Townsend And Townsend And Crew, LLP

20090158117 - Method and system for providing long and short block length low density parity check (ldpc) codes: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC... Agent: The Directv Group, Inc. Patent Docket Administration

20090158112 - Method for producing parity check matrix for low complexity and high speed decoding, and apparatus and method for coding low density parity check code using the same: Provided are a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same. The method includes: calculating a cyclic shift value of a subblock to a matrix; and when... Agent: Cantor Colburn, LLP

20090158118 - Configurable reed-solomon decoder based on modified forney syndromes: A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a... Agent: Christopher P Maiorana, PC Lsi Corporation

20090158120 - Hierarchical crc scheme: A hierarchical cyclic redundancy check (CRC) is provided that enables CRC appending and detection. A message that includes a first message portion and a second message portion is transmitted to two or more receivers. The receivers are not aware of the first message portion. One of the receivers can be... Agent: Qualcomm Incorporated

20090158119 - Parity error correction for band-limited digital signals: An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each of the... Agent: Kenyon & Kenyon LLP

20090158121 - Apparatus and method for decoding ldpc code based on prototype parity check matrixes: Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity... Agent: Cantor Colburn, LLP

20090158124 - Data storage apparatus and data storage method: In the ordinary operation mode, a data storage apparatus writes data into a first flash memory, while writing ECC data, which is used for correcting the data written in the first flash memory, into a second flash memory. When there is no remaining storage space in the first flash memory,... Agent: Beyer Law Group LLP

20090158123 - Error correction scheme for non-volatile memory: Error correcting systems, methods, and devices for non-volatile memory are disclosed. In one embodiment, a non-volatile memory device comprises a data area for storing data, an error correcting code generation section for generating an error correcting code in response to receipt of a code generation command, and an error correcting... Agent: Spansion LLC C/o Murabito , Hao & Barnes LLP

20090158122 - Forward error correction of an error acknowledgement command protocol: Embodiments of the invention are generally directed to systems, methods, and apparatuses for the forward error correction coding of an error acknowledgement command protocol. In some embodiments, a host sends commands to a memory device and monitors an error signal to determine whether the memory device received the commands without... Agent: Intel Corporation C/o Cpa Global

20090158125 - Recording/reproducing apparatus and recording/reproducing method: A recording/reproducing apparatus includes an encoding section, a decoding section, and a first judging section. The encoding section is configured to encode data that is to be recorded onto a recording medium into an LDPC (Low Density Parity Check) code. The decoding section is configured to decode the LDPC code... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090158126 - Efficient interference cancellation in analog memory cell arrays: A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or more first read thresholds. Third storage values that potentially cause cross-coupling interference in the second... Agent: D. Kligler I.p. Services Ltd

20090158127 - Decoding apparatus and decoding method: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on... Agent: Frommer Lawrence & Haug LLP

20090158128 - Decoding device, decoding method, receiving device, and storage medium reproducing device: A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of... Agent: Frommer Lawrence & Haug LLP

20090158129 - Method and apparatus for encoding and decoding channel in a communication system using low-density parity-check codes: A method for encoding a channel in a communication system using a Low-Density Parity-Check (LDPC) code. The method includes generating a plurality of column groups by grouping (categorizing) columns corresponding to an information word in a parity-check matrix of the LDPC code, and ordering the column groups; determining a range... Agent: Cha & Reiter, LLC

20090158130 - Method and apparatus for turbo encoding and decoding: A method and apparatus for turbo encoding and method and apparatus for turbo decoding are disclosed, by which encoding and decoding speeds of turbo codes and performance thereof can be enhanced. In performing turbo encoding on inputted information bits by a unit of an information frame including a predetermined number... Agent: Lee, Hong, Degerman, Kang & Waimey

20090158131 - Viterbi decoding apparatus and method: A Viterbi decoding apparatus receives a plurality of block data in time order, and transmits a block data group including the plurality of block data. Then, the Viterbi decoding apparatus applies a Viterbi decoding algorithm to the block data group and outputs some block data of the block data group.... Agent: Staas & Halsey LLP

20090158132 - Determining a message residue: In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number based on a bit... Agent: Intel Corporation C/o Cpa Global

20090150711 - Information processing device, program thereof, modular type system operation management system, and component selection method: An information processing device includes: storage means containing component information on the components constituting a system having a predetermined function; and processing means for calculating a combination of components necessary for constituting a system required for a service according to the component information, calculating risk information as information on the... Agent: Dickstein Shapiro LLP

20090150712 - Methods, systems, and computer program products for disaster recovery planning: Formulating an integrated disaster recovery (DR) plan based upon a plurality of DR requirements for an application by receiving a first set of inputs identifying one or more entity types for which the plan is to be formulated, such as an enterprise, one or more sites of the enterprise, the... Agent: Cantor Colburn, LLP - IBM Arc Division

20090150713 - Multi-voltage synchronous systems: Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane... Agent: Searete LLC Clarence T. Tegreene

20090150714 - Remote diagnostic and repair system: A system and method for remotely diagnosing and repairing a computer controlled asset comprises an access point connected to a computer controlled asset thereby allowing electronic access to the computer system of the computer controlled asset, a service center remotely connected to the access point for providing diagnostic review and... Agent: Michael A. O'neil, P.C.

20090150715 - Delivery of streams to repair errored media streams in periods of insufficient resources: In one embodiment, a method includes ingesting a program stream from a program source on a first channel. The method also includes storing the program stream, and receiving notification from a client of unrecoverable error in a stream received at the client. The unrecoverable error corresponds to at least a... Agent: Cisco Systems, Inc. Scientific-atlanta, Inc.

20090150719 - Automatically freezing functionality of a computing entity responsive to an error: Facilitating error handling of computing environments, including those environments having file systems. Responsive to an entity of the computing environment, such as a client of a file system, obtaining at least an indication of an error, a portion of functionality of the entity is automatically frozen. The obtaining is, for... Agent: Heslin Rothenberg Farley & Mesitti P.C.

20090150717 - Availability prediction method for high availability cluster: Provided is an availability prediction method for a high availability. The method includes calculating a basic survival probability that the other node survives until a failure on one node of two nodes constituting a cluster is fixed, and determining an optimal number of nodes meeting a preset reference availability probability... Agent: Staas & Halsey LLP

20090150718 - Large-scale cluster monitoring system, and method of automatically building/restoring the same: Provided are a large-scale cluster monitoring system and a method for automatically building/restoring the same, which can automatically build a large-scale monitoring system and can automatically build a monitoring environment when a failure occurs in nodes. The large-scale cluster monitoring system includes a CM server, a BD server, GM nodes,... Agent: Staas & Halsey LLP

20090150716 - Method for monitoring and managing a client device in a distributed autonomic computing environment: A stale of a managed client device in a distributed autonomic computing environment is attached to an event occurring on the managed client device. The event is sent, with the attached state of the managed client device, to a server. The state of the managed client device is saved at... Agent: Cantor Colburn LLP IBM Svl

20090150720 - Error detector in a cache memory using configurable way redundancy: A data processing system includes a processor having a multi-way cache which has a first and a second way. The second way is configurable to either be redundant to the first way or to operate as an associative way independent of the first way. The system may further include a... Agent: Freescale Semiconductor, Inc. Law Department

20090150721 - Utilizing a potentially unreliable memory module for memory mirroring in a computing system: Methods, apparatus, and products are disclosed for utilizing a potentially unreliable memory module for memory mirroring in a computing system, the computing system including at least two memory modules, that includes: retrieving error information from an error log stored in non-volatile memory, the error information describing an occurrence of a... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20090150722 - Recovering from errors in streaming dsp applications: A data processing system is provided in which processing circuitry performs at least one of a series of data processing operations in dependence upon a set of data values and control circuitry controls execution of the data processing operations. Control path error detection circuitry is provided for detecting a control... Agent: Nixon & Vanderhye P.C.

20090150723 - Computer chip set having on board wireless interfaces to support test operations: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized... Agent: Garlick Harrison & Markison

20090150725 - Method for debugging reconfigurable architectures: A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.... Agent: Kenyon & Kenyon LLP

20090150724 - Model driven diagnostics system and methods thereof: A method to perform a diagnostic test in an integrated support platform having a plurality of services is disclosed. The method includes a process of building at least one or more knowledge model for each of the plurality of services in the integrated support platform. The process of building the... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090150726 - Method and system for extending the useful life of another system: Disclosed are embodiments of a method and an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g.,... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090150727 - Data transmission method: An exemplary data transmission method is used in a data transmission system which has a data source, a data receiver, first, second, and third transmission lines connected between the data source and the data receiver. The data transmission method includes: the data source generating a checking code of a first... Agent: PCe Industry, Inc. Att. Steven Reiss

20090150728 - High speed serial trace protocol for device debug: Tracing of test information from a hardware device for debugging is formatted for transmission via a high-speed serial protocol. Data from various components in the hardware device is transmitted to an external test board using high speed serial ports. The number of serial ports needed for data transfer is significantly... Agent: Hensley Kim & Holzer, LLC

20090150729 - Method of testing memory array at operational speed using scan: A method and system for testing a chip at functional (operational) speed. The chip may include an integrated circuit having a number flops and memory arrays arranged into logically functioning elements. Additional flops may be included to output to one or more of the other flops in order to provide... Agent: Brooks Kushman P.C. / Sun / Stk

20090150730 - Test apparatus for data storage device and test method for data storage device: In a test apparatus for a data storage device, embodiments of the present invention help to support data storage devices with different specifications using a single processor. According to one embodiment, a test apparatus comprises a processor card and adapter cards. The adapter cards comprise power supply circuits to generate... Agent: Townsend And Townsend And Crew LLP

20090150731 - Test circuit capable of sequentially performing boundary scan test and test method thereof: A boundary scan test circuit is capable of sequentially performing a boundary scan test with respect to semiconductor integrated circuits bonded to both surfaces of a memory board. In order to reduce a boundary scan test time, the boundary scan test circuit includes a mirror function unit which transmits data... Agent: Baker & Mckenzie LLP Patent Department

20090150732 - Method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints: A method, system, and computer program product for integrated circuit recovery testing using simulation checkpoints is provided. The method includes executing an error injection test on an integrated circuit that includes a plurality of domains and latches. The error injection test includes injecting an error into one of the domains,... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090150733 - Test apparatus and calibration method: A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by... Agent: Jianq Chyun Intellectual Property Office

20090150734 - Tri-state i/o port: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of... Agent: Wpat, PC

20090150735 - Metadata brokering server and methods: Exemplary embodiments of the present invention provide methods and systems for supplying rich multimedia metadata usable to generate, e.g., sophisticated entertainment user interfaces in the home. These methods and systems can be implemented as a server-based software application that feeds multiple, diverse clients. The server functionality could be distributed, even... Agent: Potomac Patent Group PLLC

20090150737 - Acknowledgment packet: Various example embodiments are disclosed. According to an example embodiment, a receiving station in a wireless network may receive a plurality of Medium Access Control Packet Data Units (MPDUs) from a transmitting station. Each of the plurality of MPDUs may include a sequence number. The receiving station may also determine... Agent: Brake Hughes Bellermann LLP C/o Intellevate

20090150736 - Outer coding framework: The subject matter disclosed herein provides an outer coding framework for minimizing the error rate of packets, such as application data packets used to transmit digital video broadcast data as well as other forms of data. In one aspect, there is provided a method. The method may include determining, based... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090150738 - Data communication apparatus, data receiving apparatus, data transmitting apparatus, and retransmission control method: A data communication apparatus, a data receiving apparatus, a data transmitting apparatus and a retransmission control method wherein the transmission efficiency is improved. The data communication apparatus includes an error rate determining part (120) and an ACK/NACK generating part (122). The error rate determining part (120) determines the packet error... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090150739 - Method of supporting data retransmission in a mobile communication system: A method of supporting data retransmission in a mobile communication system is disclosed according to the present invention. A method of supporting a hybrid automatic repeat and request (HARQ) at a user equipment in a mobile communication system comprises transmitting a first packet to a network, receiving a reception status... Agent: Lee, Hong, Degerman, Kang & Waimey

20090150743 - Method and system for constructing and decoding rateless codes with partial information: A method for data transmission to a receiving host, the transmitted data being coded for forward error correction, includes providing a pre-defined set Xk of symbols, having k symbols, at the transmitting host. An individual subset Xnh of the pre-defined set Xk, comprising nh symbols, is provided at each receiving... Agent: Darby & Darby P.C.

20090150741 - Modulation symbol to outer codeword mapping: m

20090150742 - Packet error rate correlation minimization: The subject matter disclosed herein provides an outer coding framework for reducing the correlation between packet errors in a wireless network. In one aspect, there is provided a method. The method may include receiving a packet including information. The received packet may be encoded using a forward error correction code... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090150740 - Transmitting apparatus and transmitting method: A transmitting apparatus and a transmitting method wherein the systematic bit reception quality can be improved and the throughput performance can be improved. An IR parameter control part (101) controls, based on the number of retransmissions, the ratio of systematic bits to parity bits in mapping them to packets, and... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090150744 - Apparatus, system, and method for ensuring data validity in a data storage process: An apparatus, system, and method are disclosed for ensuring data validity in a data storage process. A data receiver module receives a storage block and existing parity information. An ECC generation module generates error correcting code (“ECC”) check bits for the data of the storage block in response to receiving... Agent: Kunzler & Mckenzie

20090150746 - Iterative decoder systems and methods: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used... Agent: Ropes & Gray LLP

20090150745 - Trapping set decoding for transmission frames: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any one of a group of possible trapping sets... Agent: Sawyer Law Group LLP

20090150747 - Correction of errors in a memory array: A computer system for correction of errors in a memory array includes an error correction algorithm and a memory. The error correction algorithm is capable of correcting errors up to a first bit error rate in a correctable group of memory cells having a standard size. The memory is operative... Agent: Mark M. Friedman

20090150748 - Data storage and replay apparatus: A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding... Agent: Docket Clerk

20090150749 - Digital data coding and recording apparatus, and method of using the same: A method of preparing data for a storage device includes writing unencoded main data to a memory buffer; reading the unencoded main data from the memory buffer; encoding the read main data; scrambling the encoded main data to provide address and parity information; writing the address and parity information, but... Agent: F. Chau & Associates, LLC

20090150750 - Method and apparatus for harq encoding with low memory requirement: An apparatus and method for hybrid automatic repeat request (HARQ) encoding comprising re-encoding a subpacket from a plurality of subpackets to obtain a codeword; maintaining a set of state variables for each of the plurality of subpackets; initializing the set of state variables at HARQ transmit start; updating the set... Agent: Qualcomm Incorporated

20090150751 - Memory system that uses an interleaving scheme and a method thereof: A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected... Agent: F. Chau & Associates, LLC

20090150752 - Outer coding framework for application packet error rate minimization: The subject matter disclosed herein provides an outer coding framework for minimizing the error rate of packets, such as application data packets used to transmit digital video broadcast data as well as other forms of data. In one aspect, there is provided a method. The method may include inserting a... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090150753 - Data fragmentation identification in a data table: The subject matter disclosed herein provides a mechanism for identifying packet boundaries in a data table, such as a Reed-Solomon table. The method may include receiving one or more packets for insertion into a table. A first indicator may be inserted into the table. The first indicator may be associated... Agent: Mintz, Levin, Cohn, Ferris, Glovsky And Popeo, P.c

20090150754 - High speed syndrome-based fec encoder and system using same: A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and... Agent: Ryan, Mason & Lewis, LLP

20090150755 - Optimum distance spectrum feedforward tail-biting convolutional codes: A method of generating a set of generator polynomials for use as a tail biting convolution code to operate on data transmitted over a channel comprises: (1) selecting valid combinations of generator polynomials to include in a pool of potential codes, each valid combination being a potential code; (2) determining... Agent: Nixon & Vanderhye, PC

20090150756 - Storage control device, and control method for storage control device: The storage control device of the present invention is able to perform input and output of data between blocks whose size is different with good efficiency. The size of extended logical blocks, which are units of data input and output within a storage control device, and the size of physical... Agent: Sughrue Mion, PLLC

20090144579 - Methods and apparatus for handling errors involving virtual machines: A virtual machine monitor (VMM) in a data processing system handles errors involving virtual machines (VMs) in the processing system. For instance, an error manager in the VMM may detect an uncorrectable error in involving a component associated with a first VM in the processing system. In response to detection... Agent: Michael R. Barre C/o Intellevate, LLC

20090144580 - Data transfer controlling method, content transfer controlling method, content processing information acquisition method and content transfer system: A method of controlling data transfer, a method of controlling content transfer, a method of obtaining content processing information, and a system for transferring content are provided. The method of controlling data transfer in a data interoperable environment includes: receiving a request for transmitting data from a client; gathering information... Agent: Fish & Richardson P.C.

20090144581 - Data transfer controlling method, content transfer controlling method, content processing information acquisition method and content transfer system: A method of controlling data transfer, a method of controlling content transfer, a method of obtaining content processing information, and a system for transferring content are provided. The method of controlling data transfer in a data interoperable environment includes: receiving a request for transmitting data from a client; gathering information... Agent: Fish & Richardson P.C.

20090144582 - Anti-virus method based on security chip: An anti-virus method based on a security chip according to the present invention is provided. The method comprises the following steps: a hash value obtained by a hashing operation for a computer key file and a system control program are stored in a memory of the security chip, and a... Agent: Dickstein Shapiro LLP

20090144583 - Memory circuit: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit... Agent: Coats & Bennett/qimonda

20090144584 - System and method for performance monitoring and repair of computers: A system and method for monitoring computer performance and repairing and/or optimizing system configurations. During these idle times, the present process executes a sequence of background system analyses that can trigger associated optimization, maintenance, or repair actions based on a comparison of current computer states and baseline optimal health data.... Agent: Reed Smith, LLP

20090144585 - Debugging method of the basic input/output system: A debugging method of the BIOS is disclosed. Firstly a debugging routine is written into a boot program. Then the BIOS executes the boot program. The BIOS judges whether a status value is equal to a default value of the debugging routine or not. When the status value is equal... Agent: Rosenberg, Klein & Lee

20090144586 - System and program products for facilitating access to status and measurement data associated with input/output processing: Input/output processing is facilitated by readily enabling access to information associated with input/output processing. This information includes status information and measurement data provided by a control unit executing input/output commands. The status and measurement data are provided in a status control block identified in a transport control word, which is... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20090144587 - Device and method for electronic controlling: An electronic controlling device and method is disclosed. One embodiment provides at least one module performing specific functions within one of a plurality of module modes on reception of a corresponding module mode request. A system control unit is provided to operate the at least module in one of a... Agent: Dicke, Billig & Czaja

20090144588 - Finite state machine error recovery: The use of a simple (e.g., magnitude comparator) circuit, and of a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions, and a magnitude comparator... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090144589 - Device and method for controlling an execution of a dma task: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive... Agent: Freescale Semiconductor, Inc. Law Department

20090144590 - Interleaving redundancy apparatus and method: One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving... Agent: Eschweiler & Associates LLC

20090144591 - Determining bit error rate using single data burst: A communication system comprises a transceiver capable of receiving a data burst as part of a paging block. The system also comprises processing logic capable of comparing at least part of the data burst to a plurality of permutations of the data burst to locate a matching permutation. The processing... Agent: Texas Instruments Incorporated

20090144592 - Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The... Agent: Wall & Tong, LLP/ Alcatel-lucent Usa Inc.

20090144593 - Method and apparatus for describing parallel access to a system-on-chip: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The... Agent: Wall & Tong, LLP/ Alcatel-lucent Usa Inc.

20090144595 - Built-in self-testing (bist) of field programmable object arrays: A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is... Agent: Stoel Rives LLP - Pdx

20090144594 - Method and apparatus for describing and testing a system-on-chip: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The... Agent: Wall & Tong, LLP/ Alcatel-lucent Usa Inc.

20090144596 - Decoder with resiliency to handle errors in a received data stream: A decoder provided according to an aspect of the present invention determines a type of each network abstraction layer (NAL) unit, and discards a NAL unit when the size of the NAL unit is inconsistent with the size according to the determined type. According to another aspect, a decoder corrects... Agent: Texas Instruments Incorporated

20090144597 - Encoding/decoding technique for rebroadcasting lost packets: When retransmitting lost packets of data to multiple devices in a wireless network, the original sequence of packets containing all the lost packets may be encoded into a smaller number of packets for the retransmission. These encoded packets may be collectively addressed to all the intended receiving devices through broadcast... Agent: John F. Travis Intel Corporation

20090144598 - Error correcting code predication system and method: In memory devices that degrade with use, a memory controller may monitor and record a usage history of portions of the memory. The memory controller can then vary a strength of error correction coding to protect information written to various portions of the memory having different usage histories. More specifically,... Agent: Oliff & Berridge, PLC

20090144599 - Method for evaluating the operating safety of a system: Evaluating the operating safety of a complex software and or hardware system such as a system for displaying flight information on an instrument panel of an aircraft. The evaluation method includes construction of a first architecture of the system, divided into several blocks each comprising data inputs/outputs, the inputs of... Agent: Darby & Darby P.C.

20090144600 - Efficient re-read operations from memory devices: Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values.... Agent: D. Kligler I.p. Services Ltd

20090144601 - Fec-based reliability control protocols: In a transport system, data is reliably transported from a sender to a receiver by organizing the data to be transported into data blocks, wherein each data block comprises a plurality of encoding units, transmitting encoding units of a first data block from the sender to the receiver, and detecting,... Agent: Townsend And Townsend And Crew, LLP

20090144602 - Method and system for encoding or decoding a sequence of digital data: A method is provided for encoding and decoding a sequence of digital data, according to which a portion of the sequence of digital data corresponds to a data block that includes several data packets, at least two data packets per data block containing an identifier. The position of the data... Agent: K&l Gates LLP

20090144603 - Assigning codes to and repairing huffman trees: A method for assigning codes to Huffman trees and repairing invalid Huffman trees is disclosed using a calculated delta and moving nodes within the Huffman tree by adjusting their encode register entries.... Agent: Lee & Hayes, PLLC

20090144604 - Convolutional encoding with partitioned parallel encoding operations: Convolutional encoding throughput is increased by partitioning input information bits into a plurality of blocks that are convolutionally encoded in parallel. A plurality of convolutional encoding operations which have respective initial encode states that are mutually different from one another are applied in parallel to one of the blocks to... Agent: Qualcomm Incorporated