Error detection/correction and fault detection/recovery inventions 03/09

20090083572 - Program control method for network devices and network system: Thus, among devices which operate in cooperation with one another by use of a communications protocol such as UPnP, even if there is a device having a device program that includes a bug, or even if there is a device that has a performance problem, the devices can operate in... Agent: Mcdermott Will & Emery LLP

20090083573 - Method for detecting sources of faults or defective measuring sensors by positive case modeling and partial suppression of equations: A method establishes a global system model equation including model equations, which contain parameters, of individual components that form the global system. According to said method, the parameters of the individual components are detected using sensor values from the sensors that are allocated to the individual components and it is... Agent: Staas & Halsey LLP

20090083574 - Method for operating a management system of function modules: Methods for operating a management system that manages a large number of first function modules and second function modules. An inhibitor module I sets first control statuses to designating blocking when associated events are detected by an event detecting device, and then the management system no longer makes associated first... Agent: Kenyon & Kenyon LLP

20090083575 - Replacing a failing physical processor: Replacing a failing physical processor in a computer supporting multiple logical partitions, where the logical partitions include dedicated partitions and shared processor partitions, the dedicated partitions are supported by virtual processors having assigned physical processors, and the shared processor partitions are supported by pools of virtual processors. The pools of... Agent: Ibm (roc-blf)

20090083576 - Fault tree map generation: A method for Fault Tree Map generation employs to transformation of Fault Trees of production installation, specific installation, technical system (Hardware and integrated Hardware/Software) to new Fault Tree diagram (Fault Tree Map), which permits drastically compact the Fault Tree depiction and facilitates performing of the Fault Tree qualitative analysis, including... Agent: Nixon & Vanderhye, PC

20090083577 - Scheduling and decision system: m

20090083578 - Method of testing server side objects: There is disclosed a method and system of testing server side objects in a client-server environment. A proxy is created of a first object on a server side on a client side. The proxy invokes a method of the first object on the server side to conduct a test by... Agent: Ibm Corporation

20090083579 - Method for cache correction using functional tests translated to fuse repair: A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect... Agent: Ibm Corporation (jvm)

20090083580 - Techniques for background testing a hard disk drive: A technique for background testing a hard disk drive, when an associated system is powered and the hard disk drive is available, includes receiving an interrupt test indication that indicates that the background testing of the hard disk drive is to be interrupted. The technique also includes discontinuing, at a... Agent: Dillon & Yudell LLP

20090083582 - Image forming apparatus and method of managing jobs thereof: An image forming apparatus and a job management method thereof are provided. The job management method includes detecting an occurrence of an error during a processing of a job, and upon detecting the occurrence of the error, providing information about one or more jobs related with the error from among... Agent: Stein, Mcewen & Bui, LLP

20090083581 - Methods and systems for managing response data in an information handling system: Methods for managing response data within an information handling system (IHS), where the method includes the step of obtaining response data from at least one component in the IHS, the response data generated in response to receiving a command. The method also includes accumulating the response data from the at... Agent: Andrea E. Tran Pramudji Wendt & Tran, LLP

20090083583 - Fault detection systems and methods for self-optimizing heating, ventilation, and air conditioning controls: A fault detection system for detecting a fault in a process system includes a first circuit configured to modify an input of the process system with a modifying signal. The fault detection system further includes a second circuit configured to receive an output from the process system and configured to... Agent: Foley & Lardner LLP

20090083584 - Method for maintaining track data integrity in magnetic disk storage devices: Techniques for detection of impending data errors in a mass storage system, such as a track squeeze problem in an electromagnetic disk drive, and then repairing the impending problem, such as by rewriting the affected tracks. In many cases the problem is detected and repair is effected when the original... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20090083585 - Method of pressure testing for peripheral component interconnect (pci) bus stage: A method of pressure testing for peripheral component interconnect (PCI) bus stage that is used in the overall pressure testing of PCI bus. The method includes the steps of reviewing all the PCI buses in a system; obtaining a tree-shaped structure of the all the PCI buses and PCI devices... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090083587 - Apparatus and method for selectively enabling and disabling a squelch circuit across ahci and sata power states: An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled... Agent: Pearl Cohen Zedek Latzer, LLP

20090083588 - Device remote monitor/recovery system: A system includes a support side host (PCh1) connected to a network (n1) and a monitored side system (u1) connected to the network (n1). The monitored side system (u1) is formed by monitored/support object devices (ud1, ud2) and an interface device (us4) connected between the devices and the network (n1)... Agent: Steptoe & Johnson LLP

20090083586 - Failure management device and method: A method and device for monitoring failures are disclosed herein. The monitoring device comprises an environmental event generator and a status-monitor. The environmental event generator generates an environmental trigger based on changes in an environmental factor, and the status-monitor monitors failure-status of plurality of elements in a system. The status-monitor... Agent: Peter Vogel Ge Healthcare

20090083589 - Systems, devices, and/or methods for managing communications: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial... Agent: Siemens Corporation Intellectual Property Department

20090083590 - System and method for determining the fault-tolerance of an erasure code: A method for determining a fault tolerance of an erasure code comprises deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns with one another to produce child erasure... Agent: Hewlett Packard Company

20090083591 - Method and apparatus for recording high-speed input data into a matrix of memory devices: For recording or replaying in real-time digital high bandwidth video signals, e.g. HDTV, HD progressive or HD film capture signals, very fast memories are required. For storage of streaming HD video data NAND FLASH memory based systems could be used. Flash memory devices are physically accessed in a page oriented... Agent: Robert D. Shedd Thomson Licensing LLC

20090083592 - Semicondcutor device, memory system and control method of the semiconductor device: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an... Agent: Arent Fox LLP

20090083593 - Test method and test program of semiconductor logic circuit device: The number of output switching scan flip-flops in a capture operation is decreased, which decreases the capture power consumption, so that the reduction of the power supply voltage can be decreased to decrease generation of an erroneous test. For this purpose, 0 or 1 is filled in unspecified bits within... Agent: Mcginn Intellectual Property Law Group, PLLC

20090083594 - Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device: Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090083596 - Method and apparatus for synthesis of augmented multimode compactors: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090083597 - Method and apparatus for synthesis of augmented multimode compactors: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20090083595 - Scan test circuit: When a dynamic fault test is to be performed on a plurality of divisional circuits, in order to perform the dynamic fault test also on a circuit in which the divisional circuits are combined, and to increase a fault detection rate of dynamic fault, a scan test circuit for a... Agent: Mcginn Intellectual Property Law Group, PLLC

20090083598 - Method for monitoring and adjusting circuit performance: A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency,... Agent: Mhkkg/sun

20090083599 - Hierarchical test response compaction for a plurality of logic blocks: In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices... Agent: Trop, Pruner & Hu, P.C.

20090083600 - Systems and methods for critical node filtering of integrated circuits: Systems, apparatuses, methods, and computer program products for performing silicon debugging and isolating faults in integrated circuits are disclosed. Some embodiments comprise a simulator to simulate operation of one or more portions of a circuit in order to identify elements of the circuit which are related to a fault, a... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20090083601 - Data transmission with harq and interference mitigation: Techniques for transmitting data with hybrid automatic retransmission (HARQ) and interference mitigation are described. In one design, a transmitter processes a packet of data in accordance with a rate and sends at least one transmission of the packet to a receiver with HARQ. In one design, the transmitter sends a... Agent: Qualcomm Incorporated

20090083602 - Operation of a forward link acknowledgement channel for the reverse link data: An acknowledgement method in a wireless communication system. Initially, a reverse supplemental channel (R-SCH) frame is received at a base station. The base station then transmits an acknowledgement (ACK) signal if quality of the received R-SCH frame is indicated as being good. A negative acknowledgement (NAK) signal is transmitted only... Agent: Qualcomm Incorporated

20090083603 - Radio resource control-service data unit reception: A method for receiving periodic transmissions of a segmented communication is disclosed. The segmented communication is received and each segment of the segmented communication is examined to determine if the segment is valid. Valid segments are stored, while invalid segments are discarded. Next, it is computed when the invalid segments... Agent: Volpe And Koenig, P.C. Dept. Icc

20090083604 - Ldpc encoders, decoders, systems and methods: An LDPC encoder with a complexity that increases linearly as a function of block size is provided. They arc implementable with simple logic consisting of a repeater with an irregular repeat pattern, an interleaver, and an accumulator that performs irregular accumulations.... Agent: Smart & Biggar P.o. Box 2999, Station D

20090083605 - Radio communication apparatus: A radio communication apparatus of the present invention aims at improving an error rate characteristic in the end receiver. A repeater (radio relay device) RS2 receives a signal transmitted from a repeater RS1 at a point of time of signal transmission from the repeater RS1, and detects whether or not... Agent: Pearne & Gordon LLP

20090083606 - Digital broadcasting system and data processing method: A receiving system and data processing method therein are disclosed, by which mobile service data is received and processed. The present invention includes a demodulator receiving a broadcast signal including mobile service data and main service data, the demodulator converting the received broadcast signal to a baseband signal, the mobile... Agent: Lee, Hong, Degerman, Kang & Waimey

20090083608 - Architecture and control of reed-solomon error-correction decoding: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information... Agent: Ropes & Gray LLP

20090083607 - Coding pattern comprising reed-solomon codewords encoded by mixed multi-pulse position modulation: A substrate having a coding pattern disposed on a surface thereof. The coding pattern comprises a plurality of macrodots encoding Reed-Solomon codewords. Each codeword is comprised of Reed-Solomon data symbols and Reed-Solomon redundancy symbols. The coding pattern encodes the symbols using mixed multi-pulse position modulation, with a higher number of... Agent: Silverbrook Research Pty Ltd

20090083609 - Efficient low complexity high throughput ldpc decoding method and optimization: A decoder and method for iteratively decoding of low-density parity check codes (LDPC) includes, in a code graph, performing check node decoding by determining messages from check nodes to variable nodes. In the code graph, variable node decoding is performed by determining messages from the variable nodes to the check... Agent: Nec Laboratories America, Inc.

20090083611 - Apparatus for blind checksum and correction for network transmissions: Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind... Agent: Ibm Rp-rps Sawyer Law Group LLP

20090083610 - Storage sub-system and method for controlling the same: A control means for the disk array apparatus that adds a data guarantee code to each logical data block and checks the data guarantee code when reading data has a de-duplication performing function and control means for: generating LA substitution information for a function checking the data guarantee code or... Agent: Stanley P. Fisher Reed Smith LLP

20090077412 - Administering a system dump on a redundant node controller in a computer system: Administering a system dump on a redundant node controller including detecting a communications failure between a system controller and the redundant node controller; generating a unique identifier for the communications failure; instructing a primary node controller to provoke a system dump on the redundant node controller; provoking the system dump... Agent: International Corp (blf)

20090077414 - Apparatus and program storage device for providing triad copy of storage data: An apparatus and program storage device for maintaining data is provided that includes receiving primary data at a first node, receiving mirrored data from a second and third node at the first node, and mirroring data received at the first node to a second and third node.... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090077413 - Apparatus, system, and method for server failover to standby server during broadcast storm or denial-of-service attack: An apparatus, system, and method are disclosed to failover to a standby server when a primary server is under broadcast storm or denial-of-service (“DoS”) attack. A primary attack sensing module is included to monitor a rate of incoming data from a computer network to a primary server and to determine... Agent: Kunzler & Associates

20090077415 - Control flow protection mechanism: A method is provided of protecting a program executing on a device at least to some extent from execution flow errors caused by physical disturbances, such as device failures and voltage spikes, that cause program execution to jump to an unexpected memory location. The executing program follows an execution path... Agent: Birch Stewart Kolasch & Birch

20090077416 - Method for managing a data storage system: A RAID storage system is provided with a plurality of disk drive modules in communication with a processor through a RAID controller. Tools and processes are provided for managing failure of individual modules in the RAID, identifying and managing excess spare modules, and migrating modules among array sites to produce... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20090077417 - Method, data processing apparatus and wireless device: Embodiments of the invention relate generally to a method, to a data processing apparatus and to a wireless device. In an embodiment of the invention a data processing apparatus is provided. The data processing apparatus may include a chip-integrated unit to select a check location of an external memory and... Agent: Infineon Technologies Ag Patent Department

20090077418 - Control of sparing in storage systems: Embodiments include methods, apparatus, and systems for controlling of sparing in a storage system. In one embodiment, a method compares a first amount of time to complete sparing of data from a failed disk in a storage system with a second amount of time to complete a user request to... Agent: Hewlett Packard Company

20090077419 - Monitoring system with trusted corrective actions: A system and computer program product for monitoring a data processing system is proposed. The system and computer program product involve the measuring of state parameters of the system. Indicators of the performance of the system are then inferred from the state parameters by applying fuzzy-logic rules. The proposed solution... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090077420 - Multiprocessor core dump retrieval: In particular embodiments, a monitoring processor may receive an interrupt from status monitoring logic associated with a monitored processor that has experienced an error. Interrupt logic at the monitoring processor may interrupt the monitored processor to initiate a standby mode of operation in the monitored processor. Core dump logic at... Agent: Schwegman, Lundberg & Woessner, P.A.

20090077421 - Load test method and load test apparatus: A load test method for a computer and apparatus are provided. The method includes acquiring control information indicating a type of a hardware resources required for executing a load test program and quantitative conditions determined for each type of the hardware resources, acquiring an assignment rule table specifying a set... Agent: Staas & Halsey LLP

20090077422 - Method and system for accelerating test automation of software applications: Disclosed is a method and system for capturing a user action on a user interface and fetching user interface elements in the user interface into a first list and operations of the user interface elements into a second list. A test case for the user action is created in an... Agent: Sap Ag

20090077423 - Memory device and system with bootloading operation: Provided are a semiconductor memory device, memory system and method of executing a bootloading operation. The method includes cyclically executing a bootloading operation cycle that includes loading the boot information from the memory to the controller, and performing an ECC operation on the boot information. The ECC operation provides a... Agent: Volentine & Whitt PLLC

20090077424 - Health check framework for enterprise systems: A health check framework for enterprise systems is described herein. In one embodiment, a health check framework includes one or more first layer methods as public interfaces to allow an application client to initiate one or more stages of a health checking session, where the first layer methods are independent... Agent: Sap/bstz Blakely Sokoloff Taylor & Zafman LLP

20090077425 - Method and apparatus for detection of data errors in tag arrays: A method for detecting errors in a tag array includes accessing the tag array with an index, retrieving at least one tag from the tag array, and computing a parity bit based on the expected tag.... Agent: F. Chau & Associates, LLC

20090077426 - Method and system for identifying communication errors resulting from reset skew: An electronic system includes a counter and a first component. The first component includes a reset input configured to receive a reset event, an interface to a communications interface coupleable to a second component, an error detection module configured to initiate the counter in response to detecting an error in... Agent: Larson Newman Abel & Polansky, LLP

20090077427 - Method and apparatus for evaluating effectiveness of test case: Provided are a method and apparatus for evaluating the effectiveness of a test case used for a program test on the basis of error detection capability. The method includes: receiving a target program used for evaluating the effectiveness of the test case; generating an error program by inputting errors to... Agent: Staas & Halsey LLP

20090077428 - Software method and system for controlling and observing computer networking devices: Mechanisms for managing the keyboard, video or mouse commands at a target device, which may be a computer or non-computer. During a boot up cycle, the present subject matter uses the intelligent platform management interface and a BIOS management application to receive keyboard or video signals from the BIOS, convert... Agent: Woodcock Washburn LLP

20090077429 - Memory system and wear-leveling method thereof: Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on... Agent: Harness, Dickey & Pierce, P.L.C

20090077431 - Devices and methods for bit-level coding and decoding of turbo codes: A bit-level turbo code encoder is provided. The bit-level turbo code encoder is configured to receive a first input data sequence and generate a first output data sequence. The bit-level turbo code encoder includes a first non-binary convolutional code encoder, a bit-level interleaver, and a second non-binary convolutional code encoder.... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20090077430 - Hybrid automatic repeat request apparatus and method for allocating packet-based fixed resources in a wireless mobile communication system: An apparatus and method for preventing errors in an HARQ operation and improving HARQ performance are provided. In the apparatus and method, upon receipt of HARQ feedback information, an information interpreter interprets the HARQ feedback information and determines whether the HARQ feedback information includes an error. If the HARQ feedback... Agent: JeffersonIPLaw, LLP

20090077433 - Self-healing link sequence counts within a circular buffer: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20090077432 - Semiconductor memory device: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit... Agent: Arent Fox LLP

20090077434 - Status of overall health of nonvolatile memory: A nonvolatile memory system includes nonvolatile memory organized into blocks, one or more of which are designated as spare blocks and one or more of which may be defective at the time of manufacturing of the nonvolatile memory. A controller device is coupled to the nonvolatile memory for measuring the... Agent: Leffert Jay & Polglaze, P.A.

20090077436 - Method for recording memory parameter and method for optimizing memory: The invention relates to a method for recording a memory parameter and a method for optimizing a memory. In the invention, adjusted enhancement parameter data can be stored in a non-volatile memory of a memory module. Then, the setting value of a parameter of a memory module is portable, and... Agent: Jianq Chyun Intellectual Property Office

20090077435 - Testing device, testing method, computer program product, and recording medium: There is provided a test apparatus for testing a memory under test that is addressable by the number of pulses of an address signal supplied thereto. The test apparatus includes a pattern generating section that generates writing data to be written into the memory under test, a first address generating... Agent: Jianq Chyun Intellectual Property Office

20090077437 - Method and system for routing scan chains in an array of processor resources: The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a... Agent: Lester H. Birnbaum

20090077438 - Circuit interconnect testing arrangement and approach therefor: Logic level crossings in an integrated circuit are detected. According to an example embodiment, a reset signal is provided to a flip-flop (314) as a function of a logic level of an integrated circuit. A logic level crossing condition of the integrated circuit is indicated as a function of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090077439 - Integrated circuit test method and test apparatus: A method (200) for locating a fault in an integrated circuit (100) having a plurality of digital outputs coupled to compaction logic (140) in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090077440 - Apparatus and method for verifying target cicuit: A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with... Agent: Mcginn Intellectual Property Law Group, PLLC

20090077441 - Method and apparatus for scheduling test vectors in a multiple core integrated circuit: A computer implemented method, apparatus and computer program product for extending test coverage in a simulated multiple core integrated circuit. The simulator applies at a first time a first test vector on the simulated multiple core integrated circuit, the first test vector having a duration. The simulator may also apply... Agent: Ibm Corp. (rcr) C/o Rolnik & Associates, P.C.

20090077442 - Shift register, data line driving circuit, scanning line driving circuit, electro-optical device, and electronic apparatus: To reduce a circuit area of a data line driving circuit. The data line driving circuit includes a plurality of circuit blocks. A circuit block has shift register unit circuits, logical operation unit circuits and a control unit circuit. The control unit circuit specifies the operation period of the corresponding... Agent: Oliff & Berridge, PLC

20090077443 - Storing parity information for data recovery: Provided are a system, and article of manufacture in which data is received at the first storage unit. A first information unit, a second information unit, and a third information unit are generated, wherein the first information unit, the second information unit, and the third information unit each include a... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090077444 - Method and apparatus for providing acknowledgement signaling to support an error control mechanism: An approach is provided for acknowledgement signaling. A determination is made whether an error control mechanism is enabled for transmission of a data frame. The data frame is fragmented into a plurality of coding blocks. A frame check sequence is appended to one or more sequences of the coding blocks,... Agent: Ditthavong Mori & Steiner, P.C.

20090077445 - Nonvolatile storage device, controller of nonvolatile memory, and nonvolatile storage system: A nonvolatile storage device includes a nonvolatile memory for storing data such as a flash memory, and a controller for controlling writing or reading of data to or from the nonvolatile memory. The nonvolatile memory stores control information (control program, control parameter) specifying a method of controlling writing or reading... Agent: Greenblum & Bernstein, P.L.C

20090077446 - Signal segmentation method and crc attachment method for reducing undetected error: The present invention provides for applying a cyclic redundancy check (CRC) to a data signal. The present invention includes attaching a first CRC to a first data signal block having a first length, segmenting the first data signal block attached with the first CRC into a plurality of second data... Agent: Lee, Hong, Degerman, Kang & Waimey

20090077447 - Multi-layer cyclic redundancy check code in wireless communication system: A wireless communication device (200) including a first CRC coder that generates a first block of CRC parity bits on a transport block and associates the first block of CRC parity bits with the transport block, a segmenting entity that segments the transport blocks into multiple code blocks after associating,... Agent: Motorola Inc

20090077448 - Forward error correction codec: A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting codes. The invention encodes a stream of data employing a plurality of serially concatenated, binary Bose-Ray-Chaudhuri-Hochquenghem (BCH) error correcting... Agent: Avalon Microelectronics, Inc. Attn: Intellectual Property

20090077449 - Methods and apparatus for encoding and decoding cyclic codes by processing multiple symbols per cycle: Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for each cycle and/or the configurability of... Agent: Joseph Schweiray Lee

20090077450 - Code combining soft handoff in wireless communication system: The present invention relates to a method for transmitting a signal in a wireless communication system. The method includes channel coding a data stream using a first turbo encoded puncture pattern, and channel coding the data stream using a second turbo encoded puncture pattern. Preferably, the first turbo encoded puncture... Agent: Lee, Hong, Degerman, Kang & Waimey

20090077451 - Method and apparatus for implementing decode operations in a data processor: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of... Agent: Ropes & Gray LLP

20090077452 - Method of generating error detection codes: A method for generating error detection code is disclosed. Firstly, a first error detection code PEDC is derived by using 12-byte unknown sector data information including ID, IED, RSV and the 2048-byte main data while the main data is delivered from a host. Secondly, a second error detection code MEDC... Agent: Perkins Coie LLP Patent-sea

20090077453 - Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code h-matrix: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to... Agent: Hogan & Hartson LLP

20090077457 - Iterative decoding of blocks with cyclic redundancy checks: The iterative decoding of blocks may be continued or terminated based on CRC checks. In an example embodiment, one iteration of an iterative decoding process is performed on a block whose information bits are covered by a CRC. The iterative decoding process is stopped if the CRC checks for a... Agent: Ericsson Inc.

20090077454 - Method and apparatus for mitigating memory requirements of erasure decoding processing: A system and method corrects erroneous sections received in a memory by pre-filling at least a portion of memory with a pre-defined value. If a received data packet is valid, the valid received data packet is stored over the pre-defined values in the memory location associated with the valid data... Agent: Akin Gump LLP - Silicon Valley

20090077456 - Methods and apparatus to generate multiple crcs: Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a selected cyclic redundancy check generator polynomial, at least one cyclic redundancy check is calculated based upon a... Agent: Robert E. Bushnell & Law Firm

20090077455 - Transmission system: A frame format used to send a command in which high-reliability transmission is demanded includes an SFD area, an inverted header area, a normal data area, a normal check area, an inverted header area, an inverted data area, and an inverted check area. Command data and data obtained by inverting... Agent: Foley And Lardner LLP Suite 500

20090070620 - Method and system for detecting and recovering failure command: A method and a system for detecting and recovering a failure command are provided. The method is used in a native command queuing (NCQ) and at least includes the following steps. In step (a), several commands are executed on a disk simultaneously according to the NCQ. In step (b), whether... Agent: Rabin & Berdo, PC

20090070621 - Broadcast receiving device: A broadcast receiving device includes a card slot, a fan, a temperature sensor, a memory component and a control unit. The card slot accepts an IC card. The fan rotates to cool the IC card. The temperature sensor measures a first temperature. The memory component stores correlation information indicating a... Agent: GlobalIPCounselors, LLP

20090070622 - Multi nodal computer system and method for handling check stops in the multi nodal computer system: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate... Agent: International Business Machines Corporation

20090070623 - Fail-over cluster with load-balancing capability: A solution for distributing the workload across the servers (105) in a fail-over cluster (for example, based on the MSCS) is proposed. A fail-over cluster is aimed at providing high availability; for this purpose, a resource service (205) automatically moves each resource (220) that exhibits some sort of failure to... Agent: Ibm Corp. (gig)

20090070624 - Test apparatus, test method, analyzing apparatus and computer readable medium: There is provided a test apparatus including a plurality of test signal feeding sections that are provided in a one-to-one correspondence with the plurality of memories under test, where each of the plurality of test signal feeding sections feeds a test signal designed to test a corresponding one of the... Agent: Jianq Chyun Intellectual Property Office

20090070625 - Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield: A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the... Agent: Mcandrews Held & Malloy, Ltd

20090070626 - Methods and systems for operating system bare-metal recovery: A system and method of recovering a system on replacement hardware includes booting the replacement hardware from an operating system disk. A recovery media is coupled to the replacement hardware to provide access to system information for restoring programming to replacement hardware. A specific file is provided on the recovery... Agent: Schwegman, Lundberg & Woessner, P.A.

20090070627 - System and article of manufacture for transparent file restore: Provided is a system and program for automatically handling an error when retrieving a file for an application. An error is detected while the application retrieves a file from the storage device. A user defined policy is checked to determine whether a backup copy should be restored, and the file... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090070628 - Hybrid event prediction and system control: A system for predicting an occurrence of a critical even in a computer cluster includes: a control system that includes an event log, a system parameter log, a memory for storing information related to occurrences of critical events, and a processor. The processor implements a hybrid prediction system; loads the... Agent: Michael Buchenhorner, P.A.

20090070629 - System and method for testing multiple processor modes for processor design verification and validation: A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090070630 - System and method of identifying and storing memory error locations: A system and method of identifying and storing memory error locations is disclosed. In one form, a method of using a memory is disclosed. The method can include detecting a memory error during execution of a run time environment within an information handling system, and determining if the memory error... Agent: Larson Newman Abel & Polansky, LLP

20090070631 - System and method for re-shuffling test case instruction orders for processor design verification and validation: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090070632 - System and method for testing slb and tlb cells during processor design verification and validation: A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090070633 - Test results management: Systems and methods of providing test result management are disclosed herein. A first configuring command to trace a test event data stream can be received. The test event data stream comprises test messages produced from execution of a test application. A second configuring command to trace a debug event data... Agent: Microsoft Corporation

20090070634 - System and method for automated customizable error diagnostics: A system and method of automated customizable error diagnostics is provided for use with industrial apparatus, such as semiconductor manufacturing apparatus. An external device, such as a robot, is provided with its own low level controller and a high level controller is provided to send instructions to the low level... Agent: Knobbe Martens Olson & Bear LLP

20090070635 - Method of improving the integrity and safety of an avionics system: The present invention relates to a method of improving the integrity and safety of a system, this method making it possible, on the one hand, to detect and to locate an anomaly of a system, and on the other hand to estimate the impact of such an anomaly on the... Agent: Lowe Hauptman & Berner, LLP

20090070636 - Advanced import/export panel notifications using a presentation application: A presentation application is provided that displays import notifications when a slide show presentation is opened by a user and displays export notifications when a slide show presentation is exported by the user. When the user directs the presentation application to open a slide show presentation, the presentation application may... Agent: Apple Inc. C/o Fletcher Yoder, PC

20090070637 - Electronic circuit with a memory matrix that stores pages including extra data: An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090070639 - Administering correlated error logs in a computer system: Administering correlated error logs in a computer system having a system controller and one or more redundant node controllers including providing by the system controller to a redundant node controller a unique identifier for error logs; detecting by the system controller a communications failure between the system controller and the... Agent: International Corp (blf)

20090070638 - Method and system for exception detecting and alerting: Methods and system for exception detecting and alerting are described. An exception indicating an occurrence of an error in an application and a path to the exception in an application space may be received. The received exception may be compared to a stored exception in a prior version of an... Agent: Schwegman, Lundberg & Woessner/ebay

20090070640 - Network fault manager for maintaining alarm conditions: A computer-implemented method for detecting alarm conditions, the method involving receiving at a first time a trigger notification describing a monitored occurrence on a network; setting a redundancy window to begin at the first time and to end at an expiration time; designating a first alarm condition to represent the... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20090070641 - Method of using link adaptation and power control for streaming services in wireless networks: A method for improving the performance for a streaming service by link-adaptation and power-control in a wireless packet network such as an Enhanced General Packet Radio Services (EGPRS) cellular network is described. In particular, the effects of a combined link adaptation and power control scheme (referred to as an error-based... Agent: At&t Corp.

20090070642 - System and method of dynamically mapping out faulty memory areas: An information handling system is disclosed and can include a processor and a memory coupled to the processor. Further, the system can include a system reserved area that is accessible to the processor. The system reserved area can include a physical memory fault table having a plurality of bits and... Agent: Larson Newman Abel & Polansky, LLP

20090070643 - System and method for testing a large memory area during processor design verification and validation: A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20090070644 - Method and apparatus for dynamically determining tester recipes: A method includes retrieving a group test parameter determined based on test results associated with a plurality of integrated circuit devices. A particular integrated circuit device is tested using a test program and the group test parameter.... Agent: Williams, Morgan & Amerson

20090070645 - Integrated circuit testing method and related circuit thereof: An integrated circuit testing method includes: respectively connecting a plurality of pads in a chip to generate a plurality of scan chains, wherein each scan chain connects two pads and at least one flip-flop in the chip; providing at least a selecting unit, wherein the selecting unit determines a mode... Agent: North America Intellectual Property Corporation

20090070646 - Multiple-capture dft system for scan-based integrated circuits: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The... Agent: Bacon & Thomas, PLLC

20090070648 - Efficient scheduling of background scrub commands: A method and apparatus to efficiently scrub a memory, during a scrub period, of a computer system that has a memory comprising a number of memory elements. Examples of memory elements are memory ranks and banks. A memory rank may further comprise one or more banks. The computer system has... Agent: Robert R. Williams IBM Corporation, Dept. 917

20090070647 - Scheduling of background scrub commands to reduce high workload memory request latency: A method and apparatus to scrub a memory during a scrub period, of a computer system. The computer system has a memory controller that receives read requests and write requests from a processor. The memory controller provides a different priority for scrub requests versus read requests during a period of... Agent: Robert R. Williams IBM Corporation, Dept. 917

20090070650 - Error correction for a persistent resource allocation: Methods and apparatus for communicating and utilizing persistent allocation of resources are described herein. A base station can allocate persistent resources to a client station, and can associate the client station or persistent resource allocation with a particular shared NACK channel. The base station can monitor the NACK channel for... Agent: Townsend And Townsend And Crew, LLP

20090070649 - Method and system for a transmitting antenna selection failure recovery mode: Aspects of a method and system for a transmitting antenna selection failure recover mode are presented. Aspects of the system may include a transmitting mobile terminal that enables selection of a sequence of protocol data units (PDU), for example a sequence of sounding frames, which may be transmitted during an... Agent: Mcandrews Held & Malloy, Ltd

20090070652 - Apparatus and method for channel encoding/decoding in communication system using variable-length ldpc codes: A method and apparatus for generating Low-Density Parity Check (LDPC) codes of various block lengths from a structured LDPC code in a communication system is provided. To support various block lengths, predefined rules are applied to a parity check matrix of an LDPC code, and then shortening is selectively applied... Agent: JeffersonIPLaw, LLP

20090070651 - Storage subsystem capable of adjusting ecc settings based on monitored conditions: A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system. To enable... Agent: Knobbe Martens Olson & Bear LLP

20090070654 - Design structure for a processor system with background error handling feature: A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor system that integrates error correcting code (ECC) detection and correction hardware within an memory management circuit. The design structure... Agent: Mark P. Kahler

20090070653 - Method of transmitting data: A method of transmitting data in a wireless access system is disclosed. The method includes various processes of obtaining the number of code blocks in consideration of an error detection code which is to be attached to each code block, calculating the size of the code blocks, segmenting input data,... Agent: Lee, Hong, Degerman, Kang & Waimey

20090070656 - Memory system with error correction decoder architecture having reduced latency and increased throughput: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second... Agent: Volentine & Whitt PLLC

20090070655 - Method for generating an ecc code for a memory device: A method for generating an ECC for a flash memory device is provided. The flash memory device only supports flash memories with low-level ECC technology, such as SLC (single-level cell) flash memories. By using a controller with an ECC engine, the flash memory device can directly generate a correct ECC... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20090070657 - Method of error correction in mbc flash memory: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical... Agent: Mark M. Friedman

20090070658 - Defect sensing viterbi based detector: During decoding using a Viterbi based detector, erasures are detected when surviving paths do not merge in an associated decoding window.... Agent: Cesari And Mckenna, LLP

20090070659 - Ldpc decoder with an improved llr update method using a set of relative values free from a shifting action: In a decoder having an improved LLR (log-likelihood-ratio) update method is provided. The method comprising the steps of: providing a parity check matrix; and using merely a set of parameters on a row of the parity check matrix instead of data of the whole non-zero elements of the parity check... Agent: Frank F. Tian

20090063891 - System and method for providing reliability of communication between supernodes of a multi-tiered full-graph interconnect architecture: A method, computer program product, and system are provided for providing reliability of communication. A first processor determines a current state of links coupled to ports of a first processor of the data processing system. Each port of the first processor comprises a plurality of links to a corresponding port... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090063892 - Propogation by a controller of reservation made by a host for remote storage: Provided are a method, system, and article of manufacture wherein a primary controller receives a request from a primary host to set reservations on a primary storage and a secondary storage, wherein the primary host, the primary controller and the primary storage are at a first site, and wherein a... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20090063893 - Redundant application network appliances using a low latency lossless interconnect link: Redundant application network appliances using a low latency lossless interconnect link are described herein. According to one embodiment, in response to receiving at a first network element a packet of a network transaction from a client over a first network for accessing a server of a datacenter, a layer 2... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090063894 - Autonomic pci express hardware detection and failover mechanism: A system with an autonomic PCI Express hardware detection and failover mechanism includes a plurality of combination root complex capable and endpoint capable devices. A combination root complex capable and endpoint capable device may be selectively configured to operate in either a root complex mode or an endpoint mode. One... Agent: Ibm Corporation

20090063895 - Scaleable and maintainable solid state drive: Methods and apparatus for maintaining a solid state disk drive facilitate expansion of storage capacity and maintenance of internal memory storage media, for example, are disclosed. Memory modules are adapted for removable installation in a solid state drive allowing for expansion of drive storage capacity and servicing of failed or... Agent: Leffert Jay & Polglaze, P.A.

20090063896 - System and method for providing dram device-level repair via address remappings external to the device: A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090063897 - Method of increasing system availability by assigning process pairs to processor pairs: A method is provided of assigning processors in a multiprocessor environment to a plurality of processes that are executed in the multiprocessor environment. Each process has a process pair defined by a primary process that executes on a first processor, and a backup process that executes on a second processor.... Agent: Panitch Schwarze Belisario & Nadel LLP

20090063898 - Processor instruction retry recovery: Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system,... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090063899 - Register error correction of speculative data in an out-of-order processor: In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file... Agent: Mhkkg/sun

20090063900 - Log collecting system, computer apparatus and log collecting program: A log collecting system includes a computer apparatus and at least one peripheral apparatus connected to the computer apparatus, the computer apparatus collecting a log that records operation of the at least one peripheral apparatus. The peripheral apparatus includes, a first log memory controlling section that stores a first log... Agent: Scully Scott Murphy & Presser, PC

20090063901 - Storage system that finds occurrence of power source failure: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which... Agent: Stanley P. Fisher Reed Smith LLP

20090063902 - Preliminary classification of events to facilitate cause-based analysis: The present invention provides methods and systems for performing preliminary cause-based classification of events in a computer or networked computer system. Methods are provided in which, based on an event message, cause-based preliminary classification of an associated event is performed. The result of the preliminary classification is used to facilitate... Agent: Ibm Corp. (aus) C/o Ostrow, Kaufman & Frankl LLP

20090063904 - Description of activities in software products: A method for describing activities in software products is provided. The method provides for identifying a plurality of activities in a software product that are of interest, defining an event structure to describe each identified activity as an event, associating each identified activity with one or more problem determination technologies,... Agent: Ibm St-svl Sawyer Law Group LLP

20090063903 - Method and apparatus for debugging application software in information handling systems over a memory mapping i/o bus: A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations... Agent: Mark P. Kahler

20090063905 - System and method for error checking of failed i/o open calls: A system and method in a data processing system for error checking and resolving failed input/output open calls. A configuration mechanism configures the options, such as the information stored in databases, details of how each error check is performed, and what actions should be taken when improper error checking occurs.... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090063906 - Method, apparatus and program storage device for extending dispersion frame technique behavior using dynamic rule sets: A method, apparatus and program storage device for providing control of statistical processing of error data over a multitude of sources using a dynamically modifiable DFT rule set is disclosed. The dispersion frame technique is extended in the present invention to provide dispersion frame rules with user-defined parameters thereby creating... Agent: Lieberman & Brandsdorfer, LLC

20090063907 - Debugging system, debugging apparatus and method: A debugging system which can efficiently obtain debugging information and which has excellent debugging efficiency is a debugging system which stops execution of a program executed in a program executing apparatus, at a break point, and assists debugging of the program, and which includes: a dump control unit configured to... Agent: Greenblum & Bernstein, P.L.C

20090063908 - Methods, systems, and products for verifying integrity of web-server served content: Methods, systems, and products are disclosed for verifying the integrity of web server content. Communication with a server is initiated and content is retrieved that is specified by a Uniform Resource Locator. The content is parsed and searched for an error message. When the content contains linked content, then the... Agent: At&t Legal Department Attn: Patent Docketing

20090063909 - Variable oscillator for generating different frequencies in a controller area network: A device suitable for use as a module in a Controller Area Network (CAN) system with a bus or connection includes relatively simple and inexpensive components, including an oscillator that generates a number of different frequencies in response to directions from a microcomputer. A CAN Controller receiving the frequencies is... Agent: Connolly Bove Lodge & Hutz LLP

20090063910 - Method of controlling a transceiver module: A method of controlling a transceiver module which includes a physical-layer integrated circuit having a physical-layer register unit, and a control integrated circuit having a control-side register unit. In the method, the physical-layer register unit is emulated by the control-side register unit and the physical-layer integrated circuit is prohibited from... Agent: Leydig Voit & Mayer, Ltd

20090063911 - Digital broadcast receiver: In digital broadcast receiver (100), when a bit error rate (BER) is larger than a threshold in BER determining part (109), power is supplied to tuner (103) and tuner (104) for diversity reception. When the BER is smaller than the threshold, power supply to one of tuner (103) and tuner... Agent: Ratnerprestia

20090063914 - Content-addressable memories and state machines for performing three-byte matches and secondary matches, and for providing error protection: A method and system for detecting matching strings in a string of characters utilizing content addressable memory using primary and secondary matches is disclosed.... Agent: Lee & Hayes, PLLC

20090063915 - Managing purgeable memory objects using purge groups: Memory objects associated with a portion of a cache (e.g., data blocks of a media file) are assigned a value based on their importance to an application that is consuming memory objects. The values are used to assign the data blocks to purge groups. The purge groups are a labeling... Agent: Fish & Richardson P.C.

20090063912 - Method and apparatus for implementing sram cell write performance evaluation: A method and apparatus for implementing static random access memory (SRAM) cell write performance evaluation, and a design structure on which the subject circuit resides are provided. ASRAM core includes each wordline connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state... Agent: Ibm Corporation RochesterIPLaw Dept 917

20090063913 - Semiconductor integrated circuit: Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and... Agent: Stanley P. Fisher Reed Smith LLP

20090063916 - Method for self-test and self-repair in a multi-chip package environment: A method and apparatus for operating a component including a memory device. The method includes receiving a plurality of commands and determining if a set of the plurality of commands matches a predefined pattern of commands configured to place the memory device into a test mode. Upon determining that the... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090063917 - Semiconductor integrated circuit: A semiconductor integrated circuit includes: a memory collars including: a memory cell; a fetch register that is configured to fetch data as a first fetch data; a comparing unit that is configured to compare the first fetch data with an expected value; a failure detecting signal output unit that is... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP

20090063918 - Apparatus and method for detecting word line leakage in memory devices: A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of... Agent: Townsend And Townsend And Crew, LLP

20090063919 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated

20090063920 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated

20090063921 - Staggered lbist clock sequence for noise (di/dt) amelioration: A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in current that occur during logical built-in self testing (LBIST) operations in integrated circuits. The method includes executing a first logical... Agent: Ibm Corporation

20090063923 - System and method for performing error correction at a memory device level that is transparent to a memory channel: A memory system is provided that performs error correction at a memory device level that is transparent to a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090063922 - System for performing error correction operations in a memory hub device of a memory module: A memory system is provided for performing error correction operations in a memory module. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub device comprises a link interface integrated into the... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20090063924 - Hybrid arq retransmission with reordering scheme employing multiple redundancy versions and receiver/transmitter therefor: A hybrid ARQ retransmission method in a communication system, wherein data packets consisting of symbols encoded with a forward error correction (FEC) technique prior to transmission are retransmitted based on an automatic repeat request and subsequently combined with previously received data packets the symbols of said data packets being modulated... Agent: Dickinson Wright PLLC James E. Ledbetter, Esq.

20090063926 - Apparatus and method for decoding using channel code: An apparatus and method for decoding a channel code is disclosed. The method for decoding a channel code includes the steps of receiving a low density parity check (LDPC) encoded signal from a transmitting party, generating a parity check matrix by adjusting the order of rows or columns of the... Agent: Lee, Hong, Degerman, Kang & Waimey

20090063929 - Apparatus and method for transmitting and receiving data in a communication system using low density parity check codes: An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a predetermined modulation scheme; and a bit mapper for mapping codeword bits... Agent: Cha & Reiter, LLC

20090063930 - Check matrix generating method, encoding method, decoding method, communication device, encoder, and decoder: A regular quasi-cyclic matrix is generated with cyclic permutation matrices and specific regularity given to the cyclic permutation matrices. A mask matrix for making the regular quasi-cyclic matrix into an irregular quasi-cyclic matrix is generated. An irregular masked quasi-cyclic matrix is generated by converting a specific cyclic permutation matrix in... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090063928 - Fec transmission processing apparatus and method and program recording medium: There is provided with an FEC transmission processing apparatus including: a media packet acquiring unit configured to successively acquire media packets from a media packet generator; a media packet transmission unit configured to transmit the media packets acquired to a media packet reception processing apparatus; an FEC packet generation unit... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090063925 - Lcpc decoding methods and apparatus: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code... Agent: Qualcomm Incorporated

20090063927 - Semiconductor device and method of controlling the same: A decoding section for decoding inputted first data; a first memory for being adapted to store second data obtained by decoding the first data; a second memory for being adapted to store error information on an error in decoding of the first data; and an output section for outputting the... Agent: Arent Fox LLP

20090063932 - Information processing device and method: In an information processing device, error detection information is generated from additional information and a header is generated from error detection information. An encoded header is then generated by appending a header-error correction code to the header and encoded additional information is generated by appending an information-error correction code to... Agent: Harness, Dickey & Pierce, P.L.C

20090063931 - Methods and architectures for layered decoding of ldpc codes with minimum latency: An embodiment of a decoder for decoding a Low-Density Parity-Check encoded input data includes a serial processing unit operating in clock cycles to perform serial update of the layers in the code. Operations of the serial processing unit to produce output data for a current layer are pipelined with acquisition... Agent: Graybeal Jackson Haley LLP

20090063933 - Lcpc decoding methods and apparatus: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code... Agent: Qualcomm Incorporated

20090063934 - Multi-channel memory system including error correction decoder architecture with efficient area utilization: A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second... Agent: Volentine & Whitt PLLC

20090063936 - Communication apparatus, reception method in said apparatus, codec, decoder, communication module, communication unit and decoding method: A communication apparatus includes a plurality of descramblers for subjecting a second header portion of a received frame to descrambling processing using pseudo-random sequences that differ from one another; a plurality of syndrome arithmetic units for performing a syndrome calculation, which is in accordance with a cyclic redundancy check code,... Agent: Canon U.s.a. Inc. Intellectual Property Division

20090063935 - Method and system for wireless communication of uncompressed video information: A method and system for communication uncompressed video over a wireless communication medium is provided. Pixels in an uncompressed video frame are grouped into groups of pixels for wireless transmission from a transmitter to a receiver, wherein the neighboring pixels in each group possess (have) high spatial correlation. Upon receiving... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20090063937 - Architecture and control of reed-solomon error-correction decoding: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information... Agent: Ropes & Gray LLP

20090063938 - Decoding error correction codes using a modular single recursion implementation: Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the... Agent: Steven J. Cahill/ Hitachi Gst

20090063939 - Acs (add compare select) implementation for radix-4 sova (soft-output viterbi algorithm): ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, the ACS module generates a... Agent: Garlick Harrison & Markison

20090063940 - Register exchange network for radix-4 sova (soft-output viterbi algorithm): A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput.... Agent: Garlick Harrison & Markison

20090063941 - Method and system for using redundancy to exchange data in a multicast or one way environment: A system for use in one-way communications takes data from a source and parses it into work units. The work units may have a fixed size. The data of the work units is given to a redundant array of independent disks (RAID) library. The RAID library applies parity to the... Agent: Watchstone P+d, PLLC