|Error detection/correction and fault detection/recovery patents - Monitor Patents|
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Error detection/correction and fault detection/recovery January recently filed with US Patent Office 01/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/29/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090031161 - Method, operating system and computing hardware for running a computer program: A method for executing a computer program on computing hardware, e.g., on a microprocessor, is provided, the computer program including multiple program objects and errors being detected in the method while running the computer program on the computing hardware. The program objects are subdivided into at least two classes, and... Agent: Kenyon & Kenyon LLP
20090031164 - Method for self-diagnosing remote i/o enclosures with enhanced fru callouts: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. When a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the... Agent: Ibm Corp (ya) C/o Yee & Associates Pc
20090031165 - Method for self-diagnosing remote i/o enclosures with enhanced fru callouts: A method, apparatus, and computer instructions for self-diagnosing remote I/O enclosures with enhanced FRU callouts. when a failure is detected on a RIO drawer, a data processing system uses the bulk power controller to provide an alternate path, rather than using the existing RIO links, to access registers on the... Agent: Ibm Corp (ya) C/o Yee & Associates Pc
20090031163 - Speedpath repair in an integrated circuit: A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality... Agent: Freescale Semiconductor, Inc. Law Department
20090031166 - Warm reboot enabled kernel dumper: In one embodiment, a method of a kernel dumper module includes generating a dump file associated with a kernel when the kernel crashes, storing the dump file to a functional memory upon applying an overwrite protection to a core dump of the dump file, restarting the kernel through a warm... Agent: Intellevate
20090031167 - Storage control system and storage control method: Unique information including a logical type name is stored in a user data area of a management area as a media of the alternative disk drive to become an alternative of the storage device. Upon using the alternative disk drive, a disk controller reads the unique information of the alternative... Agent: Stanley P. Fisher Reed Smith LLP
20090031168 - Monitoring vrm-induced memory errors: A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold,... Agent: Dillon & Yudell LLP
20090031169 - Self-repairing of microprocessor array structures: A level of indirection is utilized when writing to a microprocessor array structure, thereby masking hard faults in the array structure. Among other benefits, this minimizes the use of a backward error recovery mechanism with its inherent delay for recovery. The indirection is used to effectively remove from use faulty... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP
20090031171 - Apparatus, system, and method for responsive acquisition of remote debug data: An apparatus, system, and method are disclosed for responsive acquisition of remote debug data. The apparatus for responsive acquisition of remote debug data is provided with a plurality of modules configured to detect an error on a local device, trigger a remote device to generate a remote debug data set... Agent: Kunzler & Mckenzie
20090031170 - System and method to facilitate automatic globalization verification test: A method, system and program are disclosed for validating the generation of globalized versions of software programs. The directory structure of an installed software program is traversed to discover resource files containing globalized strings. The values of the globalized string and its corresponding key in the resource file are then... Agent: Hamilton & Terrile, LLP Ibm Rsw
20090031172 - Device, method, program, and recording medium for error factor measurement, and output correction device and reflection coefficient measurement device provided with the device for error factor measurement: There is provided an error factor measurement device for measuring an error factor in a switch branch signal source including a signal source and a switch, and the error factor measurement device includes a reference error factor component recording unit which records respective components E12a, E21a of a frequency tracking... Agent: Greenblum & Bernstein, P.L.C
20090031173 - Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a... Agent: Ibm Corp (ya) C/o Yee & Associates Pc
20090031176 - Anomaly detection: A system such as a Web-based system in which a plurality of computers interact with each other is monitored to detect online an anomaly. Transactions of a service provided by each of a plurality of computers to another computer are collected, a matrix of correlations between nodes in the system... Agent: Louis Paul Herzberg
20090031174 - Server outage data management: Server outage data is automatically created and managed. Outage data is automatically retrieved from one or more servers at which an outage is detected by an agent installed on the server. The agent may search for outage event data and transmit the data to a monitoring application. The monitoring application... Agent: Vierra Magen/microsoft Corporation
20090031175 - System and method for analyzing streams and counting stream items on multi-core processors: Systems and methods for parallel stream item counting are disclosed. A data stream is partitioned into portions and the portions are assigned to a plurality of processing cores. A sequential kernel is executed at each processing core to compute a local count for items in an assigned portion of the... Agent: Keusey, Tutunjian & Bitetto, P.c.
20090031177 - Method for providing download and upload service in network control system: The present invention relates to a method for providing a download and upload service using variable length packet communication in a living network control system. For example, a user located inside or outside a house controls or monitors operations or operation states of various appliances such as refrigerator or laundry... Agent: Mckenna Long & Aldridge LLP
20090031178 - Method and system for adaptive interleaving: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive... Agent: Brinks Hofer Gilson & Lione
20090031179 - Jtag test code and data compiler and method: The Compiler is also capable of allocating and managing a memory structure to store multiple data structure at the same time so that it will be ready to be used by the JTAG-bus controller during scan operations. This will allow for an expedited execution of the test functions since the... Agent: Sam Michael
20090031180 - Method for discovering and isolating failure of high speed traces in a manufacturing environment: A mechanism is provided for discovering and isolating failure of high speed traces in a manufacturing environment. The mechanism utilizes transmit pre-emphasis and receiver equalization in combination with attenuated wrap plugs to enhance discovery and isolation of manufacturing defects in the manufacturing environment. The mechanism adjusts pre-emphasis and equalization in... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.
20090031181 - Automated root cause identification of logic controller failure: A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic controller, and mapping the logic controller failure information to the... Agent: General Motors Corporation Legal Staff
20090031182 - Information communication terminal, radio communication apparatus and radio communication network system capable of performing communication corresponding to purpose: An information communication terminal performs communications with another information communication terminal over a radio communication network system. In the information communication terminal, a receiving unit receives an externally transmitted frame. In a state where error correction is to be performed, a correction processing unit outputs data after performing error correction... Agent: Fish & Richardson P.c.
20090031184 - Mimo hybrid-arq using basis hopping: A Hybrid Automatic Retransmission Request (H-ARQ) technique is provided for Multi-Input Multi-Output (MIMO) systems. The technique changes the basis (V) upon retransmission, which helps reduce the error probability upon retransmission. This basis hopping technique provides for improved performance gain without significant increase in design complexity. In one embodiment, communication device... Agent: Texas Instruments Incorporated
20090031183 - Retransmission control scheme and wireless communication apparatus: A retransmission control scheme and a wireless communication apparatus wherein the efficiency of retransmission control is enhanced to further improve the system throughput. In this wireless communication apparatus (100), an error occurrence factor addressing part (140) receives information related to the error occurrence factor of a transmitted packet or information... Agent: Dickinson Wright Pllc James E. Ledbetter, Esq.
20090031185 - Hybrid arq systems and methods for packet-based networks: Systems and methods for hybrid automatic repeat-request (HARQ) communication, comprising a transmitter employing hybrid automatic repeat-request (HARQ) and able to retransmit an incorrectly received packet without differently re-encoding data bits. The transmitter is further able to select at least one bit from any in a set to forward in at... Agent: Texas Instruments Incorporated
20090031187 - Data recording/reproducing apparatus and data recording/reproducing method: A data format, a data recording/reproducing method, and a data recording/reproducing apparatus are provided for effectively correcting data errors caused by dust and scratches on a recording medium even with the use of a conventional ECC. The data recording/reproducing apparatus includes a generation unit that generates predetermined data units by... Agent: Staas & Halsey LLP
20090031186 - Error correction coding apparatus: An error correction coding apparatus is disposed to generate a low-density parity-check code 16 from an input information sequence 15 by using a low-density parity-check matrix which satisfies a predetermined weight distribution, and includes a low-density parity-check matrix output means 13 for forming the above-mentioned low-density parity-check matrix by continuously... Agent: Birch Stewart Kolasch & Birch
20090031188 - Error correcting code generation method and memory control apparatus: An objective of the present invention is to make it possible to appropriately correct an error of data in a cache memory. A store processing unit generates an nt-ECC on the basis of data stored in a non-target area that was read out from a cache memory with a search... Agent: Staas & Halsey LLP
20090031192 - Channel encoding apparatus and method: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order... Agent: Mcneely Bodendorf LLP
20090031189 - Method and system for forming a formatted content stream and using a cyclic redundancy check: A communication system 100 includes a content repository 274 storing a content file and a video transport processing system 223 receiving the content file and dividing the content file into a plurality of content file portions, forming a leading data portion, determining a cyclic redundancy check value, forming a trailing... Agent: The Directv Group, Inc. Patent Docket Administration
20090031190 - Turbo decoding system, transmission power control method and cdma mobile communication terminal: There are disposed a BLER measuring section 10 to measure BLER as reception quality for each number of decoding bits on the basis of a CRC judge result after an error correction by the turbo decoding section 4 and an outer loop power control and iteration control section 11 to... Agent: Nec Corporation Of America
20090031191 - Wyner-ziv coding based on tcq and ldpc codes: An encoder employs a trellis coded quantization (TCQ) unit and a compression unit. The TCQ uses a set of polynomials that have been selected to maximize granular gain. The TCQ unit operates on a block of samples from a source. The compression unit compresses bit planes of the TCQ output,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.
20090031193 - Syndrome-error mapping method for decoding linear and cyclic codes: Two embodiments of the present invention are described. The first embodiment uses a full syndrome-error table, whereas the second uses a partial syndrome-error table. The method includes the following steps: calculating a syndrome corresponding to the received bit string; determining whether the syndrome is a zero bit string; when the... Agent: Pai Patent & Trademark Law Firm
20090031194 - Error-detecting and correcting fpga architecture: A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected,... Agent: Lewis And Roca LLP
20090031196 - Error-correcting method used for decoding data transmissions: An error-correcting method used for decoding of data transmissions is disclosed. The error-correcting method is used for data with an error-correcting part and comprises: providing a multinomial for processing an error-correcting part to get an operational result; providing a database for saving the corresponding operational results of each single bit;... Agent: Joe Mckinney Muncy
20090031195 - Method and apparatus for encoding and decoding reed-muller codes: A method and apparatus for encoding and decoding Reed-Muller codes are provided. In exemplary embodiments, a method comprises receiving a code-word encoded with a Reed-Muller code, generating a pattern to retrieve voting bits, decoding the code-word based on the voting bits and, and providing the decoded code-word.... Agent: Carr & Ferrell LLP
20090031197 - Erasure decoding for receivers: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a... Agent: Texas Instruments Incorporated
20090031198 - Method, an electrical system, a digital control module, and an actuator control module in a vehicle: A method, control module and system of a vehicle including at least a first and a second control computer each containing a number of local Digital Control Modules and at least one Actuator Control Module wherein the Actuator Control Module of each control computer is operatively connected to all local... Agent: Venable LLP
20090031199 - File download and streaming system: A method of encoding data operates on an ordered set of input symbols and includes generating redundant symbols from the input symbols, and includes generating output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much... Agent: Townsend And Townsend And Crew, LLP
20090031200 - High rate, long block length, low density parity check encoder: There is provided a parity check encoder (100) comprising a data memory (PROM) configured for storing input data, a calculation/parity result storage means (CPRSM), and a selector/serializer means (SSM). The CPRSM (104, 106) is coupled to the PPDM (102) and is configured to calculate parity bits in parallel using input... Agent: Harris Corporation C/o Darby & Darby Pc
20090031202 - Methods, systems, and computer program products for class verification: A method, system, and computer program product for class verification are provided. The method includes initiating loading of a class, and searching for the class in verification caches. A record from the verification caches, including a checksum, is returned upon locating the class. The method further includes comparing the checksum... Agent: Cantor Colburn LLP - Ibm Rochester Division
20090031201 - Optimized decoding in a receiver: A receiver includes a decoder configured to decode at least a portion of a data stream comprising a data frame. The data frame includes a code block having a data block and a parity block. The receiver also includes a controller. The controller is configured to determine whether to disable... Agent: Qualcomm Incorporated01/22/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090024867 - Redundant data path: Disclosed are redundant data path(s) for transmission of graphical data between components in a graphical display system. The redundant data path(s) are used to transmit graphical data by at least two independent means, so that if a failure in one data path occurs, a data transmitted via a separate data... Agent: Hugh D Jaeger, P.a.
20090024869 - Autonomous takeover destination changing method in a failover: For realizing an optimum failover in NAS, this invention provides a computer system including: a first computer; a second computer; a third computer; and a storage device coupled to the plurality of computers via a network, in which: the first computer executes, upon reception of an access request to the... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090024868 - Business continuation policy for server consolidation environment: A method, computer program product and system that establishes and maintains a business continuity policy in a server consolidation environment. Business continuity is ensured by enabling high availability of applications. When an application is started, restarted upon failure, or moved due to an overload situation, a system is selected best... Agent: Campbell Stephenson LLP
20090024870 - System and method for managing application server responses in ip multimedia subsystem: In an Internet Protocol Multimedia Subsystem (IMS), a user profile is provided with an extended schema that provides one or more error code definitions and associated error handling instructions. Response codes received in response to requests to an application server are processed to determine if a matching response code is... Agent: Ericsson Inc.
20090024871 - Failure management method for a storage system: Provided is a method of performing backup and recovery of data by using journaling, and performing management upon occurrence of a failure. The method includes: a first step of setting a recovery point indicative of the given time; a second step of creating an information of correspondence between the snapshot... Agent: Stanley P. Fisher Reed Smith LLP
20090024872 - Remote access diagnostic device and methods thereof: A method for diagnosing and correcting errors at a data processing system is disclosed includes detecting at a first device of the system, such as a network interface device, an error at a second device of the system, such as a data processor. In response to detecting the error, the... Agent: Larson Newman Abel Polansky & White, LLP
20090024873 - System and method for increasing error checking performance by calculating crc calculations after multiple test patterns for processor design verification and validation: A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024874 - Generic template to autogenerate reports for software target testing: Apparatus and methods allow users of software testing applications to obtain auto-generated reports. During use, one or more software test cases of a feature of a software target are identified for execution. A template, common to the software cases, autogenerate a first report in a first computing language, e.g., XML,... Agent: King & Schickli, Pllc
20090024875 - Serial advanced technology attachment device and method testing the same: A serial advanced technology attachment (SATA) device is provided. The SATA device includes a digital block and an analog black. The digital block is configured to generate and output an out-of-band (OOB) control signal. The analog block is configured to receive the OOB control signal, which has been output from... Agent: F. Chau & Associates, Llc
20090024876 - System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation: A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024877 - System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation: A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024878 - Apparatus and computer program product in a processor for performing in-memory tracing using existing communication paths: An apparatus and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted... Agent: Ibm Corp (ya) C/o Yee & Associates Pc
20090024879 - Disk array device, parity data generating circuit for raid and galois field multiplying circuit: In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using... Agent: Young & Thompson
20090024880 - System and method for triggering control over abnormal program termination: Methods and systems for handling errors in applications are provided. A comparison may be executed to confirm that actual results are in accordance with expected results. If the comparison results in an application error, a special execution software object is executed. The special execution software object obtains and maintains a... Agent: Kenyon & Kenyon LLP
20090024881 - System and method for debt valuation: A method of evaluating and acquiring charged-off debt portfolios that includes providing a seller with an assessment mechanism for the debt portfolio, receiving from the seller a proposed price and debt account information for the debt portfolio based on the use of the assessment mechanism, and determining whether to acquire... Agent: Renner Otto Boisselle & Sklar, LLP
20090024882 - Method for monitoring an internal control signal of a memory device and apparatus therefor: Disclosed is a method for monitoring an internal control signal of a memory device and an apparatus therefore. The method includes (a) generating a first signal having a first pulse width by a burst operation command, (b) receiving the first signal, and generating N−1 (where, N is a burst length)... Agent: Ladas & Parry LLP
20090024883 - Inter-asic data transport using link control block manager: An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a... Agent: Schwegman, Lundberg & Woessner, P.a.
20090024884 - Memory controller method and system compensating for memory cell data losses: A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP
20090024885 - Semiconductor integrated circuit and test system thereof: A semiconductor integrated circuit has a memory collar including a memory cell configured to store a written data pattern and read and output the data pattern, and a register configured to store a failed data pattern, and a built-in self test circuit configured to write the data pattern in the... Agent: Amin, Turocy & Calvin, LLP
20090024886 - System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation: A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024887 - Semiconductor storage device, data write method and data read method: A semiconductor storage device includes an arithmetic operation unit configured to perform an arithmetic operation of generating a different error detecting code depending on the information of a memory address, using the data and the information of the memory address in a memory cell into which the data is written,... Agent: Gregory Turocy Amin, Turocy & Calvin, LLP
20090024888 - Semiconductor device: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the... Agent: Mcdermott Will & Emery LLP
20090024889 - Integrated circuit having built-in self-test features: An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and distribute a built-in self-test signal. The built-in self-test signal can emulate signals internal to the integrated circuit during normal... Agent: Daly, Crowley, Mofford & Durkee, LLP
20090024890 - Circuit arrangement, data processing device comprising such circuit arrangement as well as method for identifying an attack on such circuit arrangement: In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090024893 - Integrated circuit arrangement and design method: An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (100). The arrangement (10) further comprises space... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090024891 - System and method for pseudo-random test pattern memory allocation for processor design verification and validation: A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition,... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024892 - System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation: A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that,... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024894 - System and method for predicting iwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode: During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen
20090024895 - Transmission control methods and devices for communication systems: A system and method for transmission control by an access device in a wireless communication system including a plurality of receiving devices, including receiving, from a super ordinate device, first transmission data for transmission to a subscriber device, wherein the access device communicates with the plurality of receiving devices, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090024896 - Method and apparatus for improving hybrid automatic repeat request operation in a wireless communications system: A method of improving Hybrid Automatic Repeat Request operation for a user equipment operating in HS-SCCH less operation in a wireless communications system includes receiving a retransmission data in an HARQ procedure, determining a decoding result of data stored in a first soft buffer, combining the retransmission data with the... Agent: North America Intellectual Property Corporation
20090024897 - Robust digital communication system: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust... Agent: Zenith Electronics Corporation
20090024898 - Concurrent production of crc syndromes for different data blocks in an input data sequence: Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The... Agent: Texas Instruments Incorporated
20090024900 - Cyclic redundancy checking in lane-based communications: Various embodiments provide a system and method for cyclic redundancy checking in lane-based data communications. A particular embodiment provides a data stream receiver to receive an input data stream having a plurality of data lanes, and a lane-based CRC generator to generate a set of CRC values, each CRC value... Agent: Schwegman, Lundberg & Woessner, P.a.
20090024899 - System and method for providing data integrity in a non-volatile memory system: An invention is provided for ensuring data integrity in a non-volatile memory system, including boot block data integrity during Power On Reset. The invention includes loading data into a buffer, such as a flash buffer, and generating an error detection code for the data utilizing a check code generator located... Agent: Patent Venture Group
20090024901 - Apparatus and method for decoding bursts of coded information: A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of... Agent: Vedder Price/freescale
20090024902 - Multi-channel error correction coder architecture using embedded memory: A memory system includes a plurality of memory devices; and a memory controller having a plurality of communication channels for communicating data with the plurality of memory devices. The memory controller includes an error correction encoder that is adapted to encode data to be communicated from the memory controller via... Agent: Volentine & Whitt Pllc
20090024903 - Nibble encoding for improved reliability of non-volatile memory: A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to... Agent: Intel Corporation C/o Intellevate, Llc
20090024905 - Combined distortion estimation and error correction coding for memory devices: A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, second analog values are read from the respective memory... Agent: Darby & Darby P.c.
20090024904 - Refresh of non-volatile memory cells based on fatigue conditions: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each... Agent: Leffert Jay & Polglaze, P.a. Attn: Kenneth W. Bolvin
20090024906 - Method and apparatus for data transmission using multiple transmit antenas: A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas is disclosed. A set of bits of a digital signal are used to generate a codeword. Codewords are provided according to a channel code. Delay elements may be provided in antenna output channels,... Agent: At&t Corp.
20090024907 - Crc syndrome generation for multiple data input widths: A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have... Agent: Texas Instruments Incorporated
20090024908 - Method for error registration and corresponding register: A method for error registration and a register which is assigned to a dual-computer system, information in the form of bits being stored in the register, the dual-computer system including an error-detection mechanism, and the bits in the register as error bits representing at least one error signal of the... Agent: Kenyon & Kenyon LLP
20090024909 - Turbo coding having combined turbo de-padding and rate matching de-padding: Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding.... Agent: Garlick Harrison & Markison01/15/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090019305 - Market data recovery: Networks, systems and methods for recovering data messages from a market data stream and for building a book for a financial instrument are disclosed. An out-of-band data stream related to an as-of state of the market for one or more financial instruments is distributed parallel to a stream of market... Agent: Banner & Witcoff, Ltd., Attorneys For Client No. 006119
20090019306 - Protecting tag information in a multi-level cache hierarchy: In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag... Agent: Trop Pruner & Hu, PC
20090019307 - Digital broadcast file data receiving method and apparatus: A digital broadcast file data receiving method and a digital broadcast file data receiving apparatus are provided. The digital broadcast file data receiving method and the digital broadcast file data receiving apparatus enable reception and display of proper broadcast file data by detecting an error in a specific data block... Agent: JeffersonIPLaw, LLP
20090019308 - Method and apparatus for data recovery system using storage based journaling: A storage system maintains a journal and a snapshot of one or more data volumes. Two journal entry types are maintained, an AFTER journal entry and a BEFORE journal entry. Two modes of data recovery are provided: “fast” recovery and “undo-able” recovery. A combination of both recovery modes allows the... Agent: Townsend And Townsend And Crew, LLP
20090019309 - Method and computer program product for determining a minimally degraded configuration when failures occur along connections: A minimally degraded configuration is determined when failing connections occur. Associative deconfigurations are determined from deconfiguring hardware items in a server system, associative groups are derived, and failed connections are determined. Failed connections are determined between two hardware items that are in the same associative group, and the two hardware... Agent: Cantor Colburn LLP - IBM Rochester Division
20090019310 - Collecting and representing knowledge: Problem determination knowledge is provided by an extraction tool that extracts tag information recorded in identified problem tracking tools, where the tags relate to problem knowledge. The extracted tag information is examined to produce a catalog of symptom definitions that can be utilized by tools such as problem submission, logging... Agent: Stevens & Showalter, L.L.P.
20090019311 - Method of testing an electronic system: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench... Agent: Young & Thompson
20090019312 - System and method for providing an instrumentation service using dye injection and filtering in a sip application server environment: An instrumentation service is described that uses dye injection and filtering in a Session Initiation Protocol (SIP) application server environment. The instrumentation service can provide a flexible mechanism for selectively adding diagnostic code to the SIP application server and the various applications running on it. It can allow flexible selection... Agent: Fliesler Meyer LLP
20090019314 - Network advisor: A system for diagnosing the configuration and use of devices in an interconnected network. The system may be used to analyze a network and/or discrete network devices, and then suggest steps that a user may take to improve the performance or usability of the network and/or device.... Agent: Black Lowe & Graham, PLLC
20090019313 - System and method for performing client-side input validation: A system and method for performing client-side input validation may include a JavaServer Faces (JSF) environment having parameters indicating whether to enable or disable client-side validation for a given application, and one or more validation functions for validating required fields, minimum and maximum values, regular expressions, input lengths, or other... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20090019315 - Automated software testing via multi-channel remote computing: Embodiments of the present invention address deficiencies of the art in respect to software functional testing and provide a method, system and computer program product for automated software functional testing via multi-channel remote computing. In one embodiment of the invention, an automated software functional testing data processing system can be... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg
20090019318 - Approach for monitoring activity in production systems: An approach is provided for monitoring of the activity in production computer systems. During a first period of time, substantially all of a first plurality of dispatches sent to a CPU are recorded. Each dispatch of the first plurality of dispatches indicates an initial instruction of a stream of instructions... Agent: Hickman Palermo Truong & Becker, LLP
20090019317 - Mechanism for identifying the source of performance loss in a microprocessor: A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first... Agent: Rory D. Rankin Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20090019316 - Method and system for calculating and displaying risk: A system for calculating and rendering a risk level. In response to receiving an input to perform an action within a data processing system, a level of risk to the data processing system to perform the action is calculated based on a set of rules. It is determined whether the... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090019319 - Remote monitoring diagnostic system: Disclosed is a remote monitoring diagnostic system in which a center and monitoring diagnostic units of a number of objects to be monitored are connected by a network. The center includes an algorithm forming unit for forming algorithms for monitoring, diagnosing, and operating each object to be monitored, a program... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090019320 - Method and apparatus for troubleshooting a computer system: One embodiment of the present invention provides a system for troubleshooting a computer system. During operation, the system receives an identifier for a suspect computer system, which is suspected of operating abnormally. The system also receives an identifier for a normal computer system, which is operating normally. Next, the system... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20090019321 - Error correction for memory: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.... Agent: Schwegman, Lundberg & Woessner, P.A.
20090019322 - Production line control system: A production line control system (10) comprising a support personnel call device (PB1, PB2, PB3, PB4) for a worker (M1, M2, M3, M4) to call for support personnel (H1, H2); a time-counting device (12) for operating when a call signal (I1, I2, I3, I4) is obtained; and a central control... Agent: Standley Law Group LLP
20090019324 - Method and apparatus for analyzing serial data streams: An apparatus and method for processing a data signal is provided. An acquisition unit of a test instrument acquires a data signal for a predetermined time. The data signal is stored in a memory of the test instrument and a clock recovery unit recovers a clock signal from the stored... Agent: Frommer Lawrence & Haug
20090019323 - System and method for initializing a memory system, and memory device and processor-based system using same: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the... Agent: Dorsey & Whitney LLP Intellectual Property Department
20090019325 - Memory device, supporting method for error correction thereof, supporting program thereof, memory card, circuit board and electronic apparatus: A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an... Agent: Staas & Halsey LLP
20090019326 - Self-synchronizing bit error analyzer and circuit: A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data... Agent: International Business Machines Corporation Dept. 18g
20090019327 - Generating device, generating method, program and recording medium: A generation apparatus and the like for generating a test vector set capable of reducing differences in a logic value generated before and after a scan capture for outputs from scan cells included in a full-scan sequential circuit are provided. A generation apparatus 200 generating an initial test vector set... Agent: Amin, Turocy & Calvin, LLP
20090019328 - Ic circuit with test access control circuit using a jtag interface: An integrated circuit comprises a first circuit portion (106) with a JTAG interface (108) and a test access port (110). A second circuit portion (114) has a serial bus interface (112); and a test access control circuit (104) is connected to the JTAG interface (108) via the test access port... Agent: Philips Intellectual Property & Standards
20090019329 - Serial scan chain control within an integrated circuit: An integrated circuit 2 includes a plurality of circuit blocks 38, 40, 44 each having an associated serial scan chain loop 32, 34, 36 which extends from a converter 10, to the circuit block 38, 42, 44 in question and then back to the converter 10. Multiplexing circuitry 50, 52... Agent: Nixon & Vanderhye, PC
20090019331 - Integrated circuit for a data transmission system and receiving device of a data transmission system: The invention relates to an integrated circuit for a data transmission system comprising a) a plurality of functional units, b) a TAP controller, according to IEEE 1149, having a JTAG interface, and c) a test unit for testing the functionality of the functional units, whereby the test unit has at... Agent: Muncy, Geissler, Olds & Lowe, PLLC
20090019330 - Integrated circuit having built-in self-test features: An integrated circuit includes a sensor for providing a sensor output signal and a diagnostic circuit coupled to the sensor for providing a self-diagnostic signal. The self-diagnostic signal comprises the sensor output signal during a first time duration and an inverted sensor output signal during a second different time duration.... Agent: Daly, Crowley, Mofford & Durkee, LLP
20090019333 - Generation of parity-check matrices: Circuits perform row-by-row matrix generation for encoding and decoding of data blocks. They perform fast algebraic generation of high performance low density parity check (LDPC) matrices suitable for use in a wide range of error correction coding and decoding (ECC) applications. Circuit operation is based on a mathematical Cyclic Ring... Agent: Jacobson Holman PLLC
20090019332 - Siso decoder with sub-block processing and sub-block based stopping criterion: a control unit (27) for controlling said at least one SISO decoding unit (17) based on the read window activity flags such that the information symbols of a window for which the corresponding window activity flag is set inactive are not SISO decoded in subsequent iterations.... Agent: Philips Intellectual Property & Standards
20090019335 - Auxiliary path iterative decoding: A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and... Agent: Sun Microsystems, Inc C/o Marsh Fischmann & Breyfogle LLP
20090019334 - Error correction system using concatenated codes: This invention provides an error correction system whereby codes, including codes known to be optimum, may be concatenated together so that a longer code is produced which may be decoded by decoding the individual codes using any type of error correcting decoder including list decoders, Dorsch decoders in particular, and... Agent: Martin Tomlinson
20090019336 - Memory and 1-bit error checking method thereof: A memory 1-bit error checking method is provided. Firstly, at least one piece of data fragment whose side is 2n bits is received. Next, an error correction code, a parity code and a data code are generated and written in the memory. Then, the at least one piece of data... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090019338 - Communications device and wireless communications system: Turbo coding and decoding devices provide interleaving in the error correction coding process, which improves error correction capability. A turbo decoding device for decoding data obtained by performing error detection coding on a plurality of data blocks and further subjecting that data to turbo coding that includes interleaving in the... Agent: Hanify & King Professional Corporation
20090019337 - Methods and apparatus to compute crc for multiple code blocks: A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information... Agent: Robert E. Bushnell
20090019339 - Power reception optimization method, and associated apparatus, for operating upon an encoded data block: Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts.... Agent: Docket Clerk
20090019340 - Non-systematic coded error correction: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth
20090019341 - Dynamic memory architecture employing passive expiration of data: Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in... Agent: Ryan, Mason & Lewis, LLP
20090019342 - Determining a message residue: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090019343 - Loss compensation device, loss compensation method and loss compensation program: It is possible to save storage resources. A loss compensation device for compensating a loss in periodical signals when the loss occurs in an arbitrary section of the periodical signals which are divided into predetermined sections and received in time series, includes: a periodical signal storage which stores one or... Agent: Rabin & Berdo, PC
20090019344 - Apparatus and method for generating error detection codes: An apparatus for generating error detection codes can include an error detection code generation unit configured to generate virtual error detection codes using virtual DBI information and data, and an error detection code regeneration unit configured to generate error detection codes using even and odd number information which define whether... Agent: Baker & Mckenzie LLP Patent Department
20090019345 - Compression of stream data using a hierarchically-indexed database: The present invention, in particular embodiments, is directed to methods, apparatuses and systems that provide an efficient compression technique for data streams transmitted to storage devices or over networks to remote hosts. Local storage as well as network transmission of streams is made more efficient by awareness and utilization of... Agent: Baker Botts L.L.P.
20090019346 - Crc counter normalization: The ability to accurately and efficiently calculate and report communication errors is becoming more important than ever in today's communications environment. More specifically calculating and reporting CRC anomalies in a consistent manner across a plurality of communications connections in a network is crucial to accurate error reporting. Through a normalization... Agent: Jason H. Vick Sheridan Ross, PC01/08/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090013207 - Predicting microprocessor lifetime reliability using architecture-level structure-aware techniques: A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure... Agent: Cantor Colburn LLP-ibm Yorktown
20090013209 - Apparatus for connection management and the method therefor: An apparatus and method for scheduling data distributions to or results information from, or collectively, “jobs” a plurality of data processing systems via a network. A connection to a target system is created. For each distribution, a session, which is an independent thread, is allocated from one of a plurality... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090013208 - Real time automated exception notification and reporting solution: A closed loop, autonomic exception notification and resolution system enables an application to proactively collect and forward exception information to developers with no user intervention; in some cases before the user is even aware that an exception has occurred. A notification process ensures that the appropriate resources can be applied... Agent: Emc Corporation Office Of The General Counsel
20090013210 - Systems, devices, agents and methods for monitoring and automatic reboot and restoration of computers, local area networks, wireless access points, modems and other hardware: An embodiment of the invention is a client on a local area network that periodically and automatically evaluates its physical connectivity with the local area network, exercises local-network services such as DHCP, and verifies Internet connectivity and function by pinging one or more numerically specified IP addresses and by pinging... Agent: John S. Pratt, Esq Kilpatrick Stockton, LLP
20090013211 - Memory channel with bit lane fail-over: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the... Agent: Caven & Aghevli C/o Intellevate, LLC
20090013212 - System and method for computer data recovery: The invention consists of a method of data recovery for a computer system, the steps comprising: a) initializing hardware associated with the computer system, the hardware including a hard drive, and a minimum of 32 MB of RAM; b) initializing network devices and connections associated with the computer system; c)... Agent: Lang Michener
20090013213 - Systems and methods for intelligent disk rebuild and logical grouping of san storage zones: A method of rebuilding a replacement drive used in a RAID group of drives is disclosed. The rebuilding method includes tracking data modification operations continuously during use of the drives. The method also includes saving the tracked data modifications to a log in a persistent storage, where the tracked data... Agent: Martine Penilla & Gencarella, LLP
20090013214 - On-chip samplers for asynchronously triggered events: Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP
20090013215 - Storage control device and enclosure-unit power control method: The storage control device of the present invention switch-connects each of enclosures and individually stops the transmission of power to the enclosures that are not being accessed in order to reduce the power consumption amount. A plurality of additional enclosures are switch-connected via an inter-device switch to a base enclosure.... Agent: Stanley P. Fisher Reed Smith LLP
20090013216 - System for facilitating problem resolution: Disclosed is a data processing system for facilitating problem resolution. The data processing system-implemented system includes a configuring module for configuring a system pathway that leads to a solution, and an associating module for associating a usage indicator with the symptom pathway, the usage indicator indicating a frequency in which... Agent: Sughrue Mion PLLC Uspto Customer No With Ibm/svl
20090013217 - Multicore abnormality monitoring device: A monitoring side core has an input protection part including an access checking part and an address information storage part. Address information of a count RAM area and an access prohibiting mode to the address are stored in the address information storage part in advance by CPU. The access checking... Agent: Nixon & Vanderhye, PC
20090013218 - Datalog management in semiconductor testing: Methods, systems and modules for datalog management. In one embodiment, the logging of data is allowed to at least occasionally occur while the handling equipment is preparing device(s) for testing. Additionally or alternatively, in one embodiment with a plurality of test site controllers, after testing has been completed at all... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw
20090013219 - Reconfigurable device: Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information... Agent: Mcginn Intellectual Property Law Group, PLLC
20090013220 - Data collecting apparatus and gateway apparatus: The data collecting apparatus includes device value collecting unit 2 for collecting device values from a plurality of devices, abnormal state storage unit 3 for storing the monitored device to be monitored and the threshold value or condition by which it is determined that the monitored device is abnormal, abnormal... Agent: Sughrue-265550
20090013221 - Multi-component system: To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal... Agent: Townsend And Townsend And Crew, LLP
20090013222 - Managing analysis of a degraded service in a grid environment: A method, system, and program managing analysis of a degraded service in a grid environment are provided. In a grid environment of multiple diverse systems, a service availability management agent is enabled to receive multiple types of error messages generated from the multiple diverse systems within the grid environment. Each... Agent: Ibm Corp (ap) C/o Amy Pattillo
20090013223 - Multi-bit error correction scheme in multi-level memory storage system: A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent characteristic parameter bands are assigned binary multi-bit values that differ... Agent: Law Office Of Ido Tuchman (yor)
20090013224 - Integrated circuit with blocking pin to coordinate entry into test mode: An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared... Agent: Mhkkg/sun
20090013225 - Test mode control circuit: Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090013226 - Blocking the effects of scan chain testing upon a change in scan chain topology: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer.... Agent: Texas Instruments Incorporated
20090013227 - Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit: A method is provided that uses non-linear data compression in order to generate a set of test vectors for use in scan testing an integrated circuit. The method includes the steps of initially designing the set of test vectors, and selecting one of multiple available coding schemes for each test... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090013228 - Bist ddr memory interface circuit and method for testing the same: An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test... Agent: Texas Instruments Incorporated
20090013229 - Built-in self-test using embedded memory and processor in an application specific integrated circuit: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test... Agent: Schwabe, Williamson & Wyatt, P.C.
20090013230 - Circuit arrangement and method of testing and/or diagnosing the same: To further develop a circuit arrangement (100; 100′), and in particular an application circuit, that is arranged to generate at least one test pattern, and a method of testing and/or diagnosing the circuit arrangement (100; 100′) in such a way that reliable fault detection is ensured, it is proposed that... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090013231 - Multi-bit error correction scheme in multi-level memory storage system: A method, system, and computer software product for operating a memory cell collection. Memory cells in the collection store binary multi-bit values delimited by characteristic parameter bands of a characteristic parameter. In one embodiment, a comparing unit compares a retrieved count and a stored count for each binary multi-bit value.... Agent: Law Office Of Ido Tuchman (yor)
20090013232 - Method and arrangement for harq in wireless multi-carrier systems: The present invention relates to automatic repeat request (ARQ) in wireless communication systems wherein a coded message block is spread over a plurality of sub-carriers or components. According to the invention an equalizing HARQ method is introduced. The equalizing HARQ identifies (215) and retransmits (230) the most distorted parts of... Agent: Ericsson Inc.
20090013235 - Conditional decoding receiver: This invention relates to a wireless telecommunication system receiver, comprising a demodulator (220, 230) adapted to demodulate a signal received from a source via a transmission channel to provide an error correction code word in the form of flexible or hard values, a decoder (240) adapted to decode said code... Agent: Thelen LLP
20090013234 - Data storage with an outer block code and a stream-based inner code: Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based... Agent: Knobbe Martens Olson & Bear LLP
20090013233 - Error recovery storage along a nand-flash string: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects... Agent: Knobbe Martens Olson & Bear LLP
20090013236 - Method and apparatus for cascade encoding: A cascade encoding method and apparatus are applied to a handheld television system or other fields. The method includes the following: A. Reed-Solomon (RS) encoding is performed on inputted Medium Access Control (MAC) packets, and coded MAC packets are outputted; and B. Low density parity check code (LDPC) encoding is... Agent: Harness, Dickey & Pierce, P.L.C
20090013237 - Distributed processing ldpc (low density parity check) decoder: Distributed processing LDPC (Low Density Parity Check) decoder. A means is presented herein that includes an LDPC decoding architecture leveraging a distributed processing technique (e.g., daisy chain) to increase data throughput and reduce memory storage requirements. Routing congestion and critical path latency are also improved thereby. Each daisy chain includes... Agent: Garlick Harrison & Markison
20090013238 - Multi-code ldpc (low density parity check) decoder: Multi-code LDPC (Low Density Parity Check) decoder. Multiple LDPC coded signals can be decoded using hardware provisioned for a minimum requirement needed to decode each of the multiple LDPC coded signals. In embodiments where each LDPC matrix (e.g., employed to decode each LDPC coded signal) includes a common number of... Agent: Garlick Harrison & Markison
20090013239 - Ldpc (low density parity check) decoder employing distributed check and/or variable node architecture: LDPC (Low Density Parity Check) decoder employing distributed check into variable node architecture. A means of decoding processing is presented in which at least one portion of the check node processing functionality is actually integrated into the variable/bit node processing functionality (e.g., distributed check node embodiment). In alternative embodiments, at... Agent: Garlick Harrison & Markison
20090013240 - System for precoding parity bits to meet predetermined modulation constraints: A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined... Agent: Cesari And Mckenna, LLP01/01/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090006883 - Software error report analysis: Described herein is technology for, among other things, accessing error report information. It involves various techniques and tools for analyzing and interrelating failure data contained in error reports and thereby facilitating developers to more easily and quickly solve programming bugs. Numerous parameters may also be specified for selecting and searching... Agent: Microsoft Corporation
20090006884 - Automatically managing system downtime in a computer network: Embodiments are provided to automatically managing system downtime in a computer network. In one embodiment, an event is created in an application server to schedule a system downtime period for a web server. When the scheduled downtime occurs, the web server is automatically removed from the network and a downtime... Agent: Merchant & Gould (microsoft)
20090006885 - Heartbeat distribution that facilitates recovery in the event of a server failure during a user dialog: An exemplary method facilitates automatic recovery upon failure of a server in a network responsible for replying to user requests. Periodic heartbeat information is generated by a first group of servers responsible for replying to user requests. The heartbeat information provides an indication of the current operational functionality of the... Agent: Patti , Hewitt & Arezina LLC
20090006887 - System and method for addressing errors in a multiple-chip memory device: A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master... Agent: Posz Law Group, PLC
20090006886 - System and method for error correction and detection in a memory system: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090006888 - Fast primary cluster recovery: A cluster recovery process is implemented across a set of distributed archives, where each individual archive is a storage cluster of preferably symmetric nodes. Each node of a cluster typically executes an instance of an application that provides object-based storage of fixed content data and associated metadata. According to the... Agent: Law Office Of David H. Judson
20090006889 - I2c failure detection, correction, and masking: A method of operation of a computer system having a master and slave Inter-IC (I2C) bus network includes detecting and isolating an I2C bus failure, configuring a failed I2C bus as offline, reconfiguring a remaining I2C bus as a multi-mastered bus, and masking the failed I2C bus from operation until... Agent: John A. Griffiths, PLLC
20090006890 - Storage system and control method of storage system: Provided is a storage system superior in fault tolerance. This storage system is composed of a controller having a plurality of processors and other units. When an error occurs in any one of the components in the controller, the storage system cuts off an I/O path of the controller, specifies... Agent: Stanley P. Fisher Reed Smith LLP
20090006891 - Apparatus, system, and method for hard disk drive redundancy: An apparatus, system, and method are disclosed for hard disk drive redundancy. A demarcation module demarks a parity data block in each set of a specified number of data blocks on a hard disk drive. An association module associates a PBA of each un-demarked data block with a LBA. A... Agent: Kunzler & Mckenzie
20090006892 - Method and system to detect errors in computer systems by using state tracking: Disclosed are a method and system for detecting errors in a computer system including a processing unit to perform tasks to change items. The method comprises the steps of assigning a task control block to the processing unit, and using the task control block to keep track of items being... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006893 - Information processing apparatus, diagnosis method, and computer program product: A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical... Agent: Staas & Halsey LLP
20090006894 - Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan: An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006896 - Failure analysis apparatus: Relating with board numbers of the boards mounted with the logic circuits and mounted places on the boards and in relation to log information to be collected from the logic circuits, analysis information describing information to be processed when the log information is generated, information of a condition for which... Agent: Staas & Halsey LLP
20090006895 - Method for debugging reconfigurable architectures: A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.... Agent: Kenyon & Kenyon LLP
20090006897 - Automated service testing: A service test case generation and execution system is provided that automatically generates one or more test cases for the service according to a service definition associated with the service. The service definition can specify one or more methods available in the service and/or one or more parameters for the... Agent: Amin, Turocy & Calvin, LLP
20090006898 - Transmission of generic digital messages through a microprocessor monitoring circuit: Embodiments of the invention concern a method for transmitting digital messages through a microprocessor monitoring circuit of specific type and integrated to a microprocessor, each message including an identifier and consisting of several groups of successive and juxtaposed bits divided into segments. The method consists in successively transmitting segments associated... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.
20090006899 - Error correcting code with chip kill capability and power saving enhancement: A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006900 - System and method for providing a high fault tolerant memory system: A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090006901 - Control systems and method using a shared component actuator: In one embodiment, a control system supports an unlimited number of feedback control loops all sharing control of a component. A component performance rate or “speed” is used as a common metric for negotiating control of the component. Each control loop continuously monitors a system parameter it is tasked with... Agent: Ibm Corporation (ss/nc) C/o Streets & Steele
20090006902 - Methods, systems, and computer program products for reporting fru failures in storage device enclosures: Monitoring a plurality of field-replaceable units (FRUs) in an enclosure using two or more microcontroller-equipped power supplies to detect an FRU failure. Upon detection of an FRU failure, a first signal indicative of the failure is communicated from at least one of the microcontroller-equipped power supplies to one or more... Agent: Cantor Colburn LLP-ibm Poughkeepsie
20090006903 - Network alarm management: In a fault management system, a method and a converting unit for converting correlated sequences of network alarms into a high level language format are disclosed. The method comprises receiving episodic alarm sequence for the correlated sequences obtaining a high level language scheme, and converting the episodic alarm sequence using... Agent: Ericsson Inc.
20090006904 - Apparatus and method to check data integrity when handling data: An apparatus and method to check integrity when handling data. The method provides a storage array which includes a plurality of sectors. The method defines (N) data state identifiers and (N) parity state identifiers. The method receives a command to handle data, where that command designates a target sector. The... Agent: Dale F. Regelman Quarles & Brady, LLP
20090006905 - In situ register state error recovery and restart mechanism: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20090006906 - Method and system for encoding data using rate-compatible irregular ldpc codes based on edge growth and parity splitting: In a system for parity encoding data using a low density parity check (LDPC) code, a rate-compatible, irregular LDPC code is generated by extending a base code using a constrained edge growth operation and a parity splitting operation. The base code is a “daughter” code having an encoding rate higher... Agent: Mccormick, Paulding & Huber LLP
20090006907 - Method and apparatus for identification of program check errors indicating code with high potential for storage overlay: In a data processing system, in order to provide its operating system with a better mechanism to identify and track addressing errors with a high potential to cause a storage overlay, it is first determined whether or not, a program interrupt has occurred. It is next determined whether or not... Agent: Heslin Rothenberg Farley & Mesiti P.C.
20090006909 - Methods and apparatus for event logging in an information network: Methods and apparatus for logging, analysis, and reporting of events such as reboots in a client device (e.g., consumer premises equipment in a cable network) using applications. In one aspect, an improved event logging and monitoring system is provided within the device with which the application(s) can interface to record... Agent: Robert F. Gazdzinski, Esq. Gazdzinski & Associates
20090006908 - System and method for fault mapping of exceptions across programming models: A system and method for mapping exceptions from a first programming model to a second programming model is disclosed. The system comprises a first device operating a first programming model and a second device operating a second programming model. The first device sends an instruction to, or invokes the second... Agent: Kunzler & Mckenzie
20090006910 - Selective hybrid arq: Briefly, in accordance with one or more embodiments, a HARQ process may be selectively executed according to longer term and/or shorter term packet error rate statistics to be within one or more requirements of an application. As result, the number of retransmissions for the HARQ process may be reduced or... Agent: Cool Patent, P.C. C/o Intellevate
20090006911 - Data replacement processing method: A data replacement processing method is disclosed. In the present invention, buffering and decoding are not interrupted when a data block to be replaced is found. The data block to be replaced can be a defect or a remapped block. The data block to be replaced is not processed until... Agent: Madson & Austin
20090006912 - Semiconductor memory device having burn-in test mode and method for driving the same: A semiconductor memory device includes: a pattern selector configured to receive a first test control signal and a second test control signal to output a plurality of pattern selection signals and a selection end signal in response to an entry signal; a shifting controller configured to receive the first test... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090006913 - Semiconductor memory device having test address generating circuit and test method thereof: A semiconductor memory device includes a test address generating circuit configured on the device. The test address generating circuit generates a plurality of test addresses for a test of the semiconductor memory device in response to at least one externally applied test address generation signal. As a result, the number... Agent: Mills & Onello LLP
20090006914 - Semiconductor integrated circuit and method of detecting fail path thereof: Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period... Agent: Baker & Mckenzie LLP Patent Department
20090006915 - Apparatus and method for embedded boundary scan testing: Embedded boundary scan testing apparatus and methodologies are disclosed for testing processor-based circuit boards without processor intervention. A boundary scan controller is embedded in a circuit board along with a boundary scan chain having JTAG devices connected with an electrical circuit of the board. Upon power up, the boundary scan... Agent: Fay Sharpe/lucent
20090006916 - Method for cache correction using functional tests translated to fuse repair: A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect... Agent: Ibm Corporation (jvm)
20090006917 - Test circuit for supporting concurrent test mode in a semiconductor memory: A test circuit is capable of simultaneously performing various test modes. The test circuit includes a concurrent test mode controller for providing a plurality of decoding signals by receiving test mode input signals while test modes are being activated, and simultaneously providing the decoding signals if predetermined concurrent test mode... Agent: Baker & Mckenzie LLP Patent Department
20090006919 - Information appended-amendment method: An information appended-amendment method and system. The information appended-amendment method includes the steps of locating erroneous information sent by a sender, amending the sent erroneous information in accordance with the location of the sent erroneous information, sending error amendment information to a receiver, and amending the sent erroneous information received... Agent: Patterson, Thuente, Skaar & Christensen, P.A.
20090006918 - Method and apparatus for flash memory reclaim: Machine-readable media, methods, apparatus and system for flash memory reclaim are described. In some embodiment, a system may comprise a flash memory having a plurality of flash memory blocks, and a managing logic to manage a file operation on the flash memory. The managing logic may, during a foreground reclaim... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP
20090006920 - Bulk data transfer: This disclosure relates to network data communication. Some embodiments include initiating a network connection between an original source and an ultimate destination, transmitting a block of data from the original source to the ultimate destination on the network, requesting retransmission of lost blocks from the ultimate destination to the source... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20090006921 - Distributed checksum computation: Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.... Agent: Fsp LLC
20090006922 - Error correcting apparatus and error correcting method: According to one embodiment, an error correction parity bit sequence is generated for a data sequence obtained by adding a dummy symbol of a specific pattern to a digital information sequence modulated to convert into a form satisfying the request of a reproducing system. If the parity bit sequence meets... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20090006923 - Combined group ecc protection and subgroup parity protection: A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group... Agent: Scully, Scott, Murphy & Presser, P.C.
20090006924 - Fast decoding method for low density parity check (ldpc) code: A fast decoding method for low density parity check (LDPC) code obtains a block from the information received by a digital communication system, and computes the information of a bit node and a check node by a simplified method, and determine the actual value of the bit node from the... Agent: Hdsl
20090006925 - Feedback signaling error detection and checking in mimo wireless communication systems: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.... Agent: Volpe And Koenig, P.C. Dept. Icc
20090006926 - Device providing selective error correction data reception: In transmission systems using digital video broadcasting standards for handheld terminals data is transmitted in bursts. A decoder unit (25) is provided to correct errors in the data. An error amount determination unit (30) is provided to determine, when the amount of error correction data for error correction is sufficient... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090006928 - Method and apparatus for burst error detection and digital communication device: A digital communication device is provided for decoding a data stream to generate a receiver output. In the digital communication device, a burst error detector determines burst noise locations corresponding to the data stream according to an error-check equation and accordingly generates a burst error indicator. Thereafter, an inner decoder... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20090006927 - Method for providing unequal error protection to data packets in a burst transmission system: The present invention relates to a method for providing an equal error protection to data packets in a burst transmission system. The data packets are grouped based upon respective priority levels and error protection is provided to each group of data packets based upon the respective priority level. The error... Agent: Sughrue Mion, PLLC
20090006929 - Erased sector detection mechanisms: The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still be used as the number of corrupted... Agent: Davis Wright Tremaine LLP - Sandisk Corporation
20090006930 - Techniques for generating bit reliability information in the post processor: A detector generates a detected sequence, and a post processor generates probability values that indicate the likelihood of a plurality of error events in the detected sequence. The post processor partitions the values into first and second subsets. The post processor selects a first most likely value from the first... Agent: Steven J. Cahill/ Hitachi Gst
20090006931 - Techniques for generating bit reliability information in a post-processor using an error correction constraint: Techniques are provided that generate bit reliabilities for a detected sequence. A detector generates the detected sequence. According to one embodiment, a post-processor finds a first set of combinations of one or more error events in the detected sequence satisfying a complete set or a subset of error correction constraints... Agent: Steven J. Cahill/ Hitachi Gst
20090006932 - Device, system and method of modification of pci express packet digest: Device, system and method of modification of PCI Express packet digest. For example, an apparatus includes a credit-based flow control interconnect device to generate a credit-based flow control interconnect Transaction Layer Packet in which one or more bits of a digest portion carry non-ECRC data.... Agent: Ibm Corporation RochesterIPLaw Dept. 917
20090006935 - Methods, systems, and products for verifying integrity of web-server served content: Methods, systems, and products are disclosed for verifying the integrity of web server content. A request for a Uniform Resource Locator is received, with the request originating from a referring Uniform Resource Locator. A response to the request is communicated. The requested Uniform Resource Locator is stored along with the... Agent: Scott P. Zimmerman, PLLC
20090006933 - Server directory schema comparator: The embodiments generally relate to systems and methods for determining changes in a directory schema. In embodiments, directory changes are recorded in a change log. The change log may have one or more entries. A determination is made as to which change log entries should be retrieved. Once retrieved, the... Agent: Merchant & Gould (microsoft)
20090006934 - Triggering diagnostic operations within a data processing apparatus: A data processing apparatus 2 is provided including diagnostic mechanism 10, 12 and comparator circuitry 8. The comparator circuitry 8 is responsive to a signal indicative of execution of a block of program instructions to trigger any watchpoints or watch ranges within that block of program instructions. The relative ordering... Agent: Nixon & Vanderhye, PCPrevious industry: Electrical computers and digital processing systems: support
Next industry: Data processing: presentation processing of document
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