Error detection/correction and fault detection/recovery inventions 09/08

20080235531 - Apparatus and computer program product for testing ability to recover from cache directory errors: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080235532 - Reducing overpolling of data in a data processing system: A computer implemented method, apparatus, and computer usable program code for reducing overpolled data in a data processing system is provided. A controller identifies a set of redundant measurements in a cycle. The controller then identifies a number of measurements repeated in the set of redundant measurements. The controller the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080235533 - Fall over method through disk take over and computer system having failover function: When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the servers boot an operation system from the external disk device, task processing is taken over from the primary server to a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080235534 - Integrity protection in data processing systems: A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading... Agent: Cantor Colburn, LLP - IBM Arc Division

20080235535 - Writing data processing control apparatus, writing method, and writing apparatus: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080235536 - System and method of preventing a web browser plug-in module from generating a failure: The present invention improves the stability of a Web browser by identifying plug-in modules that cause failures. Data in memory at the time of a failure is analyzed, and a failure signature is generated. The failure signature is compared to a database of known failure signatures so that the source... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20080235537 - System and method for electronic testing of multiple memory devices: A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory... Agent: Gregory W. Osterloth Holland & Hart, LLP

20080235538 - Techniques for generating a trace stream for a data processing apparatus: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable... Agent: Nixon & Vanderhye P.C.

20080235539 - Test apparatus and electronic device: There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction stream, a transfer section that reads... Agent: Jianq Chyun Intellectual Property Office

20080235540 - Test apparatus and electronic device: A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from... Agent: Jianq Chyun Intellectual Property Office

20080235541 - Method for testing a word line failure: A method for testing a word line failure of a memory device is provided. The memory device comprises a memory cell with a transistor connecting to a word line and a bit line. The method comprises driving the word line to a predetermined voltage level by a word line driver... Agent: Jianq Chyun Intellectual Property Office

20080235543 - Conversion device, conversion method, program, and recording medium: Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device 400 converts a test vector set corresponding to... Agent: Amin, Turocy & Calvin, LLP

20080235542 - Electronic testing device for memory devices and related methods: Described are an electronic testing device for memory devices and related methods. The testing device, comprises a memory controller managing a transfer of data and a controller buffer disposed within the memory controller. The controller buffer transfers data between the memory controller and a memory module. The memory controller tests... Agent: Gregory W. Osterloth Holland & Hart, LLP

20080235544 - Built-in self-test of integrated circuits using selectable weighting of test patterns: A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides... Agent: Klarquist Sparkman, LLP

20080235545 - Re-using production test scan paths for system test of an integrated circuit: Mission circuitry provided to implement desired data processing operations in an integrated circuit apparatus is tested by using a plurality of scan paths to subject the mission circuitry to production testing before the integrated circuit apparatus is deployed in a mission environment. The plurality of scan paths are re-used to... Agent: Texas Instruments Incorporated

20080235546 - System and method for detecting a work status of a computer system: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang

20080235547 - Self-test output for high-density bist: A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/FAIL signal from each embedded memory... Agent: Texas Instruments Incorporated

20080235549 - Test apparatus and electronic device: There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the... Agent: Jianq Chyun Intellectual Property Office

20080235550 - Test apparatus and electronic device: There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction... Agent: Jianq Chyun Intellectual Property Office

20080235548 - Test apparatus, and electronic device: A test apparatus is provided. The test apparatus includes: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from... Agent: Jianq Chyun Intellectual Property Office

20080235551 - Error correction circuit and method thereof: An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080235553 - Data link layer tunneling technique for high-speed data in a noisy wireless environment: In accordance with the invention, a data link layer tunneling technique is disclosed for improving the throughput of high speed data in noisy wireless environments. The method for recovering lost frames transmitted between a packet sending unit and a packet receiving unit in a data communications system, and generally comprises... Agent: At&t Corp.

20080235552 - Packet-asynchronous hybrid-arq: Aspects described a low receiver complexity approach for reliable packet decoding when Hybrid ARQ protocol is employed with persistent assignment and potentially an erasure sequence transmission. Multiple hypotheses packet decoding performance is achieved while mitigating multiple hypotheses receiver complexity. A reference number is utilized to perform hypotheses. The reference number... Agent: Qualcomm Incorporated

20080235554 - Device and method for improved lost frame concealment: Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more... Agent: Bereskin And Parr

20080235555 - Method, apparatus, and system for retention-time control and error management in a cache system comprising dynamic storage: Methods, systems, and apparatuses are provided for operating a cache comprising dynamic storage having an array of cells. At a refresh interval, the array of cells of the cache is refreshed. A determination is made whether an error is found in the cache at the refresh interval. If no error... Agent: Cantor Colburn LLP-ibm Yorktown

20080235556 - Reverse concatenation for product codes: A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into... Agent: Law Office Of Dan Shifrin

20080235557 - Semiconductor memory device: A semiconductor memory device includes: a plurality of error correction code (ECC) groups, each ECC group including plural data configured to be read from and written to the semiconductor memory device and plural parity data configured to correct an error of the plural data, wherein at least one of the... Agent: Mcdermott Will & Emery LLP

20080235558 - Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (crc) address error detect for use in a 76-bit memory module: A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits... Agent: Stuart T Auvinen

20080235559 - Strengthening parity check bit protection for array-like ldpc codes: An LDPC parity check matrix originated using an array code provides more protection against errors for parity bits 1 through 1-p, which can, during decoding, allow faster convergence to a higher LLR value for those bits as well as higher overall reliability of other parity check bits. The present parity... Agent: Morrison & Foerster LLP

20080235560 - Flash error correction: A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in software. In one embodiment, the coding unit is capable receiving... Agent: Greenberg Traurig LLP (la)

20080235561 - Methodology and apparatus for soft-information detection and ldpc decoding on an isi channel: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at... Agent: Morrison & Foerster LLP

20080235562 - Reverse concatenation for product codes: Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array... Agent: Law Office Of Dan Shifrin

20080229139 - Space-and time- adaptive nonblocking algorithms: We explore techniques for designing nonblocking algorithms that do not require advance knowledge of the number of processes that participate, whose time complexity and space consumption both adapt to various measures, rather than being based on predefined worst-case scenarios, and that cannot be prevented from future memory reclamation by process... Agent: Mhkkg/sun

20080229140 - System and method of disaster recovery: In a DR system, from the viewpoint of device cost, when search is not carried out, a physical application where log recovery is available by inexpensive DB appliance server is adopted. Further, a local mirror operation at a secondary site is not carried out. Furthermore, from the viewpoint of operation,... Agent: Stanley P. Fisher Reed Smith LLP

20080229141 - Debugging method: The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the... Agent: Birch Stewart Kolasch & Birch

20080229142 - Self-service recovery of application data: Self-service recovery of application data. A list of recoverable objects for the application is generated in response to the receipt of a request for an application recovery from a user. The list of recoverable objects for the application is sent to the user. A selected recoverable object from the user... Agent: Senniger Powers LLP (msft)

20080229143 - Management of available circuits to repair defective circuits: Systems and methods are provided for management of available, possibly redundant, circuits, in particular memory circuits, possibly found in defective processors, to repair defective circuits, in particular memory circuits, such as shared memory, wherein functional memory of a potentially-deactivated available circuit may be activated and used in place of dysfunctional... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20080229144 - Flexible row redundancy system: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row... Agent: The Farrell Law Firm, P.C.

20080229145 - Method and system for soft error recovery during processor execution: A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting... Agent: Law Office Of Ido Tuchman (yor)

20080229146 - High availability multi-processor system: A method and system are provided for enabling replacement of a failed processor without requiring redundancy of hardware. The system is a multiprocessing computer system that includes one or more processor chips. Each processor chip may include one or more logical processors. During system initialization, one or more logical processors... Agent: Lieberman & Brandsdorfer, LLC

20080229147 - Data protection system: The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors.... Agent: Jagtiani + Guttag

20080229148 - Enhanced error identification with disk array parity checking: When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080229149 - Remote testing of computer devices: In embodiments of the present invention improved capabilities are described for a method and system of software testing that may used on a computer network, the network may include a plurality of computer devices; may use a network management system to transmit test data over the computer network to at... Agent: Strategic Patents P.C..

20080229150 - Address translation system for use in a simulation environment: Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of the system definition file... Agent: Merchant & Gould PC

20080229151 - Electronic control unit: An ECU that controls an engine of a vehicle includes a MPU and an IC that monitors the operation of the MPU. The MPU is programmed to execute a verification result check and test selection function for selecting a test for verifying the function of the MPU. The MPU runs... Agent: Nixon & Vanderhye, PC

20080229152 - On-chip debug emulator, debugging method, and microcomputer: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080229153 - System and method of network error analysis: Systems and methods for network analysis are provided. A system may include an input to receive communication reports from a plurality of end terminals of a multicast network. The system may also include a memory including multicast network topology data. The system may also include logic to determine a source... Agent: Toler Law Group

20080229155 - Enhanced error identification with disk array parity checking: When parity checking in a disk array such as a RAID-6 system determines data and parity information is unsynchronized, additional calculations are performed to determine whether the error may be attributed to faulty data on a disk drive or to a more systemic problem such as a faulty controller. In... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20080229154 - Self-referencing redundancy scheme for a content addressable memory: A self-referencing redundancy scheme in a content addressable memory may use a faulty bit table, populated during manufacturing, to indicate, not only the address of all the defective memory locations, but also the data which they should hold. Then, during read out, a read out state machine may access the... Agent: Trop Pruner & Hu, PC

20080229156 - Method and apparatus for hardware awareness of data types: A method, apparatus, and computer instructions in a processor for associating a data type with a memory location. The type is associated with a location by means of metadata that is generated and manipulated by hardware instructions that are typically generated by a compiler as it generates the other instructions... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080229157 - Performing externally assisted calls in a heterogeneous processing complex: A mechanism is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the input and output parameters for the function... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080229158 - Restoration device for bios stall failures and method and computer program product for the same: A restoration device for restoring a system when the BIOS falls in a stall failure includes a first watchdog timer and a second watchdog timer, a setter for setting timer values respectively in the first watchdog timer and in the second watchdog timer, a suspender for suspending the decrement of... Agent: Nec Corporation Of America

20080229160 - Controlling software failure data reporting and responses: User input defines transmission filter rules to be met when sending an error report to a support provider. User input also defines collection filter rules to be met when including failure data within an error report. Error reports corresponding to crash failures at clients are filtered with the transmission filter... Agent: Workman Nydegger/microsoft

20080229159 - Failsafe computer support assistant: A computer running a host operating system in a host virtual machine includes a support operating system running in a support virtual machine. A support module running in the support operating system identifies and remediates defects associated with the host operating system. A monitoring module running in the support operating... Agent: Symantec/ Fenwick Silicon Valley Center

20080229161 - Memory products and manufacturing methods thereof: Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if... Agent: Thomas, Kayden, Horstemeyer & Risley LLP

20080229162 - Test apparatus and test method: Provided is a test apparatus including: test signal supply sections supplying a test signal writing test data to the connected memory under test, to a terminal of the memory; terminal correspondence determination sections outputting a terminal unit determination result indicating whether test data from the connected terminal matches an expected... Agent: Jianq Chyun Intellectual Property Office

20080229163 - Test apparatus, test method and machine readable medium storing a program therefor: The present invention provides a test apparatus that tests a plurality of memories under test. The test apparatus includes a data input-output section that gives and receives data to and from data input-output terminals of the plurality of memories under test, a test data supplying section that parallel supplies test... Agent: Jianq Chyun Intellectual Property Office

20080229164 - Memory card and memory controller: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at... Agent: Miles & Stockbridge PC

20080229165 - Address translation system for use in a simulation environment: Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of virtual addresses required for execution of the system definition file... Agent: Merchant & Gould PC

20080229166 - Accelerating test, debug and failure analysis of a multiprocessor device: A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs,... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080229167 - Packet data transmitting method and mobile communication system using the same: A packet data transmitting method and mobile communication system using the same enables transmission of common ACK/NACK information from each sector of a base station to a user entity in softer handover. The method includes receiving via at least one of the plurality of sectors a data packet from the... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20080229168 - Multi-antenna transmitting apparatus, multi-antenna receiving apparatus, and data re-transmitting method: In a multi-antenna communication system using LDPC codes, a simple method is used to effectively improve the received quality by performing a retransmittal of less data without restricting applicable LDPC codes. In a case of a non-retransmittal, a multi-antenna transmitting apparatus (100) transmits, from two antennas (114A, 114B) , LDPC... Agent: Dickinson Wright PLLC

20080229169 - Data recovery circuit: A data recovery circuit for recovering data from a parity error without entirely rewriting the data. A write circuit is connected to memory regions including an actual data region and a copy region. A first parity generation circuit writes actual data with even parity to the actual data region. A... Agent: Arent Fox LLP

20080229172 - High rate turbo encoder and recoder for product codes: The invention relates to a Method of decoding a matrix built from concatenated codes, corresponding to at least two elementary codes, with uniform interleaving, this matrix having n1 lines, n2 columns and n1*n2 symbols, characterized in that the method comprises a process of all the lines- and columns-vectors of the... Agent: Alston & Bird LLP

20080229170 - Parallel arrangement of serial concatenated convolutional code decoders with optimized organization of data for efficient use of memory resources: A decoding system (100) is provided. The decoding system is comprised of two or more serial concatenated convolution code (SCCC) decoders (1021-102N) operating in parallel. The SCCC decoders are configured to concurrently decode codebocks which have been encoded using a convolutional code. The decoding system is also comprised of a... Agent: Harris Corporation C/o Darby & Darby PC

20080229171 - Serial concatenated convolutional code decoder: A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory (102), one or more processing loop modules (120), and an output buffer memory (112). Each processing loop module is comprised of a permutation module (110), inner decoding engines (2021-202N); a depermutation... Agent: Harris Corporation C/o Darby & Darby PC

20080229173 - Method and apparatus for error code correction: The present invention is related to a method and apparatus for ECC (error code correction). The method of ECC includes a first directional first decoding, a first directional second decoding, a second directional first decoding, a second directional second decoding, wherein the error tolerant ability of first directional second decoding... Agent: Perkins Coie LLP Patent-sea

20080229174 - Error detection in a communications link: An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection... Agent: Zagorin O'brien Graham LLP

20080229175 - Method and apparatus for providing help upon user's wrong button manipulation: A method and apparatus for providing help upon a user's wrong button manipulation, the method including: obtaining information on a user's button manipulation; checking whether an error pattern is detected in the button manipulation, using the information on button manipulation; and if the error pattern is detected, providing help information... Agent: Sughrue Mion, PLLC

20080229176 - Method for fast ecc memory testing by software including ecc check byte: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20080229177 - Channel quality index feedback reduction for broadband systems: A system and methodology are disclosed for exploiting channel correlation in time and/or frequency to reduce CQI feedback in wireless communications systems. By compressing CQI feedback at the receiver to reduce redundancy in CQI feedback information that results from the channel correlation, the average feedback rate is reduced. In various... Agent: Hamilton & Terrile, LLP

20080229178 - Radio tag communication apparatus: A signal transmitted from a radio tag is received, and an I-signal and a Q-signal are generated from the received signal. The I-signal and Q-signal are decoded, and a decoding error of the decoded data to be detected is detected and a decoded data error of the decoded data is... Agent: Harness, Dickey & Pierce, P.L.C

20080229179 - Data access detection: Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080222446 - Status display control apparatus: an apparatus comprises a data display unit which causes a display device to output display data that indicates a drawing screen complying with the display request, a reliability decision unit which decides a legality of a transmission source of the display request, and which makes an output request for information... Agent: Greer, Burns & Crain

20080222447 - Prevention of frame duplication in interconnected ring networks: An attribute is extracted from the respective copies of the data packet at each of the interconnect nodes, and a predefined mapping function is applied to the extracted attribute so as to select a single interconnect node for forwarding the data packet to the second ring network. A single copy... Agent: Darby & Darby P.c.

20080222448 - System, method and program product for recovering from a failure: System, method and computer program product for recovering from a failure of a computing device. Start up of a first component of the device is monitored and a determination is made whether the first component has started successfully. If so, a second, higher level component of the device is started.... Agent: Ibm Corporation

20080222449 - System and method for information handling system error recovery: An information handling system recovers from memory errors associated with a memory unit that supports operation of an SMI handler by using another memory unit to support operation of the SMI handler. For example, if an SMI handler detects an error associated with a DIMM that supports operation of the... Agent: Hamilton & Terrile, LLP

20080222450 - Zero-penalty raid controller memory leak detection and isolation method and system utilizing sequence numbers: A method and system for detecting and isolating memory leak in RAID controllers utilizing sequence numbers. The system monitors whether the count of un-freed memory blocks for a sequence number (SN) zone (after a start-of-day SOD operation, but smaller than the current sequence number zone) is not eventually decremented to... Agent: Lsi Corporation

20080222451 - Active spam testing system: A method and system for introducing spam into a search engine for testing purposes is provided. An active spam testing system receives from a tester a specification of spam that is to be introduced into the search engine for testing purposes. The testing system may then generate auxiliary data structures... Agent: Perkins Coie LLP/msft

20080222452 - Test apparatus for testing a circuit unit: Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold unit for sampling at least one voltage value of an output signal output from the circuit unit and... Agent: Dickstein Shapiro LLP

20080222453 - Method for integrating event-related information and trace information: A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the selected points. As such, the event information and trace information... Agent: Cypress C/o Murabito, Hao & Barnes LLP

20080222454 - Program test system: An improved automated software testing system provides the ability to generate and reuse test cases over multiple platforms. Keywords and natural language are used in test case creation, simplifying the process for non-technical business users. Business users can write test cases without scripts. Test cases can be generated even before... Agent: Carstens & Cahoon, LLP

20080222455 - Reporting diagnostic information for code of an application program interface: A technology for reporting diagnostic information for code of an application program interface is disclosed. In one method approach, diagnostic information for a line of code in a file associated with an application program interface is received. The diagnostic information includes a designation of the line of code. The diagnostic... Agent: Microsoft Corporation

20080222456 - Method and system for implementing dependency aware first failure data capture: A method and system for implementing failure data capture in a system having multiple components and where the components have processing dependencies with respect to other of the components. Trace data is collected for a first of the components using failure data capture data tracing. In response to detecting a... Agent: Dillon & Yudell LLP

20080222457 - Electronic data processing system and method for monitoring the functionality thereof: A method for monitoring of the functionality of an EDP system that is monitored in portions thereof by respectively associated agents that are designed to evaluate errors and to send error messages should increase the operating security in an EDP system. Each agent is monitored by a simulated error being... Agent: Schiff Hardin, LLP Patent Department

20080222458 - Data protecting method of storage device: A data protection method of a storage device, applied in a computer having a storage device, is provided. The storage device is consisted of a plurality of blocks. The method includes the following steps. When a data containing a plurality of bit data is stored in the storage device in... Agent: J C Patents, Inc.

20080222459 - Methods, systems, and products for verifying integrity of web-server served content: Methods, systems, and products are disclosed for verifying the integrity of web server content. A client-side integrity verification of a web page communicated from a web server to a client computer is received. A server-side error in the web page is received from the web server. The results of the... Agent: Scott P. Zimmerman

20080222460 - Memory test circuit: A memory test circuit is provided, comprising: an output data selector configured to receive the plurality of read data bits and output a fraction of the plurality of read data bits as a plurality of fractional data bits; and a control circuit configured to select a set of bit positions... Agent: Posz Law Group, Plc

20080222461 - Apparatus and method for calculating error metrics in a digital communication system: A method and an apparatus for calculating an error metric in a digital communication receiver. In the receiver, an input data stream is used to generate at least one input bit stream. The combinational logic unit performs an error-check operation on delayed and current bits of the input bit stream... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080222462 - Image forming system, image processing apparatus, determination device, and image processing method: An object of the present invention is to provide an image forming system, an image processing apparatus, a determination device, and image processing method that are capable of preventing users' convenience from reducing even when an image forming apparatus prints a coded image with a low print precision. A first... Agent: Fitzpatrick Cella Harper & Scinto

20080222463 - Apparatus, method and product for testing communications components: An apparatus, method and product for independently testing communications components are disclosed. A testing apparatus is provided that has a test control component which includes an input configured to receive a test script, an upper interface coupling and a lower upper interface coupling. In operation, a protocol stack component to... Agent: Volpe And Koenig, P.c. Dept. Icc

20080222464 - Structure for system for and method of performing high speed memory diagnostics via built-in-self-test: A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST... Agent: Downs Rachlin Martin Pllc

20080222465 - Checkpointing user design states in a configurable ic: Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state... Agent: Adeli & Tollen, LLP

20080222466 - Meeting point thread characterization: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic... Agent: Kraguljac & Kalnay, Llc

20080222467 - Method of controlling a test mode of circuit: A test vector decode circuit includes a lockout circuit to prevent inadvertent latching of output vectors. The test vector decode circuit is driven by an additional output vector from the test vector decode circuit. The additional output vector, as well as the other output vectors, undergo at least one latching.... Agent: Trask Britt, P.c./ Micron Technology

20080222468 - Method and dual interlocked storage cell latch for implementing enhanced testability: A method and a Dual Interlocked Storage Cell (DICE) latch implementing enhanced testability includes an L1 latch and an L2 latch coupled to the L1 latch. Each L1 latch and each L2 latch includes redundant latch structures. A separate output is provided with the redundant L2 latch. The DICE latch... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080222469 - Method and dual interlocked storage cell latch for implementing enhanced testability: A method and Dual Interlocked Storage Cell (DICE) latch for implementing enhanced testability, and a design structure on which the subject DICE latch circuit resides are provided. DICE latch includes an L1 latch and an L2 latch are coupled to the L1 latch. Each L1 latch and each L2 latch... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080222470 - Scan test circuit, semiconductor integrated circuit and scan enable signal time control circuit: A SCAN test circuit for giving a semiconductor integration circuit a scan test includes a scan enable signal generating device that generates scan enable signals based on a scan enable external input signal, a clock generator that generate launch and capture clocks for collectively detecting a delay malfunction at a... Agent: Dickstein Shapiro LLP

20080222471 - Circuitry to prevent peak power problems during scan shift: In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals... Agent: Silicon Image/bstz Blakely Sokoloff Taylor & Zafman LLP

20080222472 - Method for automatic test pattern generation for one test constraint at a time: A method for automatically generating test patterns for an IC device includes initially generating a subset of available test patterns according to each of a plurality of test constraints for the IC device, determining an incremental amount of total test coverage of the IC device attributable to each of the... Agent: Cantor Colburn LLP-ibm Burlington

20080222473 - Test pattern generating device and test pattern generating method: An apparatus for LSI test has a risk place extraction unit supplied with a design information of the LSI to specify a place by estimating an error in LSI operation based on the design information of the LSI to write the place on a risk place list, and a pattern... Agent: Young & Thompson

20080222474 - Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product: In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle... Agent: Staas & Halsey LLP

20080222475 - Method and apparatus for compensating for packet loss: A client, system, and method are provided to compensate for the loss of multicast data packets. When data packets transmitted to two or more clients are lost, a client determines whether compensation for the data packet is needed; if so, the client requests other clients to compensate, receives a compensated... Agent: Sughrue Mion, Pllc

20080222476 - Utilizing a network to correct flawed media data: A system and method of utilizing a network to correct flawed media data. The media device includes a processor, a memory, a network adapter, a removable media interface, an error-correction module, and a communication module. The network device enables the media device to connect to the network and server. The... Agent: Dillon & Yudell LLP

20080222477 - Communication system using communication network and communication method: A communication system for guaranteeing only one each of two processing operations, correlated with each other and executed on different devices. A server has a unit which, on receipt of a first processing request, with identification information, executes this processing only once for one item of the identification, and a... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080222479 - Method and apparatus for handling reordered data packets: The present invention provides a method and apparatus for handling reordered data packets. A method comprises receiving a data packet and determining if the data packet is received out of order. The method further comprises delaying transmission of an acknowledgement indicating that a data packet is missing in response to... Agent: Ibm Corporation (wma) C/o Williams, Morgan & Amerson, P.c.

20080222478 - Retransmission method and wireless communication system: Disclosed herewith is a communication method employed for a wireless communication system. The method controls retransmission in case where wireless communication between a data transmitter and a data receiver in the system is unstable, thereby suppressing increasing of a communication delay time that might otherwise be caused by the retransmission... Agent: Stanley P. Fisher Reed Smith LLP

20080222480 - Erasure-resilient codes having multiple protection groups: A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and... Agent: Microsoft Corporation C/o Lyon & Harr, LLP

20080222481 - Multiple protection group codes having maximally recoverable property: A multiple protection group (MPG) erasure-resilient coding method for constructing MPG codes for encoding and decoding data. The MPG codes constructed herein protect data chunks of data in multiple protection groups and subgroups. In general, the MPG erasure-resilient codes are constructed by locating data chunks into multiple protection groups and... Agent: Microsoft Corporation C/o Lyon & Harr, LLP

20080222482 - Transmitter and receiver: There is provided with a transmitter including: an input unit configured to input a data symbol sequence; a block generator configured to sequentially generate data blocks each including a plurality of data symbols by using the data symbol sequence; an addition unit configured to add a duplicate of h data... Agent: Amin, Turocy & Calvin, LLP

20080222483 - Method, system, and apparatus for distributed decoding during prolonged refresh: Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However,... Agent: Trask Britt, P.c./ Micron Technology

20080222484 - Single engine turbo decoder with single frame size buffer for interleaving/deinterleaving: A method and apparatus for decoding and de-interleaving a received encoded and interleaved signal, the method employing and the apparatus including a single decoder coupled to a common buffer, the common buffer size equal to a frame of the received signal and the method further employing, and the apparatus further... Agent: Jaquez & Associates

20080222485 - Error correction methods and apparatus for mobile broadcast services: An apparatus and method of an outer Forward Error Correcting (FEC) code for a mobile broadcast service based on TD-SCDMA network is disclosed.... Agent: Perkins Coie LLP Patent-sea

20080222486 - Methods and apparatus for encoding and decoding low density parity check (ldpc) codes: A novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph are provided. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed... Agent: Qualcomm Incorporated

20080222488 - method of computing partial crcs: Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and... Agent: Greenblum & Bernstein, P.L.C

20080222489 - Apparatus for implementing processor bus speculative data completion: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080222487 - Quantum key distribution mehtod and communication apparatus: An error of reception data is corrected using check matrixes for an “Irregular-LDPC code” that are definite and have stable characteristics and a part of shared information is discarded according to error correction information opened to the public. A parity check matrix corresponding to a specific coding rate is extracted... Agent: Birch Stewart Kolasch & Birch

20080222491 - Flash memory system for improving read performance and read method thereof: A method of transmitting data from a flash memory device to a host includes: detecting whether the data includes an error or not; performing an error correction operation for correcting the data having the error when the error exists in the data; and sequentially storing the data having the error... Agent: F. Chau & Associates, Llc

20080222490 - Method, apparatus, and system for dynamic ecc code rate adjustment: A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.... Agent: Trop, Pruner & Hu, P.c.

20080222492 - Data protection system: The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors.... Agent: Jagtiani + Guttag

20080222493 - Method and system for control loop response time optimization: A method and system for optimizing a response time of a monitoring loop with forward error correction. Characteristics of a fiber optic communications channel are adjusted based on the number of errors corrected in the FEC decoder. An adaptive BER is calculated much faster by using a signal from an... Agent: Arent Fox LLP

20080222494 - Communication apparatus, communication method and computer readable medium: There is provided with a communication method including: attempting to receive a media packet from a network; storing a received media packet in a first buffering unit; receiving an FEC packet including redundant data to recover a lost media packet and information which specifies a plurality of media packets associated... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080222495 - Data storage apparatus: A data storage apparatus with multiple-modes for error detecting and correcting is disclosed, comprising a controller, a data storage media, and a multiple-modes error detecting and correcting device, wherein the multiple-modes error detecting and correcting device is provided within the controller, wherein the controller further comprises a ECC register electrically... Agent: Rosenberg, Klein & Lee

20080222496 - Secure protection of biometric templates: This invention relates to methods and devices for verifying the identity of a person based on a sequence of feature components extracted from a biometric sample. Thereafter, the feature components are quantized and assigned a data bit sequence in such a way that adjacent quantization intervals have a Hamming distance... Agent: Philips Intellectual Property & Standards

20080222497 - Decoding method and decoding circuit: An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing signal having a code sequence having a decoding unit generating... Agent: Foley And Lardner LLP Suite 500

20080222498 - Sequential decoding method and apparatus thereof: A sequential decoding method and a decoding apparatus are provided. According to the method, an open stack is adopted for storing a plurality of paths. When the codeword generated by an internal decoder in the decoding apparatus is incorrect, a codeword is generated again by using the paths stored in... Agent: Jianq Chyun Intellectual Property Office

20080222499 - Cyclic comparison method for low-density parity-check decoder: The present invention discloses a cyclic comparison method for an LDPC decoder, which applies to the comparators used in an LDPC decoder. According to the cyclic comparison algorithm of the present invention, the nth element of the input k elements, wherein n=1, . . . , k, is sequentially removed... Agent: Sinorica, Llc

20080222500 - Data relay apparatus, data relay method and data relay integrated circuit: According to an aspect of an embodiment, a data relay apparatus for transferring writing data and an associated check code sequentially sent from a host into a memory device, said writing data containing a plurality of fields classified by the kind of information in said writing data, comprising: a memory... Agent: Staas & Halsey LLP

20080222501 - Analyzing test case failures: Apparatus and method for categorizing test failures are disclosed. In one embodiment, a data set of a current test failure is compared with the data sets of historical test failures to result in a set of correspondence values. The current test failure is categorized with respect to the historical test... Agent: Lee & Hayes Pllc

20080222502 - Error determining apparatus and method: An error determining apparatus includes an Error Detection Code (EDC) error detector to detect an EDC error of data read from an optical disk, a continuity error detector to detect a continuity error of a currently decoded address by comparing the currently decoded address and a previously decoded address, and... Agent: Stein, Mcewen & Bui, LLP

20080215909 - Apparatus, system, and method for transactional peer recovery in a data sharing clustering computer system: The invention provides an apparatus, system, and method for cluster-wide peer recovery in the event of a computer failure. A failure of a first computer is detected and a recovery module is registered as the first computer. In one embodiment, the recovery module is a peer computer. The recovery module... Agent: Kunzler & Mckenzie

20080215910 - High-availability networking with intelligent failover: Methods and systems for maintaining high-availability in a computer network using intelligent failover are presented. In a network switch running an OSI model layer-2 or higher protocol on its external links, the protocol state information is monitored to determine failover status of the link to avoid identifying external link failures... Agent: Guerin & Rodriguez, LLP

20080215911 - Storage device capable of meeting the reliability and a building and data writing method thereof: A storage device capable of meeting the reliability has a storage capacity and the reliability of the storage device is defined. The storage device includes at least one first storage unit, at least one second storage unit, and a control unit. The first storage unit forms the storage capacity of... Agent: Rosenberg, Klein & Lee

20080215912 - System and method for raid recovery arbitration in shared disk applications: A RAID controller is provided for each host sharing a RAID. Each RAID controller can determine whether another host is sharing the RAID and assume a master or slave status with respect to rebuild operations for the shared disk. The master controller may then manage any rebuild operations on rebuild... Agent: Baker Botts, LLP

20080215913 - Information processing system and information processing method: An anomaly detector detects anomaly of a first device. A second device reset part, in case that anomaly has been detected by the anomaly detector, resets a second device. A first device reset part, in case that anomaly has been detected by the anomaly detector, resets a first device. Further,... Agent: Edwards Angell Palmer & Dodge LLP

20080215914 - Self-reparable semiconductor and method thereof: A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched... Agent: Harness, Dickey & Pierce P.L.C

20080215915 - mechanism to change firmware in a high availability single processor system: A “high availability” system comprises multiple switches under the control of a control processor (“CP”). The firmware executing on the processor can be changed when desired. Consistent with the high availability nature of the system (i.e., minimal down time), a single CP system implements a firmware change by loading new... Agent: Conley Rose, P.C. David A. Rose

20080215916 - Template based parallel checkpointing in a massively parallel computer system: A method and apparatus for a template based parallel checkpoint save for a massively parallel super computer system using a parallel variation of the rsync protocol, and network broadcast. In preferred embodiments, the checkpoint data for each node is compared to a template checkpoint file that resides in the storage... Agent: Martin & Associates, LLC

20080215917 - Synchronizing cross checked processors during initialization by miscompare: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent... Agent: International Business Machines Corporation

20080215918 - Method for monitoring server sub-system health: A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a server's sub-systems and deployed applications. The SHM may make health check inquiries to server sub-systems periodically or based on external... Agent: Fliesler Meyer LLP

20080215919 - Method and system for verifying information handling system hardware component failure diagnosis: Hardware component failure diagnosis of an information handling system is verified with a hardware diagnostics code generated by a diagnostics module integrated with an information handling system and sent from the information handling system to a diagnostics engine of a service center. The hardware diagnostics code includes a unique identifier... Agent: Hamilton & Terrile, LLP

20080215921 - Method, system and computer program for performing regression tests based on test case effectiveness: A method (400) for performing a regression test on a software application is proposed. The regression test involves the execution (481-463) of a subset of selected test cases on the software application (among all the ones being available). In the proposed solution, the selection of the test cases to be... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080215920 - Program code trace signature: A processor generates a signature value indicating a sequence of executed instructions, and the signature value is compared to signature values calculated for two or more possible sequences of executed instructions to determine which instruction sequence was executed. The signature is generated via a signature generator during program execution, and... Agent: Schwegman, Lundberg & Woessner / Infineon

20080215923 - Design structure for task based debugger (transaction-event -job-trigger): Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080215922 - Method and system for diagnosing an application: A system, method and program enabling users to diagnose applications easily without affecting the operating performance of the application server, optimizing the log mechanism based on the integrated development environment. The method includes running the application in a main running environment and at least one shadow environment, the shadow environment... Agent: Anne Vachon Dougherty

20080215924 - Method for performing a corrective action upon a sub-system: A server self health monitor (SHM) system monitors the health of the server it resides on. The health of a server is determined by the health of all of a server's sub-systems and deployed applications. The SHM may make health check inquiries to server sub-systems periodically or based on external... Agent: Fliesler Meyer LLP

20080215925 - Distributed fault injection mechanism: Methods and systems are provided for testing distributed computer applications using finite state machines. A finite state machine definition for use in a distributed computer system is combined with the fault injections definitions contained within a fault injection campaign that is created for testing the computer application employing that finite... Agent: George A. Willinghan, Iii August Law Group, LLC

20080215926 - Dubug by a communication device: An embodiment of the present invention includes a communication system configured to conform to SATA or SAS standards and causing communication between one or more hosts and a SATA device. The communication system includes a communication device adapted to generate debug information incorporated through one or more links using an... Agent: Law Offices Of Imam And Lsi Corporation

20080215927 - Method of monitoring the correct operation of a computer: The present invention relates to computers executing in time-share mode, under the control of their operating systems, a number of separate and independent application programs. The present invention relates in particular to the networks of onboard computer networks of IMA type executing application programs written independently of the hardware specifications... Agent: Lowe Hauptman & Berner, LLP

20080215928 - Failure resistant multiple computer system and method: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in... Agent: Perkins Coie LLP

20080215929 - Switching a defective signal line with a spare signal line without shutting down the computer system: A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20080215930 - Flash memory with multi-bit read: A memory device is described that uses extra data bits stored in a multi-level cell (MLC) to provide error information. An example embodiment provides a memory cell that uses more than 2X logic levels to store X data bits and an error bit. At least one extra bit provided during... Agent: Schwegman, Lundberg & Woessner/micron

20080215932 - Controlling software failure data reporting and responses: User input defines transmission filter rules to be met when sending an error report to a support provider. User input also defines collection filter rules to be met when including failure data within an error report. Error reports corresponding to crash failures at clients are filtered with the transmission filter... Agent: Workman Nydegger/microsoft

20080215933 - Controlling software failure data reporting and responses: User input defines transmission filter rules to be met when sending an error report to a support provider. User input also defines collection filter rules to be met when including failure data within an error report. Error reports corresponding to crash failures at clients are filtered with the transmission filter... Agent: Workman Nydegger/microsoft

20080215931 - Systems and methods for embedded application test suites: Systems, methods and media for testing computer programs m response to a program upgrade or installation are disclosed. In one embodiment, a computer executes software to detect when an upgrade or an installation occurs. When an upgrade or installation occurs the computer initiates a test of one or more applications... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC

20080215934 - Detecting method and system for consistency of link scrambling configuration: A detecting method for the consistency of a link scrambling configuration, comprises: setting the first threshold of the data packet error rate received by the receiving end; when the receiving end receiving date from the link, counting the received data packet error rate; judging whether the error rate is above... Agent: Leydig, Voit & Mayer, Ltd (for Huawei Technologies Co., Ltd)

20080215935 - Processing configuration data frames: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device... Agent: Sadler, Breen, Morasch & Colby, Ps

20080215936 - Non-chronological av-stream recording:

20080215937 - Remote bist for high speed test and redundancy calculation: Disclosed in a hybrid built-in self test (BIST) architecture for embedded memory arrays that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A standalone BIST logic controller operates at a lower frequency and communicates with a plurality of embedded memory arrays using a BIST instruction... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080215938 - Memory device and related testing method: A method for testing a memory device is disclosed. The method includes: respectively writing at least one test data into a plurality of storage blocks in the memory device such that a plurality of first time written test data are stored in the storage blocks; in a read with write... Agent: North America Intellectual Property Corporation

20080215939 - Semiconductor memory device with fail-bit storage unit and method for parallel bit testing: There are provided a semiconductor memory device and a method for testing the same, in which when a plurality of semiconductor memory devices are under test, tester equipment can detect which one of the semiconductor memory devices fails without a separate fail memory. The semiconductor memory device with a memory... Agent: Harness, Dickey & Pierce, P.L.C

20080215941 - Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications: A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a... Agent: Cantor Colburn LLP - IBM Austin

20080215940 - Methods and apparatus for estimating a position of a stuck-at defect in a scan chain of a device under test: As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when... Agent: Gregory W. Osterloth Holland & Hart, LLP

20080215942 - Testing of integrated circuits using boundary scan: Circuit testing equipment comprising a computer (110) having stored thereon a boundary scan description language (BSDL) file (111), a netlist (112) and a connections list (113). A connector (112) connects the computer to a boundary scan bus of a circuit (120) to be tested. The computer is arranged to parse... Agent: Holland & Knight LLP

20080215943 - Generating test sets for diagnosing scan chain failures: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to... Agent: Klarquist Sparkman, LLP

20080215944 - Built-in self test (bist) architecture having distributed interpretation and generalized command protocol: Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol is disclosed. In an embodiment, a system is disclosed and includes a centralized built-in self-test (BIST) controller configured to store an algorithm to test a plurality of memory modules. The BIST controller stores the algorithm as a set of... Agent: Qualcomm Incorporated

20080215945 - System and method for system-on-chip interconnect verification: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080215946 - Semiconductor integrated circuit and memory test method: A semiconductor integrated circuit is provided which is capable of testing a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the... Agent: Dickinson Wright PLLC

20080215947 - Debug circuit and a method of debugging: A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the multi-mode circuit a corresponding debug signal based on a clock signal provided at... Agent: Texas Instruments Incorporated

20080215948 - Method and apparatus for hybrid automatic repeat request transmission: A method and apparatus for hybrid automatic repeat request (HARQ) transmission are disclosed. If a packet has not been successfully transmitted, it is determined whether an HARQ early termination condition is met. If the HARQ early termination condition is met, the HARQ process is terminated and the packet is discarded... Agent: Volpe And Koenig, P.C. Dept. Icc

20080215949 - Server and client for determining error restoration according to image data transmission, and method of determining error restoration according to image data transmission: Provided are a server and client for determining error restoration according to image data transmission, and a method thereof. The server includes a forward error correction (FEC) mode performer to output image data in which a redundant bit for error correction is added, an automatic repeat request (ARQ) mode performer... Agent: Stein, Mcewen & Bui, LLP

20080215951 - Communication system: At the transmitter side, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into, two, first and second, data streams. The signal points are divided into signal point groups to which data of the first... Agent: Wenderoth, Lind & Ponack L.L.P.

20080215950 - Ldpc (low density parity check) coded signal decoding using parallel and simultaneous bit node and check node processing: LDPC (Low Density Parity Check) coded signal decoding using parallel and simultaneous bit node and check node processing. This novel approach to decoding of LDPC coded signals may be described as being LDPC bit-check parallel decoding. In some alternative embodiment, the approach to decoding LDPC coded signals may be modified... Agent: Garlick Harrison & Markison

20080215952 - Hybrid flash memory device, memory system, and method controlling errors: Provided is a hybrid flash memory device, a memory system, and a method of controlling errors. The hybrid flash memory device includes a data storage block with first and second data storage regions of flash memory cells, and error control block implementing first and second error control schemes, such that... Agent: Volentine & Whitt PLLC

20080215953 - Three bit error detection using ecc codes: An Error Correction Code (ECC) encoding module encodes an input data word by calculating parity bits according to an ECC index mapping. An ECC correction/detection module receives the encoded data word that may have become corrupted due to noise or distortion. The ECC correction/detection module executes a parity calculation on... Agent: Cisco Systems, Inc. Scientific-atlanta, Inc.

20080215954 - Bit error repair method and information processing apparatus: An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080215955 - Semiconductor storage device: A semiconductor storage device includes: a memory configured to store data at a first address and store an error detecting code corresponding to the data at a second address which is set up in a predetermined relation with the first address and different from the first address; and an address... Agent: Amin, Turocy & Calvin, LLP

20080215956 - Computing an error detection code syndrome based on a correction pattern: The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values... Agent: Shumaker & Sieffert, P.A.