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Error detection/correction and fault detection/recovery inventions 05/08

Recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing format for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
05/29/2008 > patent applications in patent subcategories.

20080126828 - Dynamic enablement and customization of tracing information in a data processing system: A computer implemented method, system, and computer usable program code for staged tracing, where an initial high-level trace is performed to detect potential problems or issues at a sub-system level, followed by a dynamic tracing state, with a more detailed level of tracing for an identified problematic sub-system. During such... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080126830 - Error accumulation register, error accumulation method, and error accumulation system: In operating a dual core processor, a register file collects a history of the error state information for each core. The core error state data can be analyzed to understand the recovery sequence of events. The recorded error sequence over time presents a detailed history of the recovery sequence which... Agent: International Business Machines Corporation

20080126829 - Simulation of failure recovery within clustered systems: Failure recovery within clustered systems is simulated. For each of a number of failure conditions for an initial state of a number of computing elements of a computerized system, a failure state of the computing elements is generated that corresponds to the failure condition and that is based on the... Agent: Law Offices Of Michael Dryja

20080126832 - Failover system and method: One aspect of the present invention provides a system for failover comprising at least one client selectively connectable to one of at least two interconnected servers via a network connection. In a normal state, one of the servers is designated a primary server when connected to the client and a... Agent: T. Andrew Currier Perry + Partners

20080126833 - Match server for a financial exchange having fault tolerant operation: Fault tolerant operation is disclosed for a primary match server of a financial exchange using an active copy-cat instance, a.k.a. backup match server, that mirrors operations in the primary match server, but only after those operations have successfully completed in the primary match server. Fault tolerant logic monitors inputs and... Agent: Brinks Hofer Gilson & Lione / Cme

20080126835 - Method and network element for improving error management in managed networks, and computer program product therefor: A method for identifying an error cause affecting the configuration of a network element (110) controlled by a network manager (100) is described. The method includes the step of transmitting from the network element (110) to the network manager (100) a message (5) including a first field (30, 40) for... Agent: Sughrue Mion, PLLC

20080126834 - On-demand provisioning of computer resources in physical/virtual cluster environments: A server cluster comprises a physical node and a virtual host node. The physical node includes an active node running an application. The virtual host node includes an inactive virtual node. The virtual node is activated upon failure of the active node and the application is failed over to the... Agent: Larson Newman Abel Polansky & White, LLP

20080126836 - Real time data storage monitoring and administration: The remote monitoring and administration system and method provides proactive monitoring and maintenance of one or more storage systems at remote locations from a central monitoring system. The remote locations include at least one data storage system connected to the Internet. The central monitoring system includes one or more cluster... Agent: Foley Hoag, LLP Patent Group, World Trade Center West

20080126831 - System and method for caching client requests to an application server based on the application server's reliability: An Intelligent Caching Tool collects reliability statistics for an application server to build a Hidden Markov Model. Using the Hidden Markov Model, the Intelligent Caching Tool calculates a reliability index for the application server. After setting a user defined reliability threshold, the Intelligent Caching Tool caches all client requests and... Agent: Ibm Corp. (raleigh Software Group) C/o Rudolf O Siegesmund Gordon & Rees, LLP

20080126840 - Method for reconstructing data in case of two disk drives of raid failure and system therefor: The present invention is to provide a method for reconstructing data in case of failure of two HDs of a RAID, wherein the RAID is a logical disk drive assembly including at least three HDs and a RAID controller and data is divided into block strips which are stored on... Agent: Bacon & Thomas, PLLC

20080126837 - Method of recovering damage of hard disk having different types of partitions: The present invention discloses a method of recovering damage of a hard disk having different types of partitions. The method can be exercised in an electronic device including several operating hard disks and a backup hard disk, and these operating hard disks are all created an unrecoverable configuration partition and... Agent: Bacon & Thomas, PLLC

20080126841 - Methods and systems for recovering meta-data in a cache memory after a corruption event: A method for recovering meta-data that has been subjected to corruption is disclosed for a cache memory. Each table entry in the cache memory has an in-cache indicator for indicating whether the data unit associated therewith is stored in a cache-slot in the cache memory. A first review is conducted... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080126838 - Optimized reconstruction and copyback methodology for a disconnected drive in the presence of a global hot spare disk: In a further aspect of the present invention, a method for the reconstruction and copyback of a disconnected RAID disk utilizing a global hot spare disk is disclosed. The method includes: disconnecting a RAID component disk; reconstructing data from the disconnected RAID disk onto a global hot spare disk; reconnecting... Agent: Lsi Corporation

20080126839 - Optimized reconstruction and copyback methodology for a failed drive in the presence of a global hot spare disc: In a further aspect of the present invention, a method for the reconstruction and copyback of a failed disk volume utilizing a global hot spare disk is disclosed. The method includes: detecting the failure of a RAID component disk; reconstructing a portion of the data contained on the failed RAID... Agent: Lsi Corporation

20080126845 - Automatic failover configuration with lightweight observer: Techniques used in an automatic failover configuration having a primary database system, a standby database system, and an observer for preventing divergence among the primary and standby database systems while increasing the availability of the primary database system. In the automatic failover configuration, the primary database system remains available even... Agent: Gordon E. Nelson Patent Attorney PC

20080126846 - Automatic failover configuration with redundant abservers: Techniques used in an automatic failover configuration having a primary database system, a standby database system, and an observer for preventing divergence among the primary and standby database systems while increasing the availability of the primary database system. In the automatic failover configuration, the primary database system remains available even... Agent: Gordon E. Nelson Patent Attorney PC

20080126847 - Data-recovery control device: A first storing unit stores therein information on a communication status relating to installing positions of a plurality of storage devices forming a disk array. A selecting unit selects a plurality of storage devices for storing data, based on stored information. A second storing unit stores recovery data recovered from... Agent: Staas & Halsey LLP

20080126843 - Memory controller, memory circuit and memory system with a memory controller and a memory circuit: Methods and apparatus for adjusting a phase difference between clock signals. A first clock signal at a memory controller is adjusted relative to a clock second signal at a memory device. In one embodiment, data is transferred to the memory device according to the first clock signal, which has a... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080126842 - Redundancy recovery within a distributed data-storage system: Embodiments of the present invention are directed to methods, and distributed data-storage systems employing the methods, for recovering redundancy within a distributed data-storage system upon failure of one or more mass-storage devices within a component data-storage system of the distributed data-storage system. In certain embodiments, failure of a mass-storage device... Agent: Hewlett Packard Company

20080126844 - Storage system: If a failure occurs in any of a plurality of data disks, and if a controller receives a read request from a host computer for the RAID group including the failed data disk, the controller performs data recovery using data stored in the other data disks in the RAID group,... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080126848 - Stored data processing apparatus, storage apparatus, and stored data processing program: A stored data processing apparatus comprises: a calculation section that performs calculation for each bit position using data of all first blocks in a second block that has been specified as an update target on a storage medium and outputs a result of the calculation as calculation data; a write... Agent: Greer, Burns & Crain

20080126851 - Redundant storage enclosure processor (sep) implementation for use in serial attached scsi (sas) environment: An information handling system includes a storage enclosure operable to communicate with a storage initiator. The storage enclosure includes a first controller corresponding to a first storage domain for enabling access between the storage initiator and a plurality of storage targets using a storage protocol. A second controller of the... Agent: Baker Botts, LLP

20080126850 - System and method of repair management for raid arrays: A storage array disposed in a data storage system is reconfigured. A data storage system is supplied comprising a plurality of data storage devices, wherein each of the plurality of data storage devices is assigned to one of a plurality of data storage arrays, or is assigned as a spare... Agent: Quarles & Brady LLP

20080126849 - Using sas address zoning to add/replace hot spares to raid set: Certain ones of a plurality of SAS hard disk drives are assigned to different SAS zones using a SAS zoning expander(s). A processor and SAS RAID controller have access to only those SAS hard disk drives assigned to the same zone(s) as the processor and SAS RAID controller. Each SAS... Agent: Baker Botts, LLP

20080126852 - Handling fatal computer hardware errors: Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error;... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20080126853 - Fault tolerance and failover using active copy-cat: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and... Agent: Brinks Hofer Gilson & Lione / Cme

20080126854 - Redundant service processor failover protocol: A data processing system (or server) is designed with redundant service processors and a hypervisor. Both service processors are capable of performing the full set of service processor functions, with one service processor (SP) registering itself as a primary SP with the system firmware/hypervisor and the other SP registering as... Agent: Dillon & Yudell LLP

20080126855 - Storage control apparatus and failure recovery method for storage control apparatus: A storage control apparatus of the present invention reduces the frequency of disk drive failures. An error management part manages the number of times errors occur in respective disk drives. A disk drive in which the number of errors meets or exceeds a threshold value is selected as a disk... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080126856 - Configuration replication for system recovery and migration: Aspects of the subject matter described herein relate to system state changes. In aspects, a state change monitor detects a state change, determines whether the state change is within a set of state changes that are monitored, and, if so, logs data regarding the state change. The data and any... Agent: Microsoft Corporation

20080126858 - Data visualization for diagnosing computing systems: Disclosed herein is a data visualization methodology to assist network administrators and service engineers for complex computing systems in diagnosing and addressing faults, errors and other conditions within the computing system, and related computerized processes and network architectures and systems supporting the methodology. The methodology produces a visual representation of... Agent: Hogan & Hartson LLPIPGroup, Columbia Square

20080126860 - Fault management for a printing system: A printing system includes a plurality of print media processing modules which transfer print media therebetween during printing and a fault management agent associated with each of the modules for acquiring fault-related data from the respective processing module. A fault management system is in communication with the fault management agents... Agent: Fay Sharpe / Xerox - Parc

20080126861 - Industrial process control loop monitor: A process control loop monitor includes a housing configured to mount in the field of an industrial process. A loop interface circuit couples to a process control loop and receives data from the process control loop. A memory stores data received by the loop interface circuit from the process control... Agent: Westman Champlin & Kelly, P.A.

20080126859 - Methods and arrangements for distributed diagnosis in distributed systems using belief propagation: In the context of problems associated with self-healing in autonomic computer systems, and particularly, the problem of fast and efficient real-time diagnosis in large-scale distributed systems, a “divide-and-conquer” approach to diagnostic tasks is disclosed. Preferably, parallel (i.e., multi-thread) and distributed (i.e., multi-machine) architectures are used, whereby the diagnostic task is... Agent: Ference & Associates LLC

20080126857 - Preemptive data protection for copy services in storage systems and applications: A common interface and communication methodology are provided for interaction between the components of a storage area network for them to activate “triggers” that cause actions to be taken by the devices to utilize copy service functions to create additional copies of data, and to potentially route load to other... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080126862 - System and method for testing software code for use on a target processor: A system and method for testing software code for use on a target processor are disclosed. A system includes a test processor which includes a core substantially similar in physical design and functionality to the target processor for which the software code is intended to be used and an emulation... Agent: Baker Botts, LLP

20080126863 - Testing dram chips with a pc motherboard attached to a chip handler by a solder-side adaptor board with an advanced-memory buffer (amb): Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module... Agent: Stuart T Auvinen

20080126864 - Fault isolation in a microcontroller based computer: A method and data processing system for isolating a faulty component in a computer. A first microcontroller detects a fault in a component of a computer. Responsive to detecting the fault, the first microcontroller sets a first fault record for the component to pending fault, sets a second fault record... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080126865 - Debugging system and method: A debugging system, device and method for debugging the error malfunctions of a target device is provided. The system includes a debugging device setting a permanent break point in a target device when the debugging device is connected with the target device, and the target device stopping operation when the... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20080126866 - Method and system for kernel-level diagnostics using a hardware watchpoint facility: A method for performing kernel-level diagnostics. The method includes obtaining a hardware trap associated with an attempt by a kernel-level instruction stream to access a memory address, wherein the memory address is referenced by a hardware watchpoint facility, forwarding the hardware trap to a software breakpoint handler, executing a diagnostic... Agent: Osha Liang L.L.P./sun

20080126869 - Generating code to validate input data: Input data is validated by generating code based on the input data. A schema is generated based on the input data indicating conditions for the input file. The schema may then be customized based on a type of application to consume the input data. A validator executable code is generated... Agent: Merchant & Gould (microsoft)

20080126870 - Maintenance system, method of controlling maintenance system, server, record medium in which program used for server is recorded, computer and record medium in which program used for computer is recorded: In a maintenance system according to the invention, in the management terminal, an input receiving unit receives an input of management information related to a condition of the managed machine, a second transmitting unit transmits the management information related to the condition of the managed machine to the server, in... Agent: Amin, Turocy & Calvin, LLP

20080126867 - Method and system for selective regression testing: A system and method for selective regression testing is described. The system and method provides a test script database identifying multiple portions of a first low level code (e.g., assembly code) and tests associated with at least one of the multiple portions of first low level code. A comparator may... Agent: Schwegman, Lundberg & Woessner, P.A.

20080126868 - System and method for storing embedded diagnostic test failure reports on a faulty component: A method is provided for performing a diagnostic test on a piece of equipment, the equipment including a plurality of components, each of the components including a diagnostic test result store. The method comprises executing a diagnostic test by means of a diagnostic apparatus embedded within the piece of equipment,... Agent: Agilent Technologies Inc.

20080126872 - Diagnosing faults within programs being executed by virtual machines: A debug interface is disclosed that is operable to receive diagnostic signals from a host debugger, amend the diagnostic signals and send the amended diagnostic signals to a virtual machine operable to process a plurality of applications in parallel. The debug interface comprises: at least one port corresponding to at... Agent: Nixon & Vanderhye, PC

20080126873 - Resource efficient software tracing for problem diagnosis: The present invention discloses a solution that defines multiple retry points for a software application which are operable to generate and record trace information only as part of a retry execution in response to an exception. Outside these conditions, the burdens of generating and recording trace information can be avoided.... Agent: Patents On Demand, P.A.

20080126871 - Token-based trace system: A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send... Agent: Texas Instruments Incorporated

20080126874 - Arm and rollback in a multi-chassis system: A multi-chassis system includes at least a first chassis and a second chassis that each includes one or more blades. The one or more blades in turn include one or more ports. The two or more chassis are connected through use of an interconnector. The multi-chassis system may also include... Agent: Workman Nydegger

20080126876 - Semiconductor memory device and redundancy method of the same: A semiconductor memory device may include a memory cell array, a redundancy address decoder, a defective address detection unit, and a defective address program unit. The memory cell array includes a plurality of memory cell groups and a predetermined number of redundancy memory cell groups. The redundancy address decoder includes... Agent: Harness, Dickey & Pierce, P.L.C

20080126875 - System and method for updating hard disk write parameters in the field: Systems and methods are provided for updating a temperature table for a disk subsystem in a client system using information provided by a server system. In one embodiment, among others, the client receives an update command from the server system. The update command comprises instructions to update the temperature table.... Agent: Scientific-atlanta, Inc. Intellectual Property Department

20080126878 - Highlighting anomalies when displaying trace results: A computer program product and method for displaying trace log entries from a plurality of trace logs call for identifying trace log entries; determining a degree of relevancy for each of the trace log entries; and classifying the trace log entries.... Agent: Cantor Colburn LLP - IBM Austin

20080126877 - Microprocessor with trace functionality: A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and... Agent: Donald J Lenkszus

20080126880 - Automatic generation of test cases from error data: Some embodiments of a method and apparatus for automatically generating test cases from error data have been presented. In one embodiment, the method includes providing a graphical user interface (GUI) to allow a user to submit a report of an error in a program. The report may be partially written... Agent: Thomas S. Ferrill Blakely, Sokoloff, Taylor & Zafman LLP

20080126879 - Method and system for a reliable kernel core dump on multiple partitioned platform: A method and system for generating and obtaining reliable core dump from a multiple partitioned platform is described. The method generated a system core dump by a first operating system in a first partition, in response to detecting a predetermined event. The core dump may be stored in a shared... Agent: Intel/blakely

20080126881 - Method and apparatus for using performance parameters to predict a computer system failure: One embodiment of the present invention provides a system that uses performance parameters to predict a computer system failure. The system operates by evaluating a performance-parameter rule on a target system to determine if a corresponding performance parameter is within a predetermined range. Note that the performance parameter defines a... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080126882 - Devices, systems, and methods regarding a plc system fault: Certain exemplary embodiments can comprise a method, which can comprise providing a signal indicative of a set single bit flag. The flag can be set for a scan cycle responsive to a detection of a fault in an Input/Output (I/O) device of a programmable logic controller (PLC) system or an... Agent: Siemens Corporation Intellectual Property Department

20080126883 - Method and apparatus for reporting failure conditions during transactional execution: One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution,... Agent: Pvf -- Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080126884 - Method for providing detailed information and support regarding an event message: A method provides information and support related to an event message that is stored in an event log. A user display device displays the message and its description to a user. Recommended actions to the user are provided and user selectable options related to the message are presented, wherein the... Agent: Schiff Hardin, LLP Patent Department

20080126885 - Fault tolerant soft error detection for storage subsystems: A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two... Agent: Intel Corporation C/o Intellevate, LLC

20080126887 - Method and system for site configurable error reporting: Embodiments of the present invention relate generally to error reporting methods and systems. An error reporting application may be configured to be a stand-alone program, embedded within another application, or added as a plug-in application. The error reporting application may also be configured to provide a mechanism for a user... Agent: Mh2 Technology Law Group (cust. No. W/red Hat)

20080126886 - Rfid active/passive tag identifying failed sub-cru and location within higher level cru: A radio frequency identifier (RFID) active/passive tag is provided to identify failed sub-CRU and location within a higher level CRU. When an error occurs on the base blade or within one of the sub-CRUs, the embedded processor writes failure information to the RFID. RFID tags may also contain data identifying... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080126888 - Skew-correcting apparatus using external communications element: This algorithm and apparatus provides the ability to determine the amount of skew that should be injected into a high-speed data communications system consisting of a plurality of lanes comprising a data bus on a per lane basis, relative to a reference lane, for the purpose of compensating for inherent... Agent: Avalon Microelectronics, Inc. Attn: Heidi Peet

20080126889 - Transmission headstock for test stands: A mobile test unit for testing a powertrain component such as a transmission is used in a test cell. A test unit includes a movable, generally horizontal base plate, and a frame spaced from the base plate. A headstock is secured to the frame for supporting the transmission. An adjustable... Agent: Carlson, Gaskey & Olds, P.C.

20080126890 - Autonomic parity exchange: Error tolerance is increased for a storage system having a plurality of arrays by making local redundancy in a selected array globally available throughout the storage system. To achieve the increased error tolerance, a donor array is selected from the plurality of arrays when the difference between a minimum distance... Agent: Joseph P. Curtin, L.L.C.

20080126892 - Locally synchronous shared bist architecture for testing embedded memories with asynchronous interfaces: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory... Agent: Docket Clerk

20080126891 - Memory lifetime gauging system, method and computer program product: An apparatus, method, and computer program product are provided for identifying at least one aspect associated with a lifetime of memory. Further, an indicia is visually displayed reflecting the at least one aspect.... Agent: Zilka-kotab, PC

20080126893 - Method of refreshing a dynamic random access memory and corresponding dynamic random access memory device, in particular incorporated into a cellular mobile telephone: A method is for refreshing a dynamic random access memory coupled to an error correction system, which uses an error correcting code. The dynamic random access memory includes groups of memory cells storing bits, each group of memory cells being subdivided into packets of memory cells. Each packet of memory... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080126894 - Semiconductor integrated circuit which properly executes an operational test of a circuit under test in the semiconductor integrated circuit: A semiconductor integrated circuit includes a circuit under test coupled to the logic circuit to receive a plurality internal test signals and a delay time measurement terminal from which a delay time measurement signal is output. The delay time measurement signal is turned in accordance with a transition of one... Agent: Volentine & Whitt PLLC

20080126895 - Middlesoft commander: A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing... Agent: Dillon & Yudell LLP

20080126896 - System and method for device performance characterization in physical and logical domains with ac scan testing: A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for... Agent: Patentry

20080126898 - System and method for generating on-chip individual clock domain based scan enable signal used for launch of last shift type of at-speed scan testing: Presented herein are system(s) and method(s) for generating a individual clock domain based scan enable signal for launch of last shift type of at-speed scan testing. In one embodiment, there is presented a circuit for scan testing. The circuit comprises at least two flip flops, one OR gate, one inverter,... Agent: Mcandrews Held & Malloy, Ltd

20080126897 - System and method for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing: Presented herein are system(s) and method(s) for generating self-synchronized launch of last shift capture pulses using on-chip phase locked loop for at-speed scan testing. In one embodiment, there is presented a system for scan testing. The system comprises an ATE clock and a phase lock loop. The ATE clock shifts... Agent: Mcandrews Held & Malloy, Ltd

20080126899 - Pattern controlled, full speed ate compare capability for deterministic & non-deterministic ic data: Pattern controllable LFSRs or MISRs are disclosed that are able to mask indeterminate states while performing tests on DUT outputs. At appropriate times, the MISRs or the LFSRs will mask the data being input to the MISRs or the LFSRs so that indeterminate states are not received. This allows fast/complex... Agent: Morrison & Foerster, LLP

20080126900 - Array delete mechanisms for shipping a microprocessor with defective arrays: Detecting and correcting errors in arrays after ABIST testing, after ABIST testing, detected errors are faults are isolated by blowing a fuse.... Agent: International Business Machines Corporation

20080126901 - Memory with improved bist: An integrated circuit device includes an embedded memory having a plurality of memory macros and a built-in-self-test (BIST) circuit coupled to the plurality of memory macros for simultaneous operation of the memory macros, wherein the BIST circuit is configured to select from the memory macros' data outputs an individual memory... Agent: Duane Morris LLPIPDepartment (tsmc)

20080126902 - Requirements-based test generation: This test generator takes data flow block diagrams and uses requirements-based templates, selective signal propagation, and range comparison and intersection to generate test cases containing test vectors for those diagrams. The templates are based on the functionality and characteristics of a block type, and each block type has associated templates.... Agent: Honeywell International Inc.

20080126903 - Compression and decompression of stimulus and response waveforms in automated test systems: An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In... Agent: Haynes Beffel & Wolfeld LLP

20080126904 - Frame error concealment method and apparatus and decoding method and apparatus using the same: A frame error concealment method and apparatus and a decoding method and apparatus using the same. The frame error concealment method includes setting a concealment method to conceal an error based on one or more signal characteristics of an error frame having the error and concealing the error using the... Agent: Stanzione & Kim, LLP

20080126905 - Memory control device, computer system and data reproducing and recording device: The memory control device according to the present invention reads data including an error correcting code from a memory and includes: an error correcting unit which detects an error in the data and corrects the detected error in the data, based on the error correcting code, and sends the error... Agent: Greenblum & Bernstein, P.L.C

20080126906 - Communication method and communication device: A request change unit outputs a command as a request under control of a judgment control unit. A response condition determination unit determines a condition that is to be matched by a correct response which is to be returned from the other device-in-communication in reply to the command if the... Agent: Wenderoth, Lind & Ponack L.L.P.

20080126907 - Method and system for syndrome generation and data recovery: A method and system for syndrome generation and data recovery is described. The system includes a parity generator coupled to one or more storage devices to generate parity for data recovery. The parity generator includes a first comparator to generate a first parity factor based on data in one or... Agent: Blakely Sokoloff Taylor & Zafman

20080126910 - Low dimensional spectral concentration codes and direct list decoding: Systems and methods provide an optionally keyed error-correcting code that is spectrally concentrated. Each codeword of the low dimensional spectral concentration code (LDSC code) typically has very few coefficients of large magnitude and can be constructed even with limited processing resources. Decoding can be performed on low power devices. Error-correcting... Agent: Lee & Hayes PLLC

20080126909 - System for protecting data during high-speed bidirectional communication between a master device and a slave device: A system for protecting data during high-speed bidirectional communication between a master device and a slave device. The master device may control data transfer between the master device and the slave device. In addition, the master device may perform a read request to the slave device for a first data... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080126908 - Universal error control coding system for digital communication and data storage systems: The universal forward error-correction coding system provides adjustable code rates and coding gains to greatly benefit the design of many modern digital communications (data storage) systems. The channel encoding and decoding methods are universal such that a single encoder and a single decoder can be used to implement all the... Agent: Patton Boggs LLP

20080126911 - Memory wrap test mode using functional read/write buffers: A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the... Agent: Ibm Corporation (jvm)

20080126913 - Methods and systems for managing corrupted meta-data in a computer system or network: A method for managing data in a computer system comprises identifying a data-set that has data unit protection that is suspected of having been corrupted, suspending a data unit protection process for the data-set; deferring re-establishing the data unit protection process for the data-set until issuance of a request for... Agent: Emc Corporation Office Of The General Counsel

20080126912 - Storing data redundantly: A method for storing data blocks, including forming the data blocks into groups comprising N·M data blocks, where N and M are different positive integers. For every group, the N·M data blocks are assigned to correspond to elements of an array comprising N rows and M columns. A respective parity... Agent: Katten Muchin Rosenman LLP

20080126914 - Turbo decoder and turbo decoding method: A turbo decoder includes a plurality of element decoders, a memory section that stores element decoded results in matrix-patterned memory spaces, and a memory controller that writes the element decoded result of each of the element decoders in a row or column direction in the matrix-patterned memory spaces with addresses... Agent: Bingham Mccutchen LLP

20080126915 - Dvb-h receiver for forward error correction and method thereof: A DVB-H receiver for performing forward error correction is disclosed. The DVB-H receiver includes: a tuner, for receiving a data stream; a base-band receiver, coupled to the tuner, for continuously extracting and transmitting data bytes of an MPE-FEC frame from the data stream; a backend system, coupled to the base-band... Agent: North America Intellectual Property Corporation

20080126917 - Data processing systems and methods for processing digital data with low density parity check matrix: A data processing system for processing digital data with a low density parity check (LDPC) matrix includes: a storage device for storing a plurality of indices representing a plurality of shifting numbers, where the LDPC matrix comprises an array of elements, and at least one element of the LDPC matrix... Agent: North America Intellectual Property Corporation

20080126916 - Method of executing ldpc coding using parity check matrix: A low density parity check (LDPC) coding method, and more particularly, a method of executing LDPC coding using a parity check matrix is disclosed. The present invention comprises providing an information bit stream for channel encoding, and encoding the information bit stream by using a first parity check matrix including... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20080126918 - Command line testing: Provided are a system, method and article of manufacture for validating an expected data output of an application under test. A first table comprising named columns populated with the expected data output and a second table comprising named columns associated with the expected data output of the named columns of... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

  
05/22/2008 > patent applications in patent subcategories.

20080120517 - Method to control the execution of a program by a microcontroller: P

20080120516 - Variable bleed solenoid recovery system: A recovery control system and method for automatic transmissions includes a diagnostic module that determines a fault condition of a variable bleed solenoid (VBS) when the automatic transmission fails to establish a desired drive ratio. A recovery module initiates a recovery cycle of the VBS based on the fault condition.... Agent: General Motors Corporation Legal Staff

20080120518 - Replacing system hardware: A method and apparatus for managing spare partition units in a partitionable computing device is disclosed. The method comprises detecting if a spare partition unit is required for addition or replacement in a local operating system and if a spare partition unit is required for addition, initiating an addition of... Agent: Christensen, O'connor, Johnson, Kindness, Pllc

20080120520 - Security features in interconnect centric architectures: A method comprising: detecting a sub-system to be controlled in a reduced resource mode in a device having an interconnecting system architecture; sending a resource reducing request to an interconnect node of the sub-system, the interconnect node belonging to a first power/clock signal domain; and reducing resources of processing elements... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080120521 - Automated testing and control of networked devices: A system, method of automated testing and control of networked devices is provided. One or more test cases are defined in a test plan for execution against a plurality of networked devices. The test cases are created using a command defined grammar comprising verbs which characterize how commands or actions... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20080120522 - Testing of control strategies in a control system controlling a process control plant: Test cases to test control strategies of a control process are specified in input files. The instructions in the input files are automatically read by a block tester, which interfaces with the control system to issue the instructions. As a test designer can create the instructions in the input files... Agent: Honeywell International Inc.

20080120523 - Efficient and flexible trace trigger handling for non-concurrent events: A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a... Agent: Cantor Colburn LLP - Ibm Rochester Division

20080120519 - Recording medium for storing start position information for each zone and method and apparatus of managing data using the information: A recording medium for storing start position information for each zone, a method of managing data using the information, and an apparatus for recording the information and controlling recording and reproduction of data based on the recorded information. In a disc having a plurality of zones which form a group,... Agent: Stein, Mcewen & Bui, LLP

20080120524 - Method and apparatus for monitoring bit-error rate: A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of different bit-error rate profiles and... Agent: Verizon Patent Management Group

20080120525 - Method and apparatus for detecting and correcting soft-error upsets in latches: An error detection circuit for a latch precharges two dynamic nodes whose discharge paths are gated by true and complement storage nodes of the latch, such that one and only one of the dynamic nodes always discharges when the clock signal transitions from an active state to an inactive state.... Agent: Ibm Corporation (jvm)

20080120526 - Memory device with adjustable read reference based on ecc and method thereof: A first value from a set of bit cells of a sector of a non-volatile memory device is sensed based on a first read reference. A second value from the set of bit cells is sensed based on a second read reference different than the first read reference. A third... Agent: Larson Newman Abel Polansky & White, LLP

20080120527 - Communication error detection apparatus: The present invention provides a communication error detection apparatus that can detect errors of communication networks in a short term after the communication error detection apparatus are installed on the communication networks. In addition, the present invention provides a communication error detection apparatus that can immediately and correctly detect errors... Agent: Rabin & Berdo, Pc

20080120528 - Reception method, reception apparatus, and program: A reception apparatus, method and a program using the reception method are provided to prevent degradation of reception quality due to interference. In a reception apparatus, an ADC samples data rIq[k] and rQq[k]. Based on the sampled data, a level detector finds an interference evaluation value Cc[l] for each OFDM... Agent: Posz Law Group, Plc

20080120529 - Soft decision correction method, receiver using the same, and program therefor: A soft decision value correction method can detect interference occurring in a desired wave and correct a soft decision value where a received power difference between the desired wave and an interference wave is small. A receiver and a program capable of performing the soft decision value correction method are... Agent: Posz Law Group, Plc

20080120530 - Transceiver puncture circuit of wireless communication system: The present invention relates to a transceiver puncture circuit of wireless communication system, which is amounted with a control circuit and a clipper module, the puncture module couples to a coding unit of the transceiver. The control circuit bases on a fixed clock signal, results in an enable signal to... Agent: Rosenberg, Klein & Lee

20080120531 - Methods and apparatus for soft decision decoding using reliability values based on a log base two function: Methods and apparatus are disclosed for soft decision decoding using reliability values based on a log base two function. A signal is processed to determine one or more reliability values for a soft decision decoder by computing one or more log-likelihood ratio (LLR) values using a log base two function.... Agent: Ryan, Mason & Lewis, LLP

  
05/15/2008 > patent applications in patent subcategories.

20080115007 - Efficient layered coding technique to mitigate shadowing in satellite propagation channel: An original data stream is encoded into a high priority data stream and a low priority data stream. The high priority data stream is encoded so as to permit decoding of the high priority data steam independently of the low priority data stream. The high priority data stream is transmitted... Agent: Qualcomm Incorporated

20080115008 - Systems and methods for recovering from configuration data mismatches in a clustered environment: Apparatus and methods are provided for recovering from mismatching configuration data in a clustered environment having a plurality of storage devices coupled to a plurality of storage controllers. If a clustered environment has a first storage device of the plurality of storage devices that has first configuration data that does... Agent: Lsi Corporation

20080115009 - Registers in a communication system: An apparatus comprising a data storage configured to store and update a copy of data that is stored in a plurality of registers of a network wherein the registers are provided for storing data associated with respective users of the network. The apparatus is configured to communicate data from the... Agent: Foley & Lardner LLP

20080115010 - System and method to establish fine-grained platform control: In an embodiment, processes are to be migrated in a multi-core computing system. Task migration is performed between and among cores to prevent over tasking or overheating of individual cores. In a platform with multi-core processors, each core is thermally isolated and has individual thermal sensors to indicate overheating. Processes... Agent: Intel Corporation C/o Intellevate, Llc

20080115012 - Method and infrastructure for detecting and/or servicing a failing/failed operating system instance: A method and infrastructure for a diagnosis and/or repair mechanism in a computer system, that includes an auxiliary service system running on the computer system.... Agent: Mcginn Intellectual Property Law Group, Pllc

20080115011 - Method and system for trusted/untrusted digital signal processor debugging operations: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism... Agent: Qualcomm Incorporated

20080115013 - Method of authentication, and image display apparatus incorporating the method: A method of authentication and an image display apparatus incorporating the method are provided. The method of authentication includes determining whether or not an error is generated in an authentication with an externally-connected multimedia source, and upon determination that the authentication error is generated, changing a reset signal to re-attempt... Agent: Sughrue Mion, Pllc

20080115015 - Management of access to storage area of storage system: A storage management system for managing, in a computer system, access to a storage area for storing data, the computer system includes: a storage system that provides the storage area; a host computer system that mounts the storage area of the storage system via a network; and a maintenance system... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080115014 - Method and apparatus for detecting degradation in a remote storage device: A system that monitors telemetry from a host computer system to detect degradation in a remote storage device. During operation, the system monitors performance parameters from a host computer system which accesses the remote storage device, wherein the performance parameters relate to the interactions between the host computer system and... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20080115016 - System and method for analyzing unknown file format to perform software security test: A system and method for analyzing a file format to perform a software security test are provided. The system includes a file scanner for monitoring a program that loads an unknown file on a memory and parsing function parameters of the loaded file, and a file analyzer for receiving the... Agent: Rabin & Berdo, Pc

20080115017 - Detection and correction of block-level data corruption in fault-tolerant data-storage systems: Various embodiments of the present invention provide fault-tolerant, redundancy-based data-storage systems that rely on disk-controller-implemented error detection and error correction, at the disk-block level, and RAID-controller-implemented data-redundancy methods, at the disk and disk-stripe level, in order to provide comprehensive, efficient, and system-wide error detection and error correction. Embodiments of the... Agent: Hewlett Packard Company

20080115018 - Control system for an optical storage device: A control system determines read performance of an optical storage device according to lock performance of a re-timing signal. The control system includes a filtering and re-timing unit for receiving a radio frequency (RF) signal and outputting the re-timing signal and an un-corrected output signal, an error correction unit for... Agent: Birch Stewart Kolasch & Birch

20080115019 - Circuit timing monitor having a selectable-path ring oscillator: An in-circuit timing monitor having a selectable-path ring oscillator circuit provides delay and performance measurements in an actual circuit environment. A test mode signal is applied to a digital circuit to de-select a given functional input signal applied to a functional logic block within the digital circuit and replace it... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.l.c.

20080115020 - Plesiochronous receiver pin with synchronous mode for testing on ate: A method and apparatus for conveying test stimulus data from an ATE system to an integrated circuit (IC) via a plesiochronous interconnect. The IC includes a core logic unit and a first receiver coupled to the core logic unit by a first data path. The first receiver includes an input... Agent: Mhkkg/sun

20080115021 - Plesiochronous transmit pin with synchronous mode for testing on ate: A method and apparatus for conveying test response data from an integrated circuit to ATE via a plesiochronous interconnect. The integrated circuit includes a core logic unit and a first transmitter coupled thereto by a first data path. In a normal mode, data conveyed from the core logic unit to... Agent: Mhkkg/sun

20080115022 - System and related method for chip i/o test: System and related method for testing a chip with a high-speed bus interface in a low speed testing environment is provided. The testing method for testing input/output functions of a chip includes: establishing an inner loop path between a transmission mechanism and a receiving mechanism of the chip; transmitting a... Agent: North America Intellectual Property Corporation

20080115023 - Set hardened register: A radiation hardened latch and a method of operation. To mitigate SET effects, the latch includes an internally located pulse rejection inverter. The pulse rejection inverter receives an input logic signal, delays it, and compares the delay logic signal to the input logic signal. If the input logic signal and... Agent: Honeywell International Inc.

20080115024 - System and method for testing state retention circuits: This invention discloses a system and method for testing a plurality of state retention circuits in an integrated circuit (IC) chip, that comprises a built-in test circuit configured to invoke a clock, a save and a restore signal, and a plurality of serially connected data latches receiving the clock, save... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080115025 - Circuit and method operable in functional and diagnostic modes: The application discloses a circuit comprising at least one flip flop, said flip flop comprising: a master latch and a slave latch; a data signal input and a scan signal input arranged in parallel to each other and each input comprising a tristateable device; and a scan enable signal input,... Agent: Nixon & Vanderhye, Pc

20080115026 - Method and apparatus for scheduling bist routines: The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one... Agent: Qualcomm Incorporated

20080115027 - Memory model for functional verification of multi-processor systems: Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle... Agent: Ibm Corporation, T.j. Watson Research Center

20080115028 - Method and system for test verification of integrated circuit designs: A method and system for verifying the design of an integrated circuit including an analog portion and a digital portion are disclosed. As one example, a method for verifying the design of an integrated circuit is disclosed, which includes the steps of generating an analog stimulus, performing a simulation test... Agent: Fogg & Powers Llc

20080115029 - iterative test generation and diagnostic method based on modeled and unmodeled faults: A diagnostic and characterization tool applicable to structural VLSI designs to address problems associated with fault tester interactive pattern generation and ways of effectively reducing diagnostic test time while achieving greater fail resolution. Empirical fail data drives the creation of adaptive test patterns which localize the fail to a precise... Agent: International Business Machines Corporation Dept. 18g

20080115030 - Information transmission and reception: An information transmitting apparatus is described. An interface includes a first input for a valid data word, a second input for an information to be transmitted, and an output, wherein the interface provides the data word or a data word recognizable as an invalid data word at the output, depending... Agent: Slater & Matsil LLP

20080115033 - Address generation for contention-free memory mappings of turbo codes with arp (almost regular permutation) interleaves: Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function , that is based on an address mapping , which corresponds to an interleave inverse order of decoding processing... Agent: Garlick Harrison & Markison

20080115031 - Communication signal decoding: Provided are systems, methods and techniques that use an embedded error-detection code within a received communication signal to determine when to stop iterative decoding of the communication signal.... Agent: Huffman Law Group, P.c.

20080115032 - Efficient almost regular permutation (arp) interleaver and method: A method for operating an ARP interleaver is provided that includes generating each of a plurality of interleaved indices, P(j), as a function of an adjacent interleaved index. For one embodiment, the adjacent interleaved index is the immediately previous index, P(j−1), and each of the interleaved indices, P(j), is generated... Agent: Docket Clerk

20080115034 - Qpp interleaver/de-interleaver for turbo codes: m

20080115036 - Iterative read channel architectures with coded modulation: Iterative decoding channel architectures employing coded modulation are provided. The coded modulation is realized via set partitioning for Partial Response (PR) channels along with multi-level coding. Associated error correction encoding and decoding methods, with additional compatibility considerations for channel constrained coding, are also provided.... Agent: Seagate Technology Llc C/o Westman Champlin & Kelly, P.a.

20080115037 - Method and apparatus for applying forward error correction in 66b systems: A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity blocks using the... Agent: Conley Rose, P.c.

20080115035 - Post-viterbi error correction method and apparatus: In an error correction method, a codeword is transmitted through a noisy communication channel and detected by a receiving device. An error detection code is then applied to the detected codeword to generate a syndrome. Where the syndrome is not all zero, the codeword is determined to contain some error.... Agent: Volentine & Whitt Pllc

20080115038 - Dynamic early termination of iterative decoding for turbo equalization: A method and apparatus for selectively terminating turbo equalization is disclosed. At least two iterations of turbo equalization are performed. The number of errors corrected between the first iteration and the second iteration are calculated. In one embodiment, if the sign of corresponding bits in the data block is different... Agent: Seagate Technology Llc C/o Westman Champlin & Kelly, P.a.

20080115039 - Destination indication to aid in posted write buffer loading: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second element. The memory device may also include logic to... Agent: Intel Corporation C/o Intellevate, Llc

20080115040 - Checksum generator for variable-length data: One embodiment relates to a method of generating an N-bit checksum for variable-length data. An N-bit data word of the variable-length data is received by data input circuitry, and an N-bit input checksum generator is used to calculate an updated value of the N-bit checksum for N-bit data words. A... Agent: Hewlett Packard Company

20080115041 - Error correction method and apparatus for predetermined error patterns: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1)... Agent: Volentine & Whitt Pllc

20080115042 - Critical section detection and prediction mechanism for hardware lock elision: A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values... Agent: Intel Corporation C/o Intellevate, Llc

20080115043 - Semiconductor memory system and signal processing system: A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion... Agent: Rader Fishman & Grauer Pllc

  
05/08/2008 > patent applications in patent subcategories.

20080109675 - Remote logging mechanism: A method and system to remotely log debug information is described. A computer executing program code generates debug information upon the occurrence of an error in execution. The debug information is then sent to a remote computer using a network adaptor. In one embodiment, the computer executing the program is... Agent: Intel/blakely

20080109678 - System and method for intelligent data management: A system and method for intelligent data management enables the transport of items within a network by creating a first database defining a transport path of an item from an origin facility to a destination facility, and operations that affect the transport of items. In order to update the transport... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080109680 - Method and apparatus for testing web application, and comuter product: (A) “org.apache.struts.taglib.bean.WriteTag” written in a JAVA source segment is extracted as the tag class of a custom tag, “AddForm” in the segment is extracted as the attribute value of a name attribute, and “result” in the segment is extracted as the attribute value of a property attribute. (B) “<!--testStart expected=“5”-->... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20080109682 - Integrated circuit card with condition detector: An integrated circuit card includes a central processing unit, a memory and an abnormal condition detector. The memory stores data to be processed by the central processing unit. The abnormal condition detector detects whether at least one operating condition of the integrated circuit card is within one of a suspend... Agent: Volentine & Whitt Pllc

20080109683 - Automated error reporting and diagnosis in distributed computing environment: An apparatus, program product and method provide a generic error reporting and diagnosis framework that is readily suited for use in a wide variety of distributed computing environments, and that supports the autonomic reporting, diagnosis, and potentially the remediation of errors. The framework supports the encapsulation of symptomatic data associated... Agent: Wood, Herron & Evans, L.l.p. (ibm)

20080109684 - Baselining backend component response time to determine application performance: Deviation of expected response times is used to characterize the health of one or more backend machines invoked by an application to process a request. Performance data generated in response to monitoring application execution is processed to select backend response time data. The selected data is processed to predict future... Agent: Vierra Magen Marcus & Deniro LLP

20080109685 - Apparatus and method for providing error notification in a wireless virtual file system: An apparatus (20) provides a dynamically-generated audio and/or video error file upon the occurrence of an error condition in a wireless virtual file system (100). According to an exemplary embodiment, the apparatus (20) includes a host interface (22) for connecting to a host device (10) and a network interface (30)... Agent: Joseph J. Laks Thomson Licensing Llc

20080109686 - Failure diagnosis for logic circuits: A failure diagnosing method of logic circuits includes generating failure candidate data for logic circuits based on failure diagnosis data obtained from the logic circuits by using a failure diagnosis tool; and inputting the failure candidate data for the logic circuits. A predetermined data is extracted from each of the... Agent: Young & Thompson

20080109676 - Processing device and storage medium: Provided is a processing device capable of utilizing important data even if a trouble occurs. The information processing device comprises a storage device for storing a first basic program and data, start means for executing a second basic program, which is stored in a second storage unit at least logically... Agent: Staas & Halsey LLP

20080109677 - System and method for validating channel transmission: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one... Agent: Cooley Godward Kronish LLP Attn: Patent Group

20080109679 - Administration of protection of data accessible by a mobile device: The administration of protection of data on a client mobile computing device by a server computer system such as within an enterprise network or on a separate mobile computing device is described. Security tools are described that provide different security policies to be enforced based on a location associated with... Agent: King & Schickli, Pllc

20080109681 - Apparatus for adaptive problem determination in distributed service-based applications: A technique for problem determination in a distributed application is provided. Testing results of the application are first obtained through execution of test cases of a test group in the application. The testing of the application is then adaptively refined when the testing results have one or more failures, to... Agent: Ryan, Mason & Lewis, LLP

20080109687 - Method and apparatus for correcting data errors: The illustrative embodiments provide a computer implemented method and an apparatus for correcting data errors. An error correction unit receives data from a register. Responsive to receiving the data from the register, the error correction unit determines whether an error is present in the data. Responsive to identifying the error... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080109688 - Built in self test transport controller architecture: A built in self test circuit disposed within a memory matrix. Individual memory cells within the memory matrix are disposed into logical columns. The built in self test circuit has only one memory test controller, which is adapted to initiate test commands and receive test results. Transport controllers are uniquely... Agent: Lsi Corporation

20080109689 - Test system improving signal integrity by restraining wave reflection: A test system that tests a plurality of memories comprises a tester, a test board coupled to the tester, and a transmission line. The test board includes the plurality of memories. A transmission line connects the memories to each other in parallel. The test board includes a compensating unit that... Agent: Mills & Onello LLP

20080109690 - Test system employing test controller compressing data, data compressing circuit and test method: A test system employing a test controller compressing data, a data compressing circuit and a test method are provided. The test system includes a tester, a device under test (DUT), and a test controller receiving a first clock signal and serial data bits output from the DUT, compressing the serial... Agent: Volentine & Whitt Pllc

20080109691 - Method and apparatus for executing a bist routine: During a Built-In Self-Test (BIST) routine, execution of a sequence of tests is re-initiated after a corrective action is taken starting with the test having the highest re-ordered priority. The test having the highest re-ordered priority corresponds to a test in a sequence of tests that detected the error corresponding... Agent: Qualcomm Incorporated Patent Department

20080109692 - Reducing channel-change time: Systems and methods are disclosed herein for utilizing forward error correction (FEC) during a channel-change event. In one embodiment, among others, a method for executing a change from one communication channel to another includes receiving a channel-change indication and obtaining data and FEC that corresponds to the data. The data... Agent: Wm. Brook Lafferty Scientific-atlanta, Inc.

20080109693 - Harq transmission feedback for higher layer protocols in a communication system: A method is described for providing Hybrid Automatic Repeat Request (HARQ) transmission feedback to a higher layer protocol in a communication system. The method includes a step of detecting HARQ retransmissions in a first layer protocol. This can be used to determine a HARQ failure or an HARQ ACK after... Agent: Motorola, Inc.

20080109695 - Method and apparatus for performing multi-input multi-output transmission in a multi-input multi-output user equipment in a wireless communications system: A method for performing MIMO transmission in a UE capable of triggering at least one HARQ procedure in a wireless communications system is disclosed. The method includes selecting at least one HARQ process or at least one HARQ entity corresponding to a specified transmitter according to at least one transmission... Agent: Birch Stewart Kolasch & Birch

20080109694 - Method and apparatus for performing uplink transmission in a multi-input multi-output user equipment of a wireless communications system: A method for performing uplink transmission in a MIMO UE of a wireless communications system is disclosed. The UE is capable of triggering at least one HARQ procedure. The method includes configuring at least one receiver of the UE to receive at least one control or configuration message corresponding to... Agent: Birch, Stewart, Kolasch & Birch, LLP

20080109696 - Systems and methods for forward error correction in a wireless communication network: A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead and size.... Agent: Pulse-link, Inc.

20080109697 - Memory and method for checking reading errors thereof: A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data fragment from the memory... Agent: Rabin & Berdo, Pc

20080109698 - Hybrid min-sum decoding apparatus with low bit resolution for ldpc code: A new, improved method for mix min-sum decoding using a LDPC code is provided. In order to reconcile the drawbacks of the belief propagation (BP) and min-sum method, but at the same to keep the benefit of same, two major improvements have been proposed in the present invention. In the... Agent: Franklin (lin) Yang

20080109699 - Method, apparatus and computer program product providing for data block encoding and decoding: Methods, apparatus and computer program products are provided for encoding and/or decoding a data block. The method for encoding a data block includes the steps of: providing an information block of size k, I=(i0,i1, . . . i(k−1); and encoding the information block into a low-density parity-check (LDPC) codeword c... Agent: Harrington & Smith, Pc

20080109700 - Semiconductor memory device and data error detection and correction method of the same: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less... Agent: F. Chau & Associates, Llc

20080109701 - Turbo interference suppression in communication systems: Disclosed is a method and communication device for suppressing interference. The method comprises performing, with a turbo decoder (314), at least one turbo decoding attempt (1106) on a received signal (1104). The turbo decoding attempt generates at least one whole word code bit therefrom (1108). The whole word code bit... Agent: Motorola, Inc.

20080109702 - Methods of modulating error correction coding: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that... Agent: Winston & Strawn, LLP

20080109703 - Nonvolatile memory with modulated error correction coding: Data is stored in a nonvolatile memory so that different pages of data stored in the same memory cells are encoded according to different encoding schemes. A first page is decoded according to its encoding scheme and an output is provided based on the decoding of the first page that... Agent: Winston & Strawn, LLP

20080109704 - Data allocation in memory chips: In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a codeword in a single internal word of the memory device.... Agent: Hewlett Packard Company

20080109705 - Memory system and method using ecc with flag bit to identify modified data: A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080109706 - Error correction method and apparatus for optical information storage medium recording/reproducing apparatus: An error correction method and apparatus for use in an optical information storage medium recording/reproducing apparatus, in which an error data value is detected from the original data value stored in an external memory unit and a corrected data value for the error data value is updated to the external... Agent: Stein, Mcewen & Bui, LLP

20080109707 - Forward error correction encoding for multiple link transmission capatible with 64b/66b scrambling: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on... Agent: Ibm Microelectronics Intellectual Property Law

20080109708 - Apparatus and method for signal transmission/reception in a communication system: A method and an apparatus for transmitting a signal in a communication system are provided. An information vector is encoded according to a Low Density Parity Check (LDPC) encoding scheme, thereby generating an LDPC codeword. Minimum surviving check nodes are reserved for recovery of punctured nodes in the LDPC codeword.... Agent: The Farrell Law Firm, P.c.

20080109709 - Hardware-efficient, low-latency architectures for high throughput viterbi decoders: A low-latency, high-throughput rate Viterbi decoder implemented in a K1-nested layered look-ahead (LLA) manner, combines K1-trellis steps, with look-ahead step M, where K<K1<M, and K is the encoder constraint length. M can be an integer multiple or a non-integer multiple of one or both of K and K1. A K1-nested... Agent: Keshab K. Parhi

20080109710 - Viterbi decoding method: A decoding method relative to this application improves an error correction performance without increasing a memory. The decoding method includes obtaining a first decoded result from a first decoding path being on a trellis diagram; determining whether the first decoded result is incorrect or not; creating a second decoding path... Agent: Mcginn Intellectual Property Law Group, Pllc

20080109711 - Wireless communication system, wireless communication apparatus, wireless communication method, and computer program: A wireless communication system includes a first communication station configured to operate according to a first communication protocol, and a second communication station capable of operating according to both the first communication protocol and a second communication protocol. When the second communication station transmits a packet according to the second... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

  
05/01/2008 > patent applications in patent subcategories.

20080104441 - Data processing system and method: A method of kernel panic recovery, comprising detecting a kernel panic of a first kernel, retrieving at least some of a state of at least one thread running on the first kernel, and restoring the state of the at least one process on a second kernel.... Agent: Hewlett Packard Company

20080104443 - Information system, data transfer method and data protection method: Availability of an information system including a storage system that performs remote copy between two or more storage apparatuses and a host computer using such storage system is improved. A third storage apparatus including a third volume is coupled to a first storage apparatus, a fourth storage apparatus including a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080104448 - Testing apparatus for semiconductor device: A testing apparatus for semiconductor device comprises test controllers 10-1, 10-2, . . . , 10-N, variable clock generators 24-1, 24-2, . . . , 24-N which are provided respectively associated with the test controllers 10-1, 10-2, . . . , 10-N and which output variable clock signals having certain... Agent: Muramatsu & Associates

20080104450 - Computer system and control method thereof: A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and... Agent: Stanzione & Kim, LLP

20080104449 - Discrete device testing: One embodiment in accordance with the invention is a method that comprises testing a first number of physical devices using a first test sequence that comprises an item. A second number of physical devices are tested using a second test sequence. It is noted that the second test sequence comprises... Agent: Hitachi C/o Wagner Blecher LLP

20080104452 - Providing policy-based application services to an application running on a computing system: Methods, apparatus, products are disclosed for providing policy-based application services to an application running on a computing system. The computing system includes at least one compute node. The compute node includes an application and a plurality of application services of a service type. Providing policy-based application services to an application... Agent: Ibm (roc-blf)

20080104454 - System and method of error reporting in a video distribution network: Method, systems and devices for error reporting in a video distribution network are disclosed. A method may include determining that a network communication error has occurred in a video distribution network. The method may also include sending an error reporting interface to a video display. The method may also include... Agent: Toler Law Group

20080104442 - Method, device and system for automatic device failure recovery: Embodiments of the present invention provide a method, devices and a system for automatic device failure recovery. The method mainly includes: sending a recovery request message to a management device or a server; obtaining a program file used for failure recovery from the management device or the server; and performing... Agent: Sughrue Mion, PLLC

20080104446 - Hard disk drive data scrub methodology: Method, system and computer program product for reporting and recovering from uncorrectable data errors in a data processing system using the Advanced Technology Attachment (ATA) or the Serial ATA (SATA) protocol. The invention utilizes the data scrubbing functionality of SCSI hard drives to provide a higher level of data integrity... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104445 - Raid array: A method of providing a RAID array, comprising providing an array of disks (202a-202f), creating an array layout (200) comprising a plurality of blocks (D1-D26, P1-P10) on each of the disks (202a-202f) and a plurality of disk stripes (204a-204j) that can be depicted in the layout (200) with the stripes... Agent: Hewlett Packard Company

20080104444 - System including a plurality of data storage devices connected via network and data storage device used therefor: Embodiments of the present invention help improve the process for updating parities accompanied by the writing process. According to one embodiment, a host controller transmits a write command and new data to a hard disk drive (HDD). The HDD reads old data at a region where the new data are... Agent: Townsend And Townsend And Crew LLP

20080104447 - Diagnostic repair system and method for computing systems: A diagnostic system and method for repairing computing devices comprises a diagnostic application running on a same computing system having a failed operating system (O/S). The diagnostic application is provided with access to the file system of the failed O/S image. The diagnostic software application collects relevant configuration information from... Agent: Scully, Scott, Murphy & Presser, P.C.

20080104451 - Bootable post crash analysis environment: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080104453 - System and method to detect errors and predict potential failures: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults... Agent: Kenyon & Kenyon LLP

20080104455 - Software failure analysis method and system: A software failure analysis method for use following detection of a software failure on a computing system. The method includes collecting local data from the computing system pertaining to the failure, sending a request for comparison data to at least one other computing system, the request characterizing the comparison data... Agent: Hewlett Packard Company

20080104456 - Memory system including asymmetric high-speed differential memory interconnect: A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080104457 - Semiconductor integrated circuit device for display controller: The present invention is directed to repair a defective bit included in a memory in a semiconductor integrated circuit device for a display controller. The semiconductor integrated circuit device has a display memory capable of storing display data in a storage area, and a repair circuit capable of repairing a... Agent: Miles & Stockbridge PC

20080104458 - Semiconductor memory, system, testing method for system: A plurality of test patterns generated by a test pattern generator is output from a first memory chip to test a second memory chip, which is of a different type from the first memory chip and mounted in the same package. Therefore, when different types of memory chips are mounted... Agent: Arent Fox LLP

20080104460 - Medium defect detector and information reproducing device: A reproducing device performs error correction, detects a medium defect at an early stage and performs erasure correction. A reproducing device having an error correction circuit is provided with a medium defect detector. The medium defect detector computes a moving average value of the reproducing signal, slices this moving average... Agent: Greer, Burns & Crain

20080104459 - Non-volatile semiconductor memory device: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080104461 - Ate architecture and method for dft oriented testing: An ATE system is described for testing one or more DFT testing blocks contained in one or more DUTs when coupled to the ATE system. The ATE system includes hardware resources and software processes under the control of a DPK (Distributed Processing Kernel). The DPK couples the hardware resources and... Agent: Verigy, Ltd.

20080104463 - Method and system for testing chips: Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal... Agent: North America Intellectual Property Corporation

20080104462 - Serializer/de-serializer bus controller inferface: An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed... Agent: Kathy Manke Avago Technologies Limited

20080104464 - Method and apparatus for controlling access to and/or exit from a portion of scan chain: The present invention provides a method, apparatus and program product for providing controlled access to and/or exit from a portion of a scan chain. The method, apparatus, and program product take advantage of a first controlling device placed within the scan chain prior to the portion of the scan chain... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20080104465 - Failure simulation based on system level boundary scan architecture: A method and apparatus for reducing cost for the backplane and system test and for speeding up the time to market of a new product is disclosed. A failure simulation based on system level Boundary Scan architecture allows the use of an already available test infrastructure.... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20080104466 - Method and apparatus for testing embedded cores: The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to... Agent: Fish & Richardson, PC

20080104467 - Timing failure remedying apparatus for an integrated circuit, timing failure diagnosing apparatus for an integrated circuit, timing failure diagnosing method for an integrated circuit, integrated circuit, computer readable recording medium recorded thereo: A timing failure remedying apparatus for an integrated circuit has a comparator which compares a value captured in a taking-out scan chain for reference through an operation of a processing core for reference according to a first clock signal with a value captured in a taking-out scan chain to be... Agent: Staas & Halsey LLP

20080104468 - Process for improving design limited yield by efficiently capturing and storing production test data for analysis using checksums, hash values, or digital fault signatures: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.... Agent: Patentry

20080104469 - Apparatus and method for using a single bank of efuses to successively store testing data from multiple stages of testing: An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080104471 - Method and apparatus for testing an ic device based on relative timing of test signals: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC... Agent: Hewlett Packard Company

20080104470 - Methods and apparatus for diagnosing a degree of interference between a plurality of faults in a system under test: A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test, includes: 1) for each of the plurality of faults, and for each of a plurality of... Agent: Agilent Technologies Inc.

20080104472 - Parameter setting with error correction for analog circuits: A system and method for setting analog circuit parameters requires providing a first set of data bits which represent the parameters to be set, deriving a first set of error correction bits from the values of the data bits in accordance with a predefined algorithm which enables the detection of... Agent: Koppel, Patrick & Heybl

20080104473 - Rendering and correcting data: Rendering and correcting data. Data is received. The data is stored at a memory. The data is rendered for presentation at an output device. Defects in the data stored at the memory are determined. The defects in the data stored at the memory are corrected, wherein at least a portion... Agent: Hewlett Packard Company

20080104474 - Low density parity check (ldpc) decoder: A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter demodulates the down-converted signal and provides a demodulated signal to the LDPC decoder. The LDPC decoder has a partially parallel architecture... Agent: Joseph J. Laks Thomson Licensing LLC

20080104475 - Method and apparatus for encoding and decoding high speed shared control channel: A method and apparatus for encoding and decoding high speed shared control channel (HS-SCCH) data are disclosed. For part 1 data encoding, a mask may be generated using a wireless transmit/receive unit (WTRU) identity (ID) and a generator matrix with a maximum minimum Hamming distance. For part 2 data encoding,... Agent: Volpe And Koenig, P.C. Dept. Icc

20080104477 - Method for performing error corrections of digital information codified as a symbol sequence: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is... Agent: Stmicroelectronics, Inc.

20080104476 - Method, system, and apparatus for adjacent-symbol error correction and detection code: A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases.... Agent: Caven & Aghevli C/o Intellevate

20080104478 - Method and system for providing a contention-free interleaver for channel coding: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, {right arrow over (v)}, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave... Agent: Docket Clerk

20080104479 - Symbol error correction by error detection and logic based symbol reconstruction: Methods and apparatus for creating codewords of n-valued symbols with one or more n-valued check symbols are disclosed. Associating the codewords with a matrix allows for detection of one or more symbols in error and the location of such symbols in error. Methods to reconstruct symbols in error from other... Agent: Diehl Servilla LLC

20080104481 - Encoding device, decoding device, encoding/decoding device and recording/reproducing device magnetic head and method of producing the same: An encoding/decoding device corrects errors by concatenated codes of an ECC code and a parity code to prevent an increase in the circuit scale and to improve error correction performance. The device has encoders for creating a concatenation type encoded data by interleaving a data string into a plurality of... Agent: Greer, Burns & Crain

20080104480 - Method for processing noise interference: A method for processing noise interference in a serial AT Attachment (SATA) interface. The method includes the steps of detecting whether there is an error in CRC (Cyclic Redundancy Check) checksum or whether an R_ERR primitive (reception error primitive) is received, detecting whether a FIS (Frame Information Structure) is a... Agent: Birch Stewart Kolasch & Birch

20080104482 - Turbo decoder employing arp (almost regular permutation) interleave and arbitrary number of decoding processors: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still... Agent: Garlick Harrison & Markison

20080104483 - Error corrector with a high use efficiency of a memory: An error corrector with a high use efficiency of a memory includes a memory, a bus device, an input buffer and an error correction module. The memory stores data. The bus device controls a memory access. The input buffer receives and temporarily stores a coded blockcode data, and writes the... Agent: Bacon & Thomas, PLLC

20080104484 - Mass storage system and method: There is provided a system and method of mass storage. The method includes dividing storage units into standard sized blocks and upon receiving a write request from an application, generating EDC data for user application data associated with the write request. The method also includes compressing the user application data... Agent: Hewlett Packard Company

20080104485 - Data communications methods and apparatus: In an embodiment, a source device encodes source information corresponding to a frame, assembles an initial data frame that includes the encoded data blocks, and transmits the initial data frame to a destination device. The destination device decodes the encoded data blocks and assembles a restored version of the initial... Agent: Schwegman, Lundberg & Woessner, P.A.

20080104486 - Decoder and reproducing device: A reproducing device performs decoding by propagating the reliability, and detects micro medium defects to correct the reliability information. The decoder has an internal decoder, external decoder and a defect detector which calculates a moving average value of a soft-input signal, acquires a scaling factor from this, and manipulates the... Agent: Greer, Burns & Crain

20080104487 - Error detection apparatus and error detection method: When error bit position information EbP sequentially selected from a register 51 is an error bit position, such a syndrome that an LSB of an error byte position is an error bit position is output from a syndrome storage unit 52 to an adder 54 and added and stored in... Agent: Staas & Halsey LLP

20080104488 - Sliding window method and apparatus for soft input/soft output processing: In one or more embodiments, a method of processing a soft value sequence according to an iterative soft-input-soft-output (SISO) algorithm comprises carrying out sliding-window processing of the soft value sequence in a first iteration using first window placements and in a second iteration using second window placements, and varying the... Agent: Coats & Bennett, PLLC

20080104489 - Maximum likelihood detector, error correction circuit and medium storage device: A maximum likelihood decoder creates a decoding target data string and provides error candidates that are effective for an error correction circuit. The decoder has a detector for creating a decoding target data string, and an error candidate extractor for extracting the bit positions of which likelihood of each bit... Agent: Greer, Burns & Crain

20080104490 - Digital data decoding apparatus and digital data decoding method: According to one embodiment, a digital data decoding apparatus calculates branch metrics of all paths in an input data series from the path at a state of a current time to the path at a state of a next time, and obtains path metrics of all the paths up to... Agent: Knobbe Martens Olson & Bear LLP

20080104491 - Safe transmission using non-safety approved equipment: A communications method useable to safely communicate a message or a signal from a first safety approved entity (210) to a second safety approved entity (230) via a third, non-safety approved entity (220) comprising that each command is sent with the aid of a command message from the first to... Agent: Albihns Stockholm Ab

20080104492 - Data processing: A method of generating a checksum for a data message comprises processing the data message to extract data blocks therefrom and computing a checksum from the data blocks. In particular non-linear operators are applied to the data blocks. As a result improved fault-detection and speed of processing is obtained... Agent: Osha Liang L.L.P.

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