Error detection/correction and fault detection/recovery inventions 04/08

20080098262 - Performing diagnostic operations upon an asymmetric multiprocessor apparatus: An asymmetric multiprocessor apparatus 2 is provided in which respective slave diagnostic units 20, 22, 24 are associated with corresponding execution mechanisms 6, 8, 10. A master diagnostic unit 26 tracks the migration of thread execution between the different execution mechanisms 6, 8, 10 so that the execution of a... Agent: Nixon & Vanderhye, PC

20080098263 - Test apparatus and method for testing booting and shutdown process of computer system: A test apparatus for testing a booting and shutdown process of a computer system provided. The test apparatus includes a power control unit and a test control unit. The power control unit is for receiving AC power, and selectively outputting the AC power to a power supply end of the... Agent: Bacon & Thomas, PLLC

20080098255 - Communication management apparatus and communication management method: A transmitting/receiving unit receives a SIP signal after occurrence of trouble in a SIP server and outputs a call ID of the SIP signal to a recovery-file searching unit. A session control unit once again procures a call process resource and an instance for a session corresponding to a recovery... Agent: Katten Muchin Rosenman LLP

20080098256 - Computer readable storage medium for migratable services: A migration framework provides for the migration of services in a cluster. A migratable target contains a list of servers in the cluster capable of hosting a migratable service. A migration manager can migrate the service between servers in the migratable target, and can activate an instance of the service... Agent: Fliesler Meyer LLP

20080098257 - Multiple execution-path system: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the... Agent: Quarles & Brady LLP

20080098258 - Method, system, and program for error handling in a dual adaptor system where one adaptor is a master: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098259 - Method, system, and program for error handling in a dual adaptor system where one adaptor is a master: Provided is a method, system, and program for processing Input/Output (I/O) requests to a storage network including at least one storage device and at least two adaptors, wherein each adaptor is capable of communicating I/O requests to the at least one storage device. An error is detected in a system... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098260 - Methods and apparatus for handling processing errors in a multi-processing system: Methods and apparatus are provided for: monitoring processor tasks and associated processor loads therefor that are allocated to be performed by respective sub-processing units associated with a main processing unit; detecting whether a processing error has occurred in a given one of the sub-processing units; re-allocating all of the processor... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20080098261 - Adaptive recovery from system failure for application instances that govern message transactions: Mechanisms for adaptively entering and exiting recovery mode. When a message is received from a particular message transaction, the appropriate processing instance is loaded from persistent memory to system memory. The processing instance then determines from its own state information whether or not it is in recovery mode. This indication... Agent: Workman Nydegger/microsoft

20080098264 - Program debug method and apparatus: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to... Agent: George W Carr 670 Founders Square

20080098265 - System and method for embedded java memory footprint performance improvement: A system and method are provided to allow demand loading and discarding of Java executable image (JXE) files. The virtual machine allocates an address space for a requested JXE program. The read-only portion of the JXE file is memory mapped from its nonvolatile location to the allocated memory space using... Agent: Joseph T. Van Leeuwen

20080098266 - Reduced signaling interface method and apparatus: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a... Agent: Texas Instruments Incorporated

20080098267 - Semiconductor ic and testing method thereof: According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112, a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit... Agent: Steptoe & Johnson LLP

20080098268 - Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection: In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.... Agent: Ibm Corporation C/o Sally Redfern

20080098269 - Mechanism for concurrent testing of multiple embedded arrays: In one embodiment, an apparatus and method for concurrent testing of multiple embedded arrays is disclosed. In one embodiment, the apparatus comprises a built-in self test (BIST) engine coupled to a plurality of arrays having different sizes to generate test packets targeted to an array with the most entries among... Agent: Intel/blakely

20080098270 - Method for determining time to failure of submicron metal interconnects: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20080098271 - System and method for verification and generation of timing exceptions: The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing... Agent: 24ip Law Group Usa, PLLC

20080098272 - Networked test system: An automatic test system that can be configured to perform any of a number of test processes. The test system contains multiple functional modules that are interconnected by a network. By using software to configure data flow between functional modules, combinations of modules can be made, thereby creating virtual instruments.... Agent: Teradyne, Inc. C/o Wolf, Greenfield & Sacks, P.C.

20080098273 - Method and apparatus for encoding and decoding data: A method and apparatus for turbo coding and decoding is provided herein. During operation, a concatenated transport block (CTB) of length X is received and a forward error correction (FEC) block size KI is determined from a group of available non-contiguous FEC block sizes between Kmin and Kmax, and wherein... Agent: Motorola, Inc.

20080098274 - Data transmission apparatus and method: Provided are a data transmission apparatus and method which apply an appropriate coding rate according to significance of bits or bit groups included in uncompressed data and retransmit all or part of the data when a transmission error occurs in the data while the data is being transmitted over a... Agent: Sughrue Mion, PLLC

20080098275 - System and program product for error recovery while decoding cached compressed data: A system and program for decoding cached compressed data. Compressed data is received and decoded. An error is detected while decoding a first location in the compressed data. A reentry data set is accessed having a pointer to a second location in the compressed data following the first location and... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20080098276 - Semiconductor integrated circuit: The present invention provides a data transmission method capable of suppressing degradation in data rate while improving a bit error rate of transmission data, and transmitters and receivers employed in the data transmission method. On the transmitting side, a CRC bit is added to an input information bit sequence in... Agent: Volentine & Whitt PLLC

20080098277 - High density high reliability memory module with power gating and a fault tolerant address and command bus: A high density high reliability memory module with power gating and a fault tolerant address and command bus. The memory module includes a rectangular printed circuit board having a first side and a second side, a length of between 149 and 153 millimeters and first and second ends having a... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080098278 - Multiplier product generation based on encoded data from addressable location: For one disclosed embodiment, an apparatus comprises first circuitry to output encoded data from an addressable location based at least in part on an address corresponding to a first number, wherein the encoded data is based at least in part on data that corresponds to the first number and that... Agent: Intel Corporation C/o Intellevate, LLC

20080098279 - Using no-refresh dram in error correcting code encoder and decoder implementations: Embodiments of the present invention provide Forward Error Correcting Code encoders and decoder structures that use DRAM in their memory designs. DRAM is a very attractive memory options in many electronic systems due to the high memory density provided by DRAM. However, the DRAM is typically not included in ASIC... Agent: Townsend And Townsend And Crew, LLP

20080098280 - N-dimensional iterative ecc method and apparatus with combined erasure - error information and re-read: In an iterative error correction method and apparatus for correcting errors in digital data read from a storage medium, re-reads are combined with the error correction procedure in a single error recovery procedure. The data read from the storage medium are represented as a multi-dimensional data structure, and the error... Agent: Schiff Hardin, LLP Patent Department

20080098281 - Using sam in error correcting code encoder and decoder implementations: SAM is a very attractive memory option for systems due to its higher speed and reduced area when compared to RAM. However it is generally not used in implementations of FECCs due to its limitation to sequential accesses. According to the present invention, Forward Error Correcting Code encoder and decoder... Agent: Townsend And Townsend And Crew, LLP

20080098282 - High speed error correcting system: Disclosed is an error correcting system, which comprises: a demodulator, for receiving and demodulating data from the optical disc to generate input data; a data buffer, for storing the input data; an on the fly ECC decoder, for performing a PI error correction to the input data before the input... Agent: North America Intellectual Property Corporation

20080098283 - Outer coding methods for broadcast/multicast content and related apparatus: Transmission techniques are provided that improve service continuity and reduce interruptions in delivery of content that can be caused by techniques that occur when the User Equipment (UE) moves from one cell to the other, or when the delivery of content changes from Point-to-Point (PTP) connection to a Point-to-Multipoint (PTM)... Agent: Qualcomm Incorporated

20080098284 - Systems, methods, apparatus, and computer program products for providing forward error correction with low latency: Systems, methods, apparatus and computer program products for providing forward error correction with low latency to live streams in networks are provided, including outputting source data at a rate less than the rate of a source stream, building a buffer, FEC decoding the source data; and outputting the packets at... Agent: Fitzpatrick Cella Harper & Scinto

20080098285 - Apparatus for random parity check and correction with bch code: An apparatus for random parity check and correction with BCH code is provided, including a BCH parity check code encoder, a channel, a BCH parity check code decoder, and a static RAM (SRAM). The BCH parity check code encoder uses the BCH encoding to encode the parity check code in... Agent: Madson & Austin

20080098286 - Irregular systematic with serial concatenated parity codes: Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of bits using systematic bits as input, repeating the plurality of bits of the outer code a pre-determined number of times to generate at least... Agent: Fish & Richardson, PC

20080098287 - Detection and mitigation of temporary impairments in a communications channel: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses... Agent: Mcandrews Held & Malloy, Ltd

20080098288 - Forward decision aided nonlinear viterbi detector: A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal... Agent: Ropes & Gray LLP

20080091970 - Information processing system and method: In information processing between computers which perform a remote operation via a network, all or a part of process information being executed by an operation target and data for use in a process are transmitted beforehand to an operation unit, and the operation unit continues the processing by use of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080091972 - Storage apparatus: Proposed is a storage apparatus capable of alleviating the burden of maintenance work when a failure occurs in a part configuring the storage apparatus. This storage apparatus includes multiple disk drives and spare disk drives, and multiple controllers. When a failure occurs, this storage apparatus determines the operability status of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080091971 - Stored data processing apparatus, storage apparatus, and stored data processing program: A storage apparatus performs at least write processing for a storage medium. On the storage medium, data is allocated in units of a first block having a predetermined data length, the first block is allocated in units of a second block constituted by a plurality of the first blocks, and... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20080091974 - Device for controlling a multi-core cpu for mobile body, and operating system for the same: Temperatures of four CPU cores of a multi-core CPU of a mobile body are detected. If the detected temperatures of the CPU cores become high, a clock setting register in a CPU clock-forming unit is set to the highest multiplying factor, and the CPU clock multiplying factors of the other... Agent: Posz Law Group, PLC

20080091975 - Method and system for side-channel testing a computing device and for improving resistance of a computing device to side-channel attacks: Our invention presents an effective method and system which are used to perform side-channel testing of computing devices, as well as to improve resistance of computing devices against side-channel attacks.... Agent: Yevgeniy Polulyakh

20080091976 - Methods and apparatus for network re-creation in controlled environments: Methods and apparatus for network re-creation in controlled environments. In an aspect, a method for network re-creation is provided. The method includes determining a logging window, logging at least one re-creation parameter during the logging window to produce a re-creation log, and storing the re-creation log. In an aspect, an... Agent: Qualcomm Incorporated

20080091978 - Apparatus, system, and method for database management extensions: An apparatus, system, and method are disclosed for evaluating database accesses. The apparatus may comprise a computer program that causes a computer system to exchange profiling data between a client application module and a database module; execute a database access; determine a database access policy violation at a detection point... Agent: Kunzler & Mckenzie

20080091981 - Process for improving design-limited yield by localizing potential faults from production test data: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based... Agent: Patentry

20080091983 - Dynamic account provisions for service desk personnel: The present invention describes an automated process that enables dynamic provisioning (both creation and deletion) of administrative accounts based upon a real-time need as defined by service desk processes and procedures. This invention enhances current provisioning of administrative account processes that are typically handled by service desk personnel that constantly... Agent: Ibm Corporation C/o Darcell Walker, Attorney At Law

20080091969 - Semiconductor integrated circuit including memory macro: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros 1A1 and 1A2 includes a memory cell array 1A-3 connected to word lines WL1 to WL32... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080091973 - Configuring cache memory from a storage controller: Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first cluster including a first processor and a first cache, and a second cluster including a second processor and a second cache.... Agent: Scully, Scott, Murphy, & Presser, P.C.

20080091977 - Methods and apparatus for data analysis: Methods and apparatus for data analysis according to various aspects of the present invention identify statistical outliers in data, such as test data for components. The outliers may be identified and categorized according to the distribution of the data. In addition, outliers may be identified according to multiple parameters, such... Agent: Noblitt & Gilmore, LLC.

20080091979 - Semiconductor memory device and test method: A semiconductor device includes memory mats each including a plurality of memory cells to store information code or error correcting code. An error correcting circuit corrects an error of the information code by one correction unit of a predetermined number of information codes. A parallel test mode activates and tests... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080091980 - Method and system for validating pci/pci-x adapters: An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20080091982 - Storage controller and a method for recording diagnostic information: A storage controller (104) for a storage system (100) in which there are multiple storage devices (109) and a method for recording diagnostic information are provided. The storage controller (104) includes a storage device manager (203) which has means for allocating a storage device (109) in the storage system (100)... Agent: Dillon & Yudell, LLP

20080091984 - Method and system for concurrent error identification in resource scheduling: A method and system for handling real-time indications of resource scheduling conflicts. In one embodiment, the method includes a computer system including a user interface, display, processor, and some form of memory. Contained within the memory is a resource scheduling process that analyzes resource data, scheduling criteria, and work parameters... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080091985 - System and method for capturing significant events at web portlets: System and method for logging significant events occurring at a web site portal includes a base class portlet service including a significant event catcher method having a register method and a record method, a portlet action table, and an action description table. The register method is called during portlet initialization... Agent: Shelley M Beckstrand, P.C.

20080091986 - Method and apparatus for encoding and decoding data: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K′ is determined that is related to K″, where K″ from a set of sizes; wherein the set of sizes comprise K″=ap×f, pmin≦p≦pmax; fmin≦f≦fmax,... Agent: Motorola, Inc.

20080091987 - Circuit designing program and circuit designing system having function of test point insetion: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for... Agent: Mcginn Intellectual Property Law Group, PLLC

20080091988 - Memory repair system and method: A self-repairing memory system includes memory including memory elements and redundant memory elements. The memory elements include a plurality of memory cells. A memory repair module identifies non-operational memory cells and selects at least one memory element including the non-operational memory cells. A first repair sub-circuit soft repairs the memory... Agent: Harness, Dickey & Pierce P.L.C

20080091989 - System and method for testing memory blocks in an soc design: A system and method for testing a plurality of memory blocks in a System on Chip (SOC) design uses two Test Access Ports (TAPs), a user TAP and an EDA tool TAP, to provide instructions and test data to the SOC. The system includes a glue logic block, a secured... Agent: Freescale Semiconductor, Inc. Law Department

20080091990 - Controlled reliability in an integrated circuit: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable... Agent: Freescale Semiconductor, Inc. Law Department

20080091991 - Method and apparatus for performing logical compare operation: A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first data and a second data. The processor performs logical comparisons on... Agent: Trop Pruner & Hu, PC

20080091993 - On-board fifo memory module for high speed digital sourcing and capture to/from dut (device under test) using a clock from dut: In a method and system for testing, a tester (110) is operable to communicate test signals (124, 126) at a tester clock speed, and a device (190) to be tested is operable to communicate the test signals (124, 126) at a device clock speed, the device clock speed being greater... Agent: Texas Instruments Incorporated

20080091992 - Tri-level test mode terminal in limited terminal environment: A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input... Agent: Zagorin O'brien Graham LLP

20080091994 - Test system for integrated circuits: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080091995 - Progressive random access scan circuitry: A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one... Agent: Brinks Hofer Gilson & Lione

20080091996 - Single event upset test circuit and methodology: A method, involving: inputting an initial data pattern into a scan chain circuit of an integrated circuit device; applying a particle beam to the integrated circuit device, while driving the scan chain circuit with a clock signal, to generate an output data pattern; and generating a single event upset error... Agent: Bainwood Huang & Associates LLC

20080091997 - Systems and methods for improved scan testing fault coverage: Systems and methods for improved fault coverage of logic built-in-self-tests (LBISTs) in integrated circuits (ICs) which ensure testing of specific logic by forcing specific values into scan latches that contain otherwise pseudorandom test bit patterns. In one embodiment, an LBIST system comprises a plurality of scan latches and forcing logic... Agent: Law Offices Of Mark L. Berrier

20080091998 - Partial enhanced scan method for reducing volume of delay test patterns: A method includes selecting at least one regular scan cell that is replaced with a corresponding one of an enhanced scan cell in a scan chain for scan based delay testing of the digital circuit, controlling the enhanced scan cell with a skewed load approach, and controlling regular scan cells... Agent: Nec Laboratories America, Inc.

20080091999 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the... Agent: Ibm Corporation Department 417

20080092000 - Delay circuit, jitter injection circuit, and test apparatus: There is provided a delay circuit that delays and outputs a given input signal. The delay circuit includes a first delaying section that delays the input signal, a second delaying section that further delays the input signal delayed by the first delaying section, and a delay setting section that sets... Agent: Smith, Gambrell & Russell

20080092001 - Method and device for data communication: A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control... Agent: GlobalIPServices, PLLC

20080092002 - Semiconductor integrated circuit and control method thereof: A semiconductor integrated circuit includes a target circuit configured to operate in a normal mode, to form a scan chain to serially transfer a test data through the scan chain, in a scan path test mode, and to form a plurality of sub scan chains to save an internal node... Agent: Mcginn Intellectual Property Law Group, PLLC

20080092003 - Diagnostic information capture from logic devices with built-in self test: From a logic device comprising logic circuits and a built-in self-test system (BIST) comprising scan chains, diagnostic information is obtained by using the scan chains to apply a stimulus vector to the logic circuits, to capture responses of the logic circuits to the stimulus vector and to shift the captured... Agent: Agilent Technologies Inc.

20080092004 - Method and system for automated path delay test vector generation from functional tests: Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit... Agent: Barry W. Chapin, Esq. Chapin Intellectual Property Law, LLC

20080092005 - Scan testing interface: A system, method, and computer program product for scan testing a device under test (DUT). In one embodiment, compressed test data comprising packets are received at a serial test data input. The packets contain encoded data characterizing a test data bit stream and each includes a bucket select field and... Agent: Dillon & Yudell LLP

20080092006 - Optimizing a set of lbist patterns to enhance delay fault coverage: A method and system for mitigating the impact of voltage supply variations on logic built-in self-test (LBIST) results. The method includes, but is not limited to: creating a set of customized LBIST activation patterns during IC design; propagating the activation patterns from the scan-able latches through the non-scan latches to... Agent: Dillon & Yudell LLP

20080092007 - Data communication device and method: A method is described for transferring data from an unsecured computer to a secured computer. The method includes transmitting the data and then receiving the data. Next, it is determined if errors were introduced when the data was transmitted by the unsecured computer or received by the secured computer. If... Agent: Sughrue Mion, PLLC

20080092008 - Buffer compression in automatic retransmisson request (arq) systems: A method and system for improving buffer compression in automatic retransmission request (ARQ) systems includes both a compander and decompander for further processing data. A received data string k bits in length is first companded according to a predetermined companding scheme. The companded data string is reduced to a length... Agent: Synnestvedt & Lechner, LLP

20080092010 - Error correction code decoding device: An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and... Agent: Young & Thompson

20080092011 - Turbo decoding apparatus: A turbo decoding apparatus comprises: a backward-probability calculation unit that executes backward-probability calculation from time N to time 0 with respect to coded data having an information length N which is encoded with turbo-encoding; a storage unit to store backward-probability calculation results extracted from a plurality of continuous backward-probability calculation... Agent: Bingham Mccutchen LLP

20080092009 - Error correction coding apparatus and error correction decoding apparatus: An error correction coding apparatus includes a frame generating unit for buffering inputted information sequence data in frame buffers which correspond to units to be coded, respectively, a first interleaving unit for rearranging the information sequence data within two or more of the frame buffers, a first coding unit for... Agent: Birch Stewart Kolasch & Birch

20080092012 - Robust digital communication system: Normally ordered robust VSB data are reordered in accordance with a first interleave to produce reordered robust VSB data. The reordered robust VSB data and ATSC data are reordered in accordance with a second interleave to produce normally ordered robust VSB data and reordered ATSC data. The normally ordered robust... Agent: Zenith Electronics Corporation

20080092013 - System and method for interleaving data in a communication device: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080092014 - Methods of adapting operation of nonvolatile memory: In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one... Agent: Winston & Strawn, LLP

20080092015 - Nonvolatile memory with adaptive operation: In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one... Agent: Winston & Strawn, LLP

20080092016 - Memory system and method using partial ecc to achieve low power refresh and fast access to data: A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and... Agent: Dorsey & Whitney LLP Intellectual Property Department

20080092017 - Erasure pointer error correction: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block to allow for more efficient processing and... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.

20080092018 - Tail-biting turbo code for arbitrary number of information bits: Tail-biting turbo code for arbitrary number of information bits. A novel means is presented in which, for most cases, no extra symbols at all need to be padded to an input sequence to ensure that a turbo encoder operates according to tail-biting (i.e., where the beginning and ending state of... Agent: Garlick Harrison & Markison

20080092019 - Supporting a decoding of frames: For supporting a decoding of encoded frames, which belong to a sequence of frames received via a packet switched network, it is detected whether a particular encoded frame has been received after a scheduled decoding time for the particular encoded frame and before a scheduled decoding time for a next... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080092020 - Determining message residue using a set of polynomials: A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Portfolio Ip

20080092021 - System and method for performing reed-solomon encoding: An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080092022 - Non-redundant multi-error correcting binary differential demodulator: An algorithm for a non-redundant multi-error correcting binary differential demodulator simplifies error detection and reduces memory requirements in circuits embodying the same. The demodulator includes a differential detectors (DD) module, an error signal generator (ESG) module, and an error detection-and-correction (EDAC) module. The DD module receives modulated binary input at... Agent: Albin H. Gess, Esq. Snell & Wilmer L.L.P.

20080092023 - Parallel convolutional encoder: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel... Agent: Stolowitz Ford Cowger LLP

20080092024 - System for identifying localized burst errors: A system for detecting one or more localized burst errors in a receiving message comprised of a plurality of codewords. The system comprises a trellis code decoder for decoding a receiving message with a plurality of codewords and calculating one or more cumulative metrics of a maximum likelihood path and... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080092025 - Method and system for improving decoding efficiency in wireless receivers: The present invention discloses a method and system for improving the decoding efficiency in a wireless receiver to obtain a correct decoded data string. The method comprises generating an active state metric matrix of a receiving codeword, calculating a differential metric matrix pertinent to the active state metric matrix, identifying... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080092026 - Methods of soft-input soft-output decoding for nonvolatile memory: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an... Agent: Winston & Strawn, LLP

20080092028 - Deconding device and decoding method: A decoding device includes a BM calculator calculating a branch metric in a Log-MAP algorithm from received data and extrinsic information, an ACS operator calculating a maximum value of a path metric based on the branch metric, a correction term calculator calculating a Jacobian correction value of the path metric,... Agent: Young & Thompson

20080092027 - Method and system for memory partitioning: Systems and methods for interleaver and deinterleaver memory partitioning optimize data rate and error correction. Optimized memory allocation is important in systems that support bi-directional communication over multiple data paths. By using path-specific information such as impulse noise protection and data rate, memory may be dynamically partitioned to optimize the... Agent: Mcandrews Held & Malloy, Ltd

20080092029 - Method and apparatus for encryption with raid in storage system: The described methodology provides users with the ability to specify flexible encryption options in a storage system using RAID technology. The users can use the system to achieve a configuration which achieves a desired balance between security and system load/performance. Specifically, one aspect of the methodology enables the user to... Agent: Sughrue Mion, PLLC

20080092030 - Method and apparatus for template based parallel checkpointing: A method and apparatus for a template based parallel checkpoint save for a massively parallel super computer system using a parallel checksum algorithm such as rsync. In preferred embodiments, the checkpoint data for each node is compared to a template checkpoint file that resides in the storage and that was... Agent: Martin & Associates, LLC

20080086657 - Method and system for disaster recovery in a secure reprogrammable system: Methods and systems for software security in a secure communication system are disclosed and may include verifying downloaded code in a reprogrammable system and reloading prestored unmodifiable first stage code upon failure. The prestored unmodifiable first stage code, which may comprise boot code for the reprogrammable system, may be stored... Agent: Mcandrews Held & Malloy, Ltd

20080086658 - Backup control device and system for data processing system: The control device includes a queuing unit to process data backup process requests received from a plurality of devices and administrating an execution sequence, and an execution control processing unit executing a plurality of backup processes administrated in the queuing unit within a range of a predetermined value. Jobs are... Agent: Staas & Halsey LLP

20080086659 - Data processing apparatus and program: a control section adapted to start saving of the data in the volatile memory into the nonvolatile memory when the detecting circuit has output the momentary interruption detecting signal, continue save of the data, and carry out a predetermined shutdown processing when the detecting circuit has output the power failure... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080086660 - Test data management: Methods and apparatuses enable generating test content for test system from an executed transaction of an execution system. The data resulting from the execution of the transaction in the execution system is accessed and used to generate test content for a test case. The test case can include the transaction... Agent: Sap/blakely

20080086661 - Methods, systems, and computer program products for providing network outage information: Exemplary embodiments relate to methods, systems, user devices and computer program products for providing network status information. Methods include receiving alarm data for an event from a plurality of sources. The alarm data includes a plurality of alarm records each including a site identifier. The alarm data is processed to... Agent: Cantor Colburn LLP - Bellsouth

20080086662 - Link adaptation for retransmission error-control technique transmissions: Embodiments of the present invention provide for link adaptation computations accounting for retransmission error-control techniques to be employed in transmission sequences utilizing the adapted link. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.c.

20080086663 - Test pattern generating circuit and semiconductor memory device having the same: Provided are a test pattern generating circuit which generates test patterns having various types and lengths and a semiconductor memory device which performs a test operation using the test pattern generating circuit. The test pattern generating circuit includes a plurality of register blocks which receive test signals input from an... Agent: Volentine & Whitt Pllc

20080086664 - Tester input/output sharing: In one implementation, a method of testing multiple DUTs using a single tester channel is provided which includes providing an input signal with the single tester channel simultaneously to each of the DUTs. The method further includes providing a clock signal to each of the DUTs. The clock signal provided... Agent: Balzan Intellectual Property Law, Pc

20080086665 - Semiconductor integrated circuit and testing method: A semiconductor integrated circuit includes: an input/output cell that is included in a path captured during propagation delay testing and that has an output-stage buffer on an output bus; and a terminal connected to the output bus and an input bus of the input/output cell. An external load or a... Agent: Arent Fox LLP

20080086666 - Analyzer: The analyzer according to the present invention is an analyzer having a scan test function, and including scan paths each having flip-flops which function as a shift register when a scan test is performed, and a switching unit operable to switch between a first connection state, and a second connection... Agent: Greenblum & Bernstein, P.L.C

20080086667 - Chip testing device and system: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output... Agent: Birch Stewart Kolasch & Birch

20080086668 - Model-based testing method and system using embedded models: A testing system and various methods involving testing of a device under test (DUT) use a device model to model a stimulus-response behavior of a the DUT. The testing system includes a device model of the DUT that is fitted to the stimulus-response behavior of the DUT and a measurement... Agent: Agilent Technologies Inc.

20080086669 - Optimal error protection coding for mimo ack/nack/post information: Error protection based on a nonlinear code set may be used in a multiple input multiple output (MIMO) radio communications system. A decoder decodes received MIMO data streams and generates an automatic repeat request (ARQ) message for data units received for the MIMO data streams for each transmission time interval.... Agent: Nixon & Vanderhye, Pc

20080086671 - System and method for reducing power consumption in a low-density parity-check (ldpc) decoder: A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode... Agent: Freescale Semiconductor, Inc. Law Department

20080086670 - Channel estimation and fixed thresholds for multi-threshold decoding of low-density parity check codes: A method and apparatus are provided for error correction of a communication signal. A multiple fixed threshold scheme for iteratively decoding a received codeword includes making a comparison with a threshold to generate a reconstructed version of the received codeword. The threshold has at least two different values that at... Agent: Schwegman, Lundberg & Woessner, P.a.

20080086673 - General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave arp (almost regular permutation) of all possible sizes: General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes. A novel means is presented in which contention-free memory mapping is truly achieved in the context of performing parallel decoding of a turbo coded signal. A novel means of... Agent: Garlick Harrison & Markison

20080086675 - Method and system for ldpc code erasure decoding: The present invention relates to a method for LDPC code erasure decoding, including: generating a first code word through setting a value as a value in Galois field having two elements GF(2) at each of erasure locations in a received code word; generating a second code word through setting the... Agent: Leydig Voit & Mayer, Ltd

20080086674 - Reduced complexity arp (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size: Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits.... Agent: Garlick Harrison & Markison

20080086672 - Unequal error protection apparatus, systems, and methods: Apparatus and systems, as well as methods and articles, may operate to encode a data word into an unequal error protection (UEP) codeword and to transmit first and second portions of the UEP codeword associated with first and second protection levels across first and second sub-channel subsets associated with first... Agent: Schwegman, Lundberg & Woessner, P.a.

20080086676 - Segregation of redundant control bits in an ecc permuted, systematic modulation code: Redundant information may be stored separately and contiguously with encoded user data such that all redundant information is co-located. Boundaries may be defined as to how error correction coding is processed such that redundant information may be corrected independently from encoded user data. By providing this ability many controller related... Agent: Garlick Harrison & Markison

20080086677 - Adaptive systems and methods for storing and retrieving data to and from memory cells: Adaptive systems and methods that may help assure the reliability of data retrieved from memory cells are described herein. The systems may include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the... Agent: Schwabe, Williamson & Wyatt, P.c.

20080082856 - Recovering from a storage processor failure using write cache preservation: A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner... Agent: Bainwood Huang And Associates LLC

20080082858 - Computer system, changeover-to-backup-system method, changeover-to-backup-system program, monitoring device, terminal device and backup system: To aim at autonomously selecting and switching over a management system by a terminal device, and preventing the terminal device from switching over the system, managing the self-terminal, to a backup system even in the case of a temporary fault from which to recover relatively immediately and in the case... Agent: Staas & Halsey LLP

20080082857 - Operating system with corrective action service and isolation: The claimed subject matter provides a system and/or a method that facilitates re-locating a web application associated with a network service utilizing a portion of serialized data. The network service can be any collection of resources that are maintained by a party (e.g., third-party, off-site, etc.) and accessible by an... Agent: Amin. Turocy & Calvin, LLP

20080082859 - Storage apparatus and control apparatus thereof: A storage apparatus connectable to a host includes a host interface section 20 that notifies the host that data cannot be read out in the case where there is an error sector from which data cannot be read out by a read retry operation and acquires an instruction from the... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20080082861 - Error processing method and information processing apparatus: An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error... Agent: Staas & Halsey LLP

20080082862 - Method of detecting a corruption in a data block: In a tape recording apparatus having a write head and a read head, a data block is stored by writing to a tape via the write head. The tape moves past the write head in a predetermined direction and writes a first data block responsive to transmitting the first data... Agent: Ibm Endicott (anthony England) Law Office Of Anthony England

20080082866 - Method and apparatus for isolating bus failure: The embodiments of the present invention disclose a method for isolating a bus failure, which includes: acquiring, from a Compact PCI bus, an address of a target board being accessed; counting retry responses on the Compact PCI bus, wherein the retry responses are generated by access to the target board;... Agent: Leydig Voit & Mayer, Ltd

20080082867 - Remote chassis monitoring system: In a system for monitoring remote computing stations, each remote station includes an array of detectors and a controller configured to receive the detector signals. The controller causes a condition information generator to generate condition records including multiple condition information entries, each entry corresponding to one of the detector outputs.... Agent: Glen E. Schumann C/o Moss & Barnett

20080082860 - Information processing apparatus for performing a system boot by using programs stored in a non-volatile storage device: After power activation, a transferer 14 detects a bootstrap program 111 having a first error check code 114 assigned thereto and being stored in a first storage device 11, subjects the bootstrap program 111 to an error detection/correction process, and transfers the bootstrap program 111 to the second storage device... Agent: Mcdermott Will & Emery LLP

20080082863 - System and method for maintaining functionality during component failures: A system and method for maintaining functionality during component failures is presented. During application registration, a recovery engine generates a recovery plan for the application. The recovery plan includes recovery actions that correspond to each component that the application intends to access. When an application encounters an unavailable component, the... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080082864 - System and method for performance monitoring: A system for monitoring a computer software system includes a first user actuated tuning knob for allocating space in memory for performance monitoring; a second user actuated tuning knob for a specifying time out value for in-flight units of work; and a transaction monitor responsive to the first and second... Agent: Ibm Corporation Intellectual Property Law

20080082865 - Information recording apparatus, information processing apparatus, and write control method: According to one embodiment, an information recording apparatus includes a disk recording medium, a nonvolatile memory provided with a plurality of memory blocks including a plurality of alternate blocks, a data write section which writes data to a memory block of an address assigned by the system, a data read... Agent: Knobbe Martens Olson & Bear LLP

20080082868 - Overlapping sub-matrix based ldpc (low density parity check) decoder: Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of... Agent: Garlick Harrison & Markison

20080082869 - Memory control unit: The address specified from an upper-level unit is divided into a Bank address, a Row address and a Column address. Parity bits are separately generated to the Row address and the Column address supplied in a time division multiplexed manner, and check bits are generated based on the both parity... Agent: Katten Muchin Rosenman LLP

20080082870 - Parallel bit test device and method using error correcting code: Example embodiments are directed to a parallel bit test device and method using error correcting code. The parallel bit test device may include an error detecting and correcting unit configured to count the number of fail bits in an m-bit data signal, for example, by comparing bits of the m-bit... Agent: Harness, Dickey & Pierce, P.L.C

20080082871 - Semiconductor memory device and testing method of the same: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a... Agent: Volentine & Whitt PLLC

20080082872 - Memory controller, memory system, and data transfer method: According to one embodiment, a memory controller comprises a reading section which reads data from a data part of a nonvolatile memory including the data part for storing data and an extended part for storing an ECC for the data and provides the read data, a computing section which calculates... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20080082873 - Minimum memory operating voltage technique: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating... Agent: Freescale Semiconductor, Inc. Law Department

20080082874 - Fbm generation device and fbm generation method: A fail bit map generation device quickly generating an FBM identifies an abnormal address from a first mismatch detection cycle number obtained in a shipment test and shipment sequence information used in the shipment test. The fail bit map generation device generates a bit identifying pattern that does not perform... Agent: Staas & Halsey LLP

20080082877 - Integrated testing system for wireless and high frequency products and a testing method thereof: A testing system selects one of testing paths based on a control unit and a test switching unit for randomly executing tests upon a plurality of products based on the testing requirements of each of examining units, so as to decrease the costs of equipment, interference between the tests on... Agent: Rosenberg, Klein & Lee

20080082876 - Power gating in integrated circuits for leakage reduction: A system is disclosed for reducing current leakages in an integrated circuit (IC), the system comprises one or more separated power supply lines connecting between one or more power sources and an isolated circuitry, one or more switches on the separated power supply lines for controlling the connections between the... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080082875 - Secure, stable on chip silicon identification: A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises... Agent: Lsi Corporation

20080082878 - System and method to support use of bus spare wires in connection modules: In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every normal bus... Agent: International Business Machines Corporation

20080082879 - Jtag boundary scan compliant testing architecture with full and partial disable: A semiconductor device includes a JTAG boundary scan compliant testing architecture built into the semiconductor device, where the semiconductor device has a number of input points and output points. The JTAG boundary scan compliant testing architecture includes a TAP controller capable of receiving input test data, a test mode-select, and... Agent: Farjami & Farjami LLP

20080082882 - Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications: A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having... Agent: Cantor Colburn LLP - IBM Austin

20080082881 - In situ processor margin testing: Embodiments of apparatuses, methods, and systems for in situ processor margin testing are disclosed. In one embodiment, an apparatus includes virtual machine control logic and operating point control logic. The virtual machine control logic is to transfer control of the apparatus between a virtual machine monitor and a guest. The... Agent: Blakely Sokoloff Taylor & Zafman

20080082880 - Method of testing high-speed ic with low-speed ic tester: A low-frequency circuit tester tests a high-frequency circuit to determine whether the circuit will operate properly at its specified operating frequency when clocked by a clock signal having a specified period. Each of the first and second phases of the test spans the same number of test cycles, with each... Agent: Smith-hill And Bedell, P.C.

20080082883 - System for and method of performing high speed memory diagnostics via built-in-self-test: A system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic... Agent: Downs Rachlin Martin PLLC

20080082884 - Test control circuit: In a conventional semiconductor device, to effectively improve a toggling coefficient of a memory circuit, a test pattern and the like must be inputted from the outside, and there has been a problem that it is difficult to improve the toggling coefficient in a dynamic BT unless a high capability... Agent: Sughrue Mion, PLLC

20080082885 - Test circuit for testing command signal at package level in semiconductor device: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for... Agent: Mcdermott Will & Emery LLP

20080082886 - Sub-instruction repeats for algorithmic pattern generators: An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment,... Agent: Leffert Jay & Polglaze, P.A. Attn: Andrew C. Walseth

20080082887 - System and method for modifying a test pattern to control power supply noise: A system and method for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20080082888 - Measurement and calibration method for embedded diagnostic systems: An apparatus for performing an embedded diagnostic test on a piece of equipment, the equipment including a plurality of components and defining various pathways through respective subsets of the components, comprises an input stimulus generator for generating stimulus signals, coupled to provide the stimulus signals as input to the functionality... Agent: Agilent Technologies Inc.

20080082889 - Semiconductor test system: This invention provides a semiconductor test system including a test pattern generating portion for generating a test pattern data including a test signal for testing a device under test, at a predetermined timing, a driver for inputting the test pattern data generated by the test pattern generating portion into the... Agent: Sughrue-265550

20080082890 - Apparatus and method for transmitting/receiving signal in communication system: An apparatus and method for transmitting/receiving a signal in a communication system are provided. The method includes inputting an information word during initial transmission and transmitting a first code word created by encoding the inputted information word based on a first coding ratio, and transmitting a portion of a second... Agent: JeffersonIPLaw, LLP

20080082891 - Method and device for efficiently retransmitting packets in wired/wireless network: Provided a method and device for efficiently retransmitting packets of which transmissions failed in wired/wireless network including detecting continuity by detecting whether or not a sequence ID of a received packet is continuous with a start sequence ID or an end sequence ID of packets included in reception blocks which... Agent: Ladas & Parry LLP

20080082892 - Integrated circuit device including a circuit to generate error correction code for correcting error bit for each of memory circuits: An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080082893 - Error-tolerant multi-threaded memory systems with reduced error accumulation: Systems and methods establishing and/or utilizing an error-tolerant multithreaded register file are provided. The systems and methods employ dynamic multithreading redundancy (DMR) for error correction. Non-overlapped register access patterns associated create hardware redundancy dynamically that is exploited for error control. Immediate write-back and self-recovery techniques are employed to further enhance... Agent: Mccarter & English , LLP Stamford Office

20080082895 - Method and system for generating low density parity check codes: An approach for generating a structured Low Density Parity Check (LDPC) codes is provided. Structure of the LDPC codes is provided by restricting a certain part of the parity check matrix to be lower triangular, hence enabling a very simple encoding method that does not require the generator matrix of... Agent: The Directv Group, Inc. Patent Docket Administration

20080082894 - Method and system for providing short block length low density parity check (ldpc) codes: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of 3/5... Agent: The Directv Group, Inc. Patent Docket Administration

20080082896 - Burst error correction with offset for correction vector based on fire code: According to an example embodiment, a method may include determining an actual location (N) of a burst error in a data block; selecting a burst error pattern that is a correctable error based on adjusting an error pattern syndrome by an adjustment amount (S); and determining a correction vector based... Agent: Brake Hughes Bellermann LLP C/o Intellevate

20080082898 - Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit: The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calculation circuit. The masking circuit is connected with the signal... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20080082899 - Memory cell supply voltage control based on error detection: For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least... Agent: Intel Corporation C/o Intellevate, LLC

20080082897 - Soft-input soft-output decoder for nonvolatile memory: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an... Agent: Winston & Strawn, LLP

20080082900 - Semiconductor memory apparatus capable of detecting error in data input and output: A semiconductor memory apparatus capable of detecting an error in data input/output includes a memory cell block including a plurality of memory cells. A data input unit receives data from outside the semiconductor memory apparatus and performs predetermined signal processing to record the received data in the memory cell block.... Agent: Venable LLP

20080082901 - Semiconductor memory device: A semiconductor memory device including an error detecting and correcting system, wherein the error detecting and correcting system includes a 3EC system configured to be able to detect and correct 3-bit errors, and wherein the 3EC system is configured to search errors in such a manner that 3-degree error searching... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080082902 - Systems and methods for reduced complexity ldpc decoding: Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the standard float-point sum-product algorithm (SPA), and can reduce the approximation error of... Agent: Baker & Mckenzie LLP Patent Department