Error detection/correction and fault detection/recovery inventions 03/08

20080077822 - Information processing apparatus and disk drive control method: According to one embodiment, an information processing apparatus that includes a processor and a disk drive, in which the disk drive includes a disk storage medium and a nonvolatile memory device, and is configured to execute a self-diagnosis function and stores diagnosis information obtained by the self-diagnosis function, in the... Agent: Knobbe Martens Olson & Bear LLP

20080077821 - Testing system and testing method thereof: A present testing system (100) for testing electronic products is provided. The testing system includes a processor (10), a preliminary testing apparatus (20), and a final testing apparatus (30). The processor includes an encoding module (15) for generating product codes corresponding to the respective electronic products. The preliminary testing apparatus... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080077823 - Information processing apparatus, control apparatus therefor, control method therefor and control program: An information processing apparatus carrying out hardware diagnosis processing by means of initializing processing of each part of hardware when power supply in the apparatus is started, has a power-off initializing processing part carrying out the hardware diagnosis processing when the power supply in the apparatus is cut off; and... Agent: Staas & Halsey LLP

20080077825 - Tracking error events relating to data storage drives and/or media of automated data storage library subsystems:

20080077824 - Storage of data in data stores having some faulty storage locations: There is disclosed data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks, each of said data blocks comprising a plurality of bits, said data store comprising at least one faulty bit within at least some of... Agent: Nixon & Vanderhye, PC

20080077826 - Error monitoring of partitions in a computer system using partition status indicators: A computer program product and computer system for error monitoring partitions in a computer system. Provided to each partition is a partition status indicator (PSI) denoting a RUNNING or FAIL status of the partition, and an error log area (ELA) for storing partition error entries. The ELA includes a partition... Agent: Schmeiser, Olsen & Watts

20080077827 - Test method for semiconductor device: A method for testing a semiconductor device having a detection unit to detect a faulty point by a BIST, a redundant circuit and a replacing unit includes a first step to detect the faulty point by the detection unit under a first test condition and replace the faulty point with... Agent: Mcginn Intellectual Property Law Group, PLLC

20080077828 - Communication apparatus and communication system: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an... Agent: Mcginn Intellectual Property Law Group, PLLC

20080077830 - Internal signal monitoring device in semiconductor memory device and method for monitoring the same: An internal signal monitoring device in a semiconductor memory device includes: an internal signal input unit to receive an internal signal to be monitored and having an output to provide a monitor source signal in response to a test mode signal; and an internal signal output unit having an input... Agent: Blakely Sokoloff Taylor & Zafman

20080077829 - Systems and methods for generating erasure flags: Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into... Agent: Hamilton And Desanctis

20080077831 - Semiconductor integrated circuit, bist circuit, design program of bist circuit, design device of bist circuit and test method of memory: A semiconductor integrated circuit includes a memory, a BIST main circuit and a BIST sub circuit. The BIST sub circuit is to generate a row address pattern or a column address pattern of the memory and includes a boundary address generation circuit for alternately generating a top address and a... Agent: Foley And Lardner LLP Suite 500

20080077832 - Display apparatus and test circuit thereof: A display apparatus comprises a pixel array, a front-end circuit, a test circuit, and an enable circuit. The test circuit tests the pixel array. The enable circuit determines whether to enable the test circuit in response to a predetermined voltage. After the pixel array is tested, the predetermined voltage is... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080077833 - Method and structure for picosecond-imaging-circuit-analysis based built-in-self-test diagnostic: A method (and structure) of at least one of testing, diagnosing, and monitoring an operation of an electronic circuit, includes interrupting a clock signal used to provide a clocking for a normal operation of the circuit and using a second clock signal to repeatedly cycle through a predetermined cycle of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080077834 - Deterministic diagnostic information capture from memory devices with built-in self test: From a memory device comprising a memory circuit and a built-in self-test system (BIST), diagnostic information is deterministically obtained by using the BIST to perform a test sequence that tests the memory circuit. The test sequence comprises writing one or more test patterns at memory locations in the memory circuit... Agent: Verigy

20080077835 - Automatic test equipment receiving diagnostic information from devices with built-in self test: Automatic test equipment capable of receiving diagnostic information from a device under test having a built-in self-test system (BIST) and a diagnostic information collector in which the diagnostic information collector temporarily stores diagnostic patterns output by the BIST and provides a fault indication upon detecting a fault in the device... Agent: Verigy

20080077836 - Diagnostic information capture from memory devices with built-in self test: From a memory device comprising a built-in self-test system (BIST), diagnostic information is obtained by using the BIST to write a test pattern at a memory location in the memory device and to read a respective output pattern from the memory location; comparing the output pattern with a corresponding expected... Agent: Verigy

20080077837 - Interference limitation for retransmissions: The present invention relates to a method for transmitting data packets from a mobile terminal to a base station using a hybrid automatic repeat request protocol and soft combining of received data. Further, the present invention provides a base station and a mobile terminal both adapted to perform the respective... Agent: Stevens, Davis, Miller & Mosher, LLP

20080077838 - Apparatus, and associated method, for requesting data retransmission in a packet radio communication system: Apparatus, and an associated method, that reduces the occurrence of generation of redundant requests for retransmission of packet-formatted data, formatted at a physical layer and at a higher-logical layer, such as at an RLP layer. An estimate of an appropriate delay period is formed. The estimate is responsive to communication... Agent: Alston & Bird LLP

20080077839 - Stochastic decoding of ldpc codes: The present invention relates to a decoding method and system for stochastic decoding of LDPC codes. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is... Agent: Freedman & Associates

20080077840 - Memory system and method for storing and correcting data: A data memory system is provided which includes a plurality of first data storage devices, at least two second data storage devices, and a third data storage device. The plurality of first data storage devices is configured to store first data. The second data storage devices are configured to store... Agent: Hewlett Packard Company

20080077842 - Memory with cell population distribution assisted read margining: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental... Agent: Davis Wright Tremaine LLP

20080077841 - Methods of cell population distribution assisted read margining: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20080077843 - Apparatus and method for decoding using channel code: An encoding and decoding method and apparatus. is disclosed. The method and apparatus improves encoding and decoding performance without using a large memory capacity and also reduces the complexity of hardware for implementation. According to the method, an encoded signal is received from a transmitting side, and the received signal... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20080072100 - Generating functional test scripts: A method for eliminating ambiguity and incorrectness of the specification determined in a requirement defining phase in developing an information system, and systematically verifying whether an automatically executed test scenario agrees with the original requirements in a functional testing phase, includes extracting an input variable, an output variable, and the... Agent: Ibm Corporation

20080072101 - Identifying failure in a tree network of a parallel computer: Methods, parallel computers, and products are provided for identifying failure in a tree network of a parallel computer. The parallel computer includes one or more processing sets including an I/O node and a plurality of compute nodes. For each processing set embodiments include selecting a set of test compute nodes,... Agent: Ibm (roc-blf)

20080072106 - Method and system of specifying semantics of a late trigger: In a computer programming language environment operating with a real-time clock, a method comprises: providing an instruction in the programming language for performing an action and for specifying an explicit time for performing the action, the instruction including at least a first parameter for specifying whether the action should be... Agent: Agilent Technologies Inc.

20080072107 - Apparatus and method for detecting errors in display driver integrated circuit of mobile device: Disclosed are an apparatus and a method for detecting errors in a display driver IC to prevent abnormal phenomena in a display unit of a mobile device. When initializing a memory of the display driver IC, a control unit stores control values in the memory for controlling a liquid crystal... Agent: The Farrell Law Firm, P.C.

20080072099 - Fault tolerant control system: A fault tolerant data processing system for controlling a real time process. The system is tolerant to systematic faults in its software. The system includes a data processor unit with a program memory and a data memory and input and output units where program software residing in the program memory... Agent: Venable LLP

20080072102 - Forming stack frame signatures: A method of forming a stack signature responsive to execution of a computer program in a digital computer according to one embodiment comprises halting execution of the computer program, tracing the program's call stack to determine a series of stack frames resulting from execution of the program, capturing a selected... Agent: Stoel Rives LLP

20080072103 - Wireless remote firmware debugging for embedded wireless device: A method for debugging a read only memory (ROM) in a wireless target device is disclosed. A wireless communication link is established between the target device and a host computer. A debug mode change command is received from the host computer by the application program running on the target device... Agent: Brake Hughes Bellermann LLP C/o Intellevate

20080072104 - Error monitoring of partitions in a computer system using supervisor partitions: A computer program product for error monitoring partitions in a computer system. A global supervisor mapping (GSM) associates each supervised partition with a supervisor partition that monitors the supervised partition. A partition status buffer (PSB) denotes a status (GOOD, BAD, NOCARE) of the partition. The BAD status denotes that the... Agent: Schmeiser, Olsen & Watts

20080072105 - Heartbeat apparatus via remote mirroring link on multi-site and method of using same: The present invention is directed to a heartbeat apparatus via a remote mirroring link for a multi-site and a method for using the heartbeat apparatus. Information is registered in a configuration table, wherein the configuration table stores host ID information and volume ID information. The configuration table is configured, access... Agent: Reed Smith LLP

20080072108 - Method and apparatus for analyzing delay defect: The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual increase in the frequency of an operational clock pulse fed to an integrated circuit belongs. The apparatus obtains information... Agent: Staas & Halsey LLP

20080072109 - Processor memory array having memory macros for relocatable store protect keys: A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length... Agent: International Business Machines Corporation

20080072110 - Circuitry and method to detect conditions of data: A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to... Agent: Hewlett Packard Company

20080072111 - Method for performing a test case with a lbist engine on an integrated circuit, integrated circuit and method for specifying an integrated circuit: The present invention relates to a method for performing a test case with at least one LBIST engine on an integrated circuit with a plurality of storage elements and logic circuits interconnected according to a predetermined scheme. The LBIST engine is at least partially built up by storage elements and/or... Agent: International Business Machines Corporation Dept. 18g

20080072112 - Sequential scan technique providing reliable testing of an integrated circuit: Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the threshold represents a number of toggles in the corresponding portion. The toggles can include the transitions that would be caused by... Agent: Texas Instruments Incorporated

20080072113 - Method of locating packet for resend from retry buffer: In PCI-Express and alike network systems, back-up copies of recently sent packets are kept in a retry buffer for resending if the original packet is not well received by an intended destination device. A method for locating the back-up copy in the retry buffer comprises applying a less significant portion... Agent: Macpherson Kwok Chen & Heid LLP

20080072114 - Apparatus and method for tracking packets in a reliably connected transmission system: A method and apparatus tracks packets and reliably transmits data over a computer transmission system with a reduced amount of memory needed in the transmission interface. The invention eliminates the need to keep all the packets of data queued until the acknowledge message for that data has arrived. Instead, it... Agent: Martin & Associates, LLC

20080072115 - Apparatus and method for processing received data in a broadband wireless communication system: A method for processing data of a received frame in a receiver of a broadband wireless communication system. The received data processing method includes extracting, from control information for data of one frame having multiple bursts, burst sizes of bursts constituting the frame and modulation scheme information applied to the... Agent: The Farrell Law Firm, P.C.

20080072116 - System and method for using bit errors from memory to alter memory command stream: A system, method, and memory controller are provided that alters a memory command stream to a hardware memory. Data is written to the hardware memory and, after the data is stored in the memory, error correction code is received from the memory. Bit errors are identified based upon the error... Agent: Ibm Corporation- Austin (jvl) C/o Van Leeuwen & Van Leeuwen

20080072119 - Allowable bit errors per sector in memory devices: A method of reading a page from a memory array, wherein the page includes a plurality of sector, determining whether each of the plurality of sectors includes an allowable number of errors, and providing a success indicator if each of the plurality of sectors includes an allowable number of errors.... Agent: Trop, Pruner & Hu, P.C.

20080072117 - Programming a memory device having error correction logic: Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile memory array includes, in response to a first condition, switching from an... Agent: Freescale Semiconductor, Inc. Law Department

20080072118 - Yield-enhancing device failure analysis: In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred... Agent: Ryan, Mason & Lewis, LLP

20080072121 - Method and apparatus for repairing defective cell for each cell section word line: A method and apparatus for repairing defective cells for each section word line. The repairing apparatus includes an address comparison unit and a repairing unit. The address comparison unit compares a main address of a defective address, indicating the location of a defective cell, to a main address of an... Agent: F. Chau & Associates, LLC

20080072120 - Variable strength ecc: Memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory controllers, memory systems, and/or non-volatile memory devices by allowing the number of ECC check bytes being utilized to be varied to increase or decrease the ECC check depth. This allows the depth... Agent: Attn: Thomas W. Leffert Leffert Jay & Polglaze, P.A.

20080072122 - Method and apparatus for decoding data: A method and apparatus for decoding data is provided herein to show how to turbo decode LDPC codes that contain a partial dual diagonal parity-check portion, and how to avoid memory access contentions in such a turbo decoder. During operation, a decoder will receive a signal vector corresponding to information... Agent: Motorola, Inc.

20080072123 - Iterative decoder employing multiple external code error checks to lower the error floor: Iterative decoder employing multiple external code error checks to lower the error floor and/or improve decoding performance. Data block redundancy, sometimes via a cyclic redundancy check (CRC) or Reed Solomon (RS) code, enables enhanced iterative decoding performance. Improved decoding performance is achieved during interim iterations before the final iteration. A... Agent: Howrey LLP

20080072124 - Apparatus and method for detecting puncture position in a symbol stream encoded by punctured convolutional coding scheme: An apparatus and method for determining a puncture position for a de-puncturing process. A stream of received symbols that corresponds to a code is received. A slicing unit slices the stream of received symbols to determine representative bits of the code to form a first bit stream. A delay line... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080072125 - Programmable continuous phase modulation (cpm) decoder and associated methods: The programmable decoder, such as a Maximum Likelihood Sequence Estimation (MLSE) decoder (e.g. a Viterbi decoder) may include a programming input for a plurality of programmable trellis parameters, and a programmable device, such as an FPGA, connected to the programming input and implementing a continuous phase modulation (CPM) decoder including... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist

20080072126 - Programmable trellis decoder and associated methods: The programmable decoder, such as a Maximum Likelihood Sequence Estimation (MLSE) decoder (e.g. a Viterbi decoder) may include a programming input for a plurality of programmable trellis parameters, and a programmable device, such as an FPGA, connected to the programming input and implementing a trellis decoder including at least one... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist

20080072127 - Low power viterbi decoder using a novel register-exchange architecture: An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Viterbi decoder's register memory from being shifted if the... Agent: Mendelsohn & Associates, P.C.

20080072128 - Distributed ring control circuits for viterbi traceback: Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.... Agent: Marshall, Gerstein & Borun, LLP (marvell)

20080072129 - Communications digital signal processor and digital signal processing method: A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs... Agent: Greenblum & Bernstein, P.L.C

20080072130 - Pattern-triggered measurement system: A measurement system recovers a clock signal from an applied signal that includes a repeating bit pattern, provides a trigger signal synchronized to occurrences of the repeating bit pattern, acquires a set of data samples time-referenced to the trigger signal, and acquires a set of phase error samples of a... Agent: Agilent Technologies Inc.

20080065928 - Technique for supporting finding of location of cause of failure occurrence: A support system includes a storage unit for storing a dependency graph in which components are expressed as nodes and relationships of components depending directly on each other are expressed with links, a log display unit for displaying, in response to detection of a failing component, a log of events... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20080065929 - Method and apparatus for storing and distributing memory repair information: A system for repairing embedded memories on an integrated circuit is disclosed. The system comprises an external Built-In Self-repair Register (BISR) associated with every reparable memory on the circuit. Each BISR is configured to accept a serial input from a daisy chain connection and to generate a serial output to... Agent: Ridout & Maybee LLP

20080065930 - High-speed redundant disk controller methods and systems: Various apparatus and methods for controlling data for a redundant array of inexpensive/independent disks (RAID) are presented. For example, in one illustrative embodiment, a controlling apparatus can include a translation device composed substantially entirely of gate-level electronic hardware, wherein the translation device includes a sector sequencer capable of arranging sector... Agent: Agere Systems, Inc.

20080065932 - Image forming apparatus: An image forming apparatus including: a registration section which registers information on a diagnostic mode, where an operation mode to diagnose inside the image forming apparatus based on error information is assumed to be the diagnostic mode; an error detecting section which detects an error in the apparatus and outputs... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080065931 - Methods, systems, and media for generating a regression suite database: Methods, systems and media for generating an improved regression suite by applying harvesting models and/or regression algorithms to tests utilized in verification of a system are disclosed. In one embodiment, a regression manager responsive to user input may be coupled to a harvester module, an analysis module, and a management... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20080065933 - Memory correction system and method: An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module and a second memory module, each comprising a plurality of memory devices; and a memory controller operably coupled to... Agent: Hewlett Packard Company

20080065934 - Device test and debug using power and ground terminals: The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to... Agent: Texas Instruments Incorporated

20080065935 - Method of recording/reproducing digital data and apparatus for same: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against... Agent: Townsend And Townsend And Crew, LLP

20080065936 - Data stream processing method and system: A method and system for decoding a received data stream are disclosed. The appropriate time interval to decode the received data stream is derived from the data stream itself. A header of the data stream is analyzed to determine two sets of time ranges, each set of time ranges corresponding... Agent: Larson Newman Abel Polansky & White, LLP

20080065937 - Nand flash memory device with ecc protected reserved area for non-volatile storage of redundancy data: Basic redundancy information is non-volatily stored in a reserved area of an addressable area of a memory array, and is copied to volatile storage therein at every power-on of the memory device. The unpredictable though statistically inevitable presence of failed array elements in such a reserved area of the memory... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080065938 - System, method and storage medium for testing a memory module: A buffered memory module including a downstream buffer, a downstream receiver, an upstream driver, an upstream receiver. The downstream buffer and the downstream receiver are both adapted for connection to a downstream memory bus in a packetized cascaded interconnect memory subsystem. The upstream driver and the upstream receiver are both... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080065939 - Controller applying stimulus data while continuously receiving serial stimulus data: An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data... Agent: Texas Instruments Incorporated

20080065940 - Test data compression method for system-on-chip using linear-feedback shift register reseeding: A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.... Agent: Nec Laboratories America, Inc.

20080065941 - Meta-data driven test-data generation with controllable combinatorial coverage: Generation of test data for systems having functionality subject to a grammar or other sort of meta-data is automated by a controlled combinatorial approximation of naïve combinatorial coverage. A suite of control mechanisms are applied to an algorithm that generates test data to provide well-defined and understandable approximations of full... Agent: Woodcock Washburn LLP (microsoft Corporation)

20080065942 - Synthetic instrument utilizing peer-to-peer communication for error correction: An apparatus having a local network and a plurality of component modules is disclosed. Each component module has an input for receiving an input signal, an output for transferring an output signal derived from the input signal by that component module, and a network port that connects that module to... Agent: Agilent Technologies Inc.

20080065944 - Method and apparatus for dynamically allocating harq buffer in wireless communication system: Disclosed is a method and apparatus for efficiently controlling buffers which support a Hybrid Automatic Repeat Request (HARQ) in a wireless communication system. Buffer regions for the HARQ scheme are not fixedly allocated according to channel identification information, but are allocated from the viewpoint of one overall memory through aggregation... Agent: The Farrell Law Firm, P.C.

20080065943 - Method and system for using data from a failed crc block to determine retransmission of data packets: Certain aspects of a method and system for using data from a failed cyclic redundancy check (CRC) block to determine whether retransmission of data packets should occur are disclosed. Aspects of one method may include determining a sequence number of a received packet with a failed cyclic redundancy check (CRC).... Agent: Mcandrews Held & Malloy, Ltd

20080065945 - Data repair: The invention relates to a method for data repair in a system capable of one-to-many transmission. The method comprises transmitting data from a sender to at least one receiver and provides for various sender driven or receiver driven repair methods of missing data.... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080065946 - Method and system of relaying data: A method and system of relaying data are provided. The data is encoded into a turbo codeword by using a convolutional turbo code, and the turbo codeword is transmitted from a source to a relay and a destination by first puncturing the turbo codeword. The first punctured turbo codeword which... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20080065947 - Method and system for decoding low density parity check (ldpc) codes: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system... Agent: The Directv Group, Inc. Patent Docket Administration

20080065948 - Turbo code interleaver with optimal performance: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon... Agent: The Directv Group, Inc. Patent Docket Administration

20080065949 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080065950 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080065951 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20080065952 - Forward error correction scheme for data channels using universal turbo codes: A method of providing forward error correction for data services uses a parallel concatenated convolutional code which is a Turbo Code comprising a plurality of eight-state constituent encoders wherein a plurality of data block sizes are used in conjunction with said Turbo Code. A variation uses the method in a... Agent: The Directv Group, Inc. Patent Docket Administration

20080065953 - Method and system for generating parallel decodable low density parity check (ldpc) codes: An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the... Agent: The Directv Group, Inc. Patent Docket Administration

20080065954 - Method for a general near optimal turbo code trellis termination: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from... Agent: The Directv Group, Inc. Patent Docket Administration

20080065955 - Method for a general near optimal turbo code trellis termination: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from... Agent: The Directv Group, Inc. Patent Docket Administration

20080065960 - Apparatus and method for communicating fec mode and alarming mismatch: A multi-mode transmission unit processes data to form an error correction code in accordance with one of a plurality of selectable processes. The data, correction code and a process identifier can be transmitted to a receiving unit which can carry out error correction of the data in accordance with the... Agent: Welsh & Katz, Ltd

20080065959 - Efficient parallel cyclic redundancy check calculation using a novel table lookup approach: m

20080065958 - Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications: A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks... Agent: Docket Clerk

20080065956 - Method and apparatus for encoding and decoding data: A method and apparatus for encoding and decoding data is provided herein. During operation, A structured parity-check matrix H is provided to the encoder and decoder, where H is an m by n matrix and an expansion of a model matrix Hbm of size mb by nb, where m=mb×z and... Agent: Motorola, Inc.

20080065957 - Rfid decoding subsystem with pre-decode module: A radio frequency identification (RFID) decoding subsystem includes a pre-decode module and a decode module. The pre-decode module is coupled to process down-converted RFID signals into at least one of pre-decoded baseband data and corresponding decoding information. The decode module is coupled to process the pre-decoded baseband data into decoded... Agent: Garlick Harrison & Markison

20080065961 - Ldpc (low density parity check) coded modulation symbol decoding: LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that... Agent: Garlick Harrison & Markison

20080065962 - Method and apparatus for error compensation: Various approaches to recover data are described. An one example, an encoded data stream is processed in a first channel decoder producing a channel decoder output. The channel decoder output and the encoded data stream are processed in an error compensation unit to compensate the channel decoder output for low... Agent: Priest & Goldstein, PLLC

20080065963 - Forward error correction decoder and method thereof: Provided are a forward error correction decoder and a method thereof. The method comprises: generating mapping information on a location of a symbol; deciding a location of an error in a packet; deciding an erasure of a subsequent packet following the packet on the basis of the error location and... Agent: Foley And Lardner LLP Suite 500

20080065964 - Block processing of input data in graphical programming environments: In one embodiment, a processing block of a block diagram receives input data including a plurality of data elements organized as a matrix of a first size. At least a portion of the input data is partitioned into a plurality of data blocks in response to user-selected parameters. A data... Agent: Lahive & Cockfield, LLP/the Mathworks

20080065965 - Buffering packets of a media stream: Buffering packets of a media stream for transmission from a transmitting device to a receiving device. Media packets are formed from at least one kind of media information in a stream generator; forward error correction data is formed on the basis of the media packets; one or more repair packets... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20080065966 - Methods and apparatus for improved error and erasure correction in a reed-solomon date channel: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation... Agent: Lsi Corporation

20080065967 - System for controlling high-speed bidirectional communication: A system for controlling high-speed bidirectional communication includes a slave device such as a memory device, for example, coupled to a master device such as a memory controller, for example. The master device may be configured to control data transfer between the master device and the slave device. The master... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20080065968 - Decoder system for data encoded with interleaving and redundancy coding: A system for processing a data signal (such as an ADSL or VDSL signal) includes a demodulator, a first decoder unit, such as a convolutional encoder or a QAM decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a... Agent: Brinks Hofer Gilson & Lione Infineon

20080065969 - System for impulse noise and radio frequency interference detection: A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal... Agent: Brinks Hofer Gilson & Lione Infineon

20080065971 - Distributed block coding (dbc): Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080065970 - Systems and methods for code dependency reduction: Various systems and methods for code dependency reduction are disclosed herein. For example, one method includes receiving an un-encoded data set that is represented as an array of columns and rows. In addition, two groups of data bits traversing the un-encoded data set at respective angles are formed. Based at... Agent: Hamilton And Desanctis

20080065972 - Method and system for providing long and short block length low density parity check (ldpc) codes: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC... Agent: The Directv Group, Inc. Patent Docket Administration

20080059832 - Support system for failure prognosis, warning and restoration operation of machine: The invention provides a system attached to a laser beam machine for supporting failure prognosis, warning and restoration operation by monitoring the status of the machine. A laser beam machine 1 has a pallet 20 supported on a bed 10, and subjects a work W1 to laser processing. The management... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20080059835 - Method and apparatus for managing bad run-time block in mlc flash memory: A method and apparatus are provided for managing a bad run-time block in a multi-level cell flash memory. The apparatus includes a buffer-allotting module which allots a buffer in which data programmed in a least significant bit (LSB) of a cell is temporarily stored, a data-copying module which copies the... Agent: Sughrue Mion, PLLC

20080059837 - Active block diagram for controlling elements in an electronic device: A method and apparatus for controlling elements in an electronic device is via a graphical block diagram of the electronic device which displays the elements. The block diagram is coupled to the electronic device so that an operator controls the elements via the block diagram. In one embodiment of the... Agent: Agilent Technologies Inc.

20080059838 - Apparatus and method for performing failure diagnostic testing of electronic equipment: An apparatus and method for automated diagnostic testing of an electronic device assembly so that functional testing, collection of test results, diagnosis for identifying potentially failed components in the device assembly is a software controlled automated process. In one embodiment of the present invention, a component-level block diagram is coupled... Agent: Agilent Technologies Inc.

20080059839 - Intelligent integrated diagnostics: A diagnostics system comprising a topological map of a target system that has nodes (38, 40, 42, 44, 46, 48) that correspond to components (29, 30, 32, 34, 36) of the target system and links that correspond to connections between the components. Associated with the topological map is a knowledge... Agent: Christopher P. Harris Tarolli, Sundheim, Covell & Tummino

20080059843 - Debugging system, debugging circuit and information processing apparatus: A debugging system includes a CPU that is a debugging target and a debugging circuit. The CPU has an output part configured to independently output stack access information of a stack access and data access information of a data access excluding the stack access, as data access information of the... Agent: Staas & Halsey LLP

20080059845 - Computer system and method for operating the same: In a computer system, each personal computer includes a bootup management device managing the start operation thereof. The bootup management device excludes a personal computer that failed to start, and provides a user with another personal computer. The user operates the terminal device connected to a network, and can accomplish... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20080059833 - Hvac control panel for clearing fault code memory: A control panel for an HVAC unit is disclosed. The control panel includes a memory device storing a predetermined reset code that corresponds to a plurality of control signals and which memory device is configured to store a plurality of fault codes resulting from faults occurring during operation of the... Agent: Mcnees Wallace & Nurick LLC

20080059834 - Use of non-volatile memory to perform rollback function: A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults, power loss, or other computer system failure without a loss of data or processing continuity. In a typical... Agent: Knobbe Martens Olson & Bear LLP

20080059836 - Multifunctional terminal device: A multifunctional terminal device includes a sensing unit that senses a malfunction, and a determining unit that determines a type of the malfunction when a malfunction has occurred. A selecting unit selects according to the type of the malfunction a recovery operation and a notification operation. A recovering unit performs... Agent: Harness, Dickey & Pierce, P.L.C

20080059840 - Reliability evaluation system, reliability evaluating method, and reliability evaluation program for information system: A system includes an input unit (2) to which failure information corresponding to failure modes of constituents indicating software and hardware, a system configuration information and a standard value of system availability are inputted, a producing unit (32) producing a fault tree based on the system configuration information, a calculating... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080059841 - Method and system for detection of integrity constraint violations: A system (and method) of detecting an error in a database interaction, includes providing information about at least one of at least first and second software systems, and a mapping between at least a portion of the at least first and second software systems, and examining the at least one... Agent: Mcginn Intellectual Property Law Group, PLLC

20080059842 - Dynamic verification traversal strategies: A method of implementing a traversal strategy as part of a dynamic verification can include initializing a non-deterministic automaton (NDA) traversal mechanism that has (1) a strategy push-down stack (strategy PDS) that holds traversal strategy pointers and (2) an object push-down stack (object PDS) that holds object pointers, pushing a... Agent: Klarquist Sparkman, LLP

20080059844 - Switch device, storage control system and trace data obtaining method: A fiber channel switch (hereinafter, FC-SW) connected to a plurality of communications devices is provided with a buffer for temporarily storing data received from servers via a first communications port, a trace data storage memory for storing trace data, and a microprocessor (MP) for sending data accumulated in the buffer... Agent: Stanley P. Fisher Reed Smith LLP

20080059846 - Fault tolerant electronic trading system and method: A fault tolerant electronic trading system and method. The fault tolerant electronic trading system and method includes N-level redundancy that allows multiple components within the system to fail without forcing users off the system or causing the trading system to fail. Fault tolerance with risk management controls is also provided.... Agent: Lesavich High-tech Law Group, P.C.

20080059847 - Turbo code interleaver with near optimal performance: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon... Agent: The Directv Group, Inc. Patent Docket Administration

20080059848 - Data transmission speed test system and method: A data transmission speed test system is provided. The system includes a computer. The computer is configured for reading data stored in a database and transmitting the data to a target device. The computer is further configured for testing data transmission speeds at regular time intervals and dynamically displaying the... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20080059851 - Semiconductor apparatus and testing method: A semiconductor apparatus comprising: a plurality of memory circuits each including a memory and an input/output selector, the memory having a plurality of memory cells and a plurality of input/output circuits respectively corresponding to the memory cells; and an incorporated self-test circuit that executes a quality test for the memory,... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080059849 - Semiconductor device: A cut-off circuit cuts off supply of a power supply voltage from a voltage supply circuit to a non-volatile memory block. A discharge circuit discharges an electric charge accumulated in stability capacitance. In a data retention test of the memory block, a self test circuit instructs the cut-off circuit to... Agent: Arent Fox LLP

20080059850 - Self programmable shared bist for testing multiple memories: A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a memory test algorithm. The delay generator provides a delay of an expected data,... Agent: Seed Intellectual Property Law Group PLLC

20080059852 - Memory card and its initial setting method: In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is... Agent: Miles & Stockbridge PC

20080059853 - Semiconductor integrated circuit: A semiconductor integrated circuit. A scan mode is set and test data is set in a scan chain of S-FFs 4 and 2B. The circuit switches to normal mode and a first pulse of a clock signal CLK is provided. Outputs of combinational circuit 1A, acquired by S-FFs 2B, and... Agent: Volentine & Whitt PLLC

20080059854 - Merged misr and output register without performance impact for circuits under test: The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit... Agent: International Business Machines Corporation

20080059855 - Selectively accessing test access ports in a multiple test access port environment: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).... Agent: Texas Instruments Incorporated

20080059856 - Method of defining fault pattern of equipment and method of monitoring equipment using the same: Provided is a method of forming reference information for defining a fault pattern of equipment, and monitoring equipment. One example embodiment method may include performing an angle spectrum analysis by re-classifying fault points distributed on a plane, the plane including a first component axis and a second component axis, and... Agent: Harness, Dickey & Pierce, P.L.C

20080059857 - Methods and apparatus for testing a scan chain to isolate defects: Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the... Agent: Ibm Corporation C/o Sally Redfern

20080059858 - Load generating apparatus and load testing method: A load generating apparatus for applying a load on a bus of a test target system, has a mode setting register to which an operation mode is set, a data size register to which a data size of one data transfer is set, a register group to which a base... Agent: Staas & Halsey LLP

20080059860 - Communication system, communication apparatus and communication method: In an interpretation interval INTALL used in a communication system, there are provided a future-direction interval INTF associated with a 5-bit sequence number (LastSendAckNum) transmitted after LastSendAckNum ±0, and a past-direction interval INTP associated with a 5-bit sequence number (LastSendAckNum) transmitted prior to LastSendAckNum ±0. A transmitter side encodes a... Agent: Hogan & Hartson L.L.P.

20080059861 - Adaptive error resilience for streaming video transmission over a wireless network: The invention relates to a method of transmitting a signal over a communication network. The method comprises transmitting the signal and transmitting proactive repair redundancy information.... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20080059859 - Method and apparatus for dynamically allocating harq processes in the uplink: In a wireless communication system including at least one wireless transmit/receive unit (WTRU) and at least one Node-B (NB), an activation or deactivation state is determined for each of a plurality of HARQ processes. A signal that includes the activation or deactivation state for each of the HARQ processes is... Agent: Volpe And Koenig, P.C. Dept. Icc

20080059862 - Apparatus and method to transmit/receive signal in a communication system: An apparatus and method for transmitting/receiving a signal in a communication system are provided. A signal reception apparatus of a communication system receives a signal and generates a child Low Density Parity Check (LDPC) codeword vector by decoding the received signal according to a child parity check matrix supporting a... Agent: JeffersonIPLaw, LLP

20080059863 - Method of recording/reproducing digital data and apparatus for same: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against... Agent: Townsend And Townsend And Crew, LLP

20080059864 - Method of recording/reproducing digital data and apparatus for same: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against... Agent: Townsend And Townsend And Crew, LLP

20080059865 - Apparatus and method for generating a galois-field syndrome: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC C/o Portfolio Ip

20080059866 - Dtv transmitting system and receiving system and method of processing broadcast data: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20080059867 - Decoding technique for linear block codes: The present decoding technique provides an efficient technique for decoding linear block codes from multiple encoders. When an error in a code sequence is detected, the decoding technique estimates a confidence for each bit within the code sequence. Based on the confidence, a subset of bits within the code sequence... Agent: Lee & Hayes PLLC

20080059868 - System and method for forward error correction decoding using soft information: A system and method for soft decision forward error correction (FEC) decoding may be used to determine a possible error in a differential detection signal, for example, in a DPSK system. The system and method uses the constructive and destructive signals from a demodulator to provide an error locating signal.... Agent: Grossman, Tucker, Perreault & Pfleger, PLLC

20080059869 - Low cost, high performance error detection and correction: A method and apparatus provides the ability to build and use low-density linear parity-check (LDPC) codes for implementing error detection and correction (EDC). A number of data bits and a number of parity bits are received. While the number of data bits and number of parity bits are within a... Agent: Gates & Cooper LLP Howard Hughes Center