Error detection/correction and fault detection/recovery inventions 12/07

20070300102 - Operation instruction system, operation instruction device, operation instruction program storage medium, and operation instruction method: An operation instruction method includes: an operation detecting step of detecting a manual operation; an operation detail displaying step of displaying the details of a manual operation detected at the operation detecting step; and an operation occurrence notifying step of, in response to detection of a manual operation at the... Agent: Kratz, Quintos & Hanson, LLP

20070300100 - Error correction scheme for memory: An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column... Agent: Borden Ladner Gervais LLP Anne Kinsman

20070300101 - Rapid regeneration of failed disk sector in a distributed database system: A technique for read error failover processing in a mirrored disk system such as a Redundant Array of Inexpensive Disks (RAID) system, where individual disk units perform Logical Block Address (LBA) remapping. A read error causes a disk controller to report an “unrecoverable” read error to a RAID controller. After... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070300103 - Method and system for troubleshooting a misconfiguration of a computer system based on configurations of other computer systems: A method and system for identifying a configuration parameter of a “sick” computer system that is at fault for causing an undesired behavior based on analysis of configuration parameters from other computer systems is provided. In one embodiment, a troubleshooting system collects “suspect” values for “suspect” configuration parameters used by... Agent: Perkins Coie LLP/msft

20070300104 - Bit error rate reduction buffer: In a preferred embodiment, the invention provides a circuit for reducing bit error rates. A data recovery circuit recovers data from a first HSS link to differential bit pair inputs. Data from the differential bit pair outputs of the data recovery circuit drive differential bit pair inputs to a plurality... Agent: Hewlett Packard Company

20070300105 - Memory hub tester interface and method for use thereof: A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command, address, and data signals in accordance... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070300106 - Integrated memory device and method for its testing and manufacture: An integrated memory device includes an array of memory cells for storing data, a memory cell selector operationally connected to the array for selecting at least one memory cell of the array, a data interface adapted to store data provided to the data interface in a selected memory cell and... Agent: Slater & Matsil LLP

20070300107 - Device test apparatus: The present invention provides a device test apparatus for testing an integrated device circuit having a plurality of combinational circuits and multi-wiring-layers interconnecting the combinational circuits. The device test apparatus includes a plurality of scanning flip-flop (FF) circuits corresponding to the combinational circuits and the multi-wiring-layers. The FF circuits supply... Agent: Nixon Peabody, LLP

20070300108 - Logic device and method supporting scan test: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to... Agent: Qualcomm Incorporated

20070300109 - High speed interconnect circuit test method and apparatus: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan... Agent: Texas Instruments Incorporated

20070300110 - Phase shifter with reduced linear dependency: A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and... Agent: Klarquist Sparkman, LLP

20070300112 - Semiconductor integrated circuit apparatus, test circuit of semiconductor integrated circuit apparatus and test method of semiconductor integrated circuit apparatus: A semiconductor integrated circuit apparatus includes: a plurality of flip-flops configured to operate with clocks having mutually different frequencies; an oscillator configured to output oscillation output that is a source of the clocks supplied to the flip-flops; a storage part configured to store control data for a delay fault test;... Agent: Amin, Turocy & Calvin, LLP

20070300111 - Wide frequency range signal generator and method, and integrated circuit test system using same: A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled.... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070300113 - Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance: An apparatus and method for automatically calibrating a duty cycle circuit for maximum performance are provided. A chip level built-in circuit that automatically calibrates the duty cycle correction (DCC) circuit setting for each chip is provided. This chip level built-in circuit includes a clock generation macro unit, a simple duty... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070300114 - Test apparatus and test method: A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to... Agent: Osha Liang L.L.P.

20070300115 - Apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device: An apparatus and method for accelerating test, debug and failure analysis of a multiprocessor device are provided. With the apparatus and method, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that,... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070300116 - Asynchronous set-reset circuit device: An asynchronous set-reset circuit device for testing activity performed by an Automatic Test Patterns Generation tool may include a pair of logic gates having at least two inputs each, and a logic gate structure coupled upstream from the pair of logic gates. The logic gate structure may be for driving... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070300117 - Mapping logic for loading control of crossbar multiplexer select ram: A circuit and method for efficiently configuring an ACAM Select RAM for an ACAM circuit of a tester that tests multiple devices under test (DUTs).... Agent: Agilent Technologies Inc.

20070300118 - Method and system for controlling multiple physical pin electronics channels in a semiconductor test head: Methods and apparatuses for processing test execution instructions on a plurality of devices under test (DUTs) simultaneously include functionality for receiving a test instruction, extracting a specified DUT channel identifier from the test instruction, extracting an instruction from the test instruction, determining whether the instruction requires application of a stimulus... Agent: Agilent Technologies Inc.

20070300119 - System and method for the adjustment of compensation applied to a signal using filter patterns: In one embodiment of the present invention, a method for adjusting a signal includes applying at least one of a loss compensation for frequency-dependent distortion and an offset compensation for DC-offset distortion to a data signal before or after the distortion occurs to generate an output signal. The method also... Agent: Baker Botts L.L.P.

20070300120 - Retransmission apparatus and method for high-speed data processing: A method for requesting retransmission of high-speed packet data in a receiving Automatic Retransmission reQuest (ARQ) entity of a mobile communication system that simultaneously performs Hybrid Automatic Retransmission reQuest (HARQ) and ARQ. The method includes, upon receipt of a packet, determining a sequence number of the received packet, and determining... Agent: The Farrell Law Firm, P.C.

20070300121 - Software and methods to detect and correct data structure: Methods to detect and correct bit errors in data include the steps of specifying to a compiler a storage area with a variable wherein the variable includes a data value corresponding to its data size and an error checking code, calculating an error checking code value indicative of the corresponding... Agent: Cook, Alex, Mcfarron, Manzo, Cummings & Mehler Ltd

20070300122 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20070300123 - Error-correcting encoding apparatus: A desired coding rate is obtained by encoding source data to produce first additional data; randomizing the source data to produce randomized data; encoding the randomized data to produce second additional data; selecting a number of bits from the first and second additional data to produce first selected data and... Agent: Myers Wolin, LLC

20070300124 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error... Agent: Mark D. Saralino (mei) Renner, Otto, Boisselle & Sklar, LLP

20070300126 - Information processing device and information processing method: An information processing device implements error control including at least one of error detection and error correction. The device comprises an information bit sequence acquiring unit and an encoder. The information bit sequence acquiring unit acquires an information bit sequence. The encoder generates a redundant bit sequence enabling execution of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070300125 - Wireless communication using codeword encoded with high-rate code: Embodiments of the present invention provide methods and apparatus for wireless communication using codeword with high-rate codes. Other embodiments may be described and claimed.... Agent: Schwabe, Williamson & Wyatt, P.C.

20070300127 - Code generator and decoder for communications systems operating using hybrid codes to allow for multiple efficient users of the communications systems: A method of encoding data for transmissions from a source to a destination over a communications channel is provided. The method operates on an ordered set of source symbols and may generate zero or more redundant symbols from the source symbols, wherein data is encoded in a first step according... Agent: Townsend And Townsend And Crew, LLP

20070300128 - A method and apparatus of defect areas management: A method and the apparatus of defect areas management includes the steps as following: reading a defect area table in a random access memory; if the area is readable, then read the area. If the area is not accessible, then label and add one count in the defect area table... Agent: G.link Co., Ltd

20070300129 - System, method and storage medium for providing fault detection and correction in a memory subsystem: A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070300130 - Method of error correction coding for multiple-sector pages in flash memory devices: A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to... Agent: Anderson, Levine & Lintel L.L.P.

20070300131 - Register file cell with soft error detection and circuits and methods using the cell: Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and... Agent: Ryan, Mason & Lewis, LLP

20070300132 - Apparatus and method for defect replacement: Apparatuses and methods for defect replacement when an optical storage medium is read are provided. When the defect management is LOW, a pick-up head retrieves a set of data from the optical storage medium; a defect detector detects whether there is a defect in the set; if yes, a processor... Agent: Ladas & Parry

20070300133 - Method for recovering data in a tape drive system: A method is disclosed. The method includes performing a first read operation at a tape drive, determining if a minimum number of data bytes have been recovered in the first read operation to perform error correcting codes (ECC), performing a second read operation if the minimum number of data bytes... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20070300134 - Data transmitting device, data receiving device, and data distribution system: The data receiving device (100) includes media packet transmitting means (102) for transmitting media streams, a plurality of FEC packet calculating means (103) for calculating FEC packets having different parameters, and a plurality of FEC packet transmitting means (104) for transmitting the FEC packets as a FEC stream. Further, the... Agent: Birch Stewart Kolasch & Birch

20070300135 - Error correction encoding apparatus and error correction encoding method used therein: An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an error floor area without using any computer experiments. In a... Agent: Young & Thompson

20070300136 - Fast decoding of reed-solomon code: A technique to perform fast decoding of a Reed-Solomon code. A first multiplier unit multiplies a matrix Bh with a column vector v using common adders to produce a column vector v1. The vector v represents one of an error locator polynomial, an error evaluator polynomial, and a derivative polynomial... Agent: Blakely Sokoloff Taylor & Zafman

20070300137 - Reed solomon decoding of signals having variable input data rates: A method and apparatus are disclosed to achieve a resource optimized, class of RS decoders, featuring balanced pipelined stages and parallel algorithmic components. Our RS decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction.... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070300138 - Minimal hardware implementation of non-parity and parity trellis: Minimal hardware implementation of non-parity and parity trellis. A novel means is presented by which more than one type of trellis can be represented using a minimal amount of hardware. In magnetic recording systems and other communication systems types, there is oftentimes a need to switch between trellises which support... Agent: Garlick Harrison & Markison

20070300139 - Unified stopping criteria for binary and duobinary turbo decoding in a software-defined radio system: A decoding process for decoding a received block of N systematic binary data samples or N systematic duobinary data samples using a maximum a posteriori probability (MAP) decoding algorithm. The decoding process calculates a set of four log-likelihood values using the corresponding forward state metric, reverse state metric, and branch... Agent: Docket Clerk

20070300140 - Electronic device having a plurality of modes of operation: An electronic device including a display, a first user input, for enabling access to a plurality of functions, a second user input, and a controller, operable, in response to an input, to change the mode of operation of the device from a first, active mode of operation, in which the... Agent: Harrington & Smith, PC

20070294560 - Support self-heal tool: A self-heal tool performs self-healing tasks such as diagnostic and repair tasks at the computer host to resolve a user problem. The self-heal tool includes an instruction file and a self-heal engine which executes instructions in the instruction file. The self-healing tasks can therefore be defined independently of the engine.... Agent: Vierra Magen/microsoft Corporation

20070294561 - Providing independent clock failover for scalable blade servers: Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20070294562 - San management method and a san management system: A SAN management method in which a host to which an application should be shifted can be decided so that the influence of data transfer load is eliminated as extremely as possible. To shift an application A operating on a host A to another host, a management server performs a... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070294563 - Method and system to provide high availability of shared data: A data storage system and method are described. The system may comprise a data repository to store data, and first and second storage controllers. The first and second storage controllers may be connected via at least one network device to the data repository. One or more clients may be connected... Agent: Schwegman, Lundberg & Woessner, P.A.

20070294567 - Replacing member disks of disk arrays with spare disks: Member disks of a hard disk drive array are replaced with spare disks. First, a member disk of an array of member disks is replaced with a spare disk. The reliability factor of the member disk is lower than the reliability factor of the array, and the reliability factor of... Agent: Law Offices Of Michael Dryja

20070294566 - Restoring computing devices using network boot: A method of restoring information comprising initializing a computer from a networked device, selecting a backup image that includes user generated information, disposed on the networked device, and reinstalling the backup image from the networked device to the computer.... Agent: Microsoft Corporation

20070294568 - Storage system and method of managing data using the same: A storage apparatus includes a storage unit and a controller for controlling the storage unit. A data volume, a journal volume, and a snapshot volume are formed in the storage unit. The storage apparatus stores, in accordance with a write request sent from a host apparatus, data specified in the... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070294570 - Method and system for bad block management in raid arrays: A system and method for managing bad blocks that utilizes a remapping pool formed across an array of disks to remap bad blocks formed on individual disks. When a bad block is discovered in a particular disk the bad block is then remapped within the remapping pool and is stored... Agent: Baker Botts, LLP

20070294574 - Dual computer for system backup and being fault-tolerant: The present invention is to provide a computer for backup and being fault-tolerant comprising a CPU connected to an I/O port, a dual-port memory, a memory address decoder, a bus tri-state buffer, and an arbitration circuit, where the CPU can access data of the dual-port memory based on a decoded... Agent: Bacon & Thomas, PLLC

20070294577 - Automatic migratable services: Singleton services can be automatically migrated from one application server to another in a cluster using a lease table and a migration master in case of a failure of the first application server.... Agent: Fliesler Meyer LLP

20070294578 - Method and apparatus for facilitating process migration: A system that migrates a process from a source computer system to a target computer system. During operation, the system generates a checkpoint for the process on the source computer system, wherein the checkpoint includes a kernel state for the process. Next, the system swaps out dirty pages of a... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070294579 - Methods and apparatus for eliminating lower value tests for a unit under test, and for developing a plurality of different and synchronized test execution orders for testing a plurality of units under test: In one embodiment, test execution times are determined for a plurality of tests that are to be executed for a single unit under test (UUT). Test dependencies are also determined for the tests, as are the instruments needed to execute the tests. Then, in response to the test execution times,... Agent: Agilent Technologies Inc.

20070294580 - Virtual tester architecture: A virtual tester, for testing a device logic simulator, includes multiple virtual instruments that generate stimulus messages for delivery to the device logic simulator and for receiving response messages generated by the device logic simulator. Each virtual instrument models a corresponding hardware test instrument and comprises a concrete instrument model... Agent: Smith-hill And Bedell, P.C.

20070294586 - Automated extensible user interface testing: Automated extensible user interface testing supports testing of a user interface of a program. Test data is accessed, the test data including multiple test steps. Each test step describes at least a part of a test to be performed on the user interface. For each of the multiple test steps,... Agent: Lee & Hayes PLLC

20070294587 - Improving performance of a processor having a defective cache: In one embodiment, a method for improving performance of a processor having a defective cache includes accessing first object code and generating second object code from the first object code. The generation of the second object code takes into account one or more locations of one or more defects in... Agent: Baker Botts L.L.P.

20070294590 - Compression scheme to reduce the bandwidth requirements for continuous trace stream encoding of system performance: A system and method of counting event patterns in order to reduce the bandwidth of event data sent to a monitoring computer. The event patterns are output as one or more data packets indicating the event pattern and a number of occurrences of the pattern.... Agent: Texas Instruments Incorporated

20070294593 - Customizable system for the automatic gathering of software service information: The present invention provides methods and systems for a customizable collector application, which automates multiple diagnostic techniques to obtain sets of diagnostic information. The collector application is easily customizable for use by different products, and may reduce the diagnostic information gathering to a single session. This includes gathering all of... Agent: Mh2 Technology Law Group, LLP

20070294592 - Reducing the size of a data stream produced during instruction tracing: Tracing logic for monitoring a stream of processing instructions from a program being processed by a data processor is disclosed, said tracing logic comprising monitoring logic operable to detect processing of said instructions in said instruction stream; detect which of said instructions in said instruction stream are conditional direct branch... Agent: Nixon & Vanderhye, PC

20070294594 - Collaborative web-based airplane level failure effects analysis tool: Embodiments of methods, apparatuses, and articles for receiving system malfunction effects data including at least one malfunction and a plurality of direct and indirect effects associated with each of the at least one malfunction and storing the received system malfunction effects data, are described herein. The embodiments may also facilitate... Agent: Schwabe, Williamson & Wyatt, P.C.

20070294596 - Inter-tier failure detection using central aggregation point: The present invention provides inter-tier failure detection using a central aggregation point. A method in accordance with an embodiment of the present invention includes: performing intra-tier failure detection in a first tier of a multi-tier system; providing a failure status to a central aggregation point in the first tier; and... Agent: Hoffman Warnick & Dalessandro LLC

20070294597 - Apparatus, system, and method for signaling logical errors in an eis remote function call: An apparatus, system, and method are disclosed to signal a logical error in a function call made by an integration adapter. The apparatus includes an communication module, a code extraction module, a comparison module, and an error report module. The communication module receives a business object having an error dictionary... Agent: Kunzler & Mckenzie

20070294598 - Hard disk drive with built-in mirror: Methods and systems are provided for mirroring data within a single hard drive. A hard disk drive (210) can receive a write command to write data on platters (216) therein. The data is then written in two locations (212, 214) using two different read/write heads. Additionally, hard disk drive (210)... Agent: Gateway, Inc. Attn: Patent Attorney

20070294599 - Method for patching a read-only memory and a data processing system comprising a means of patching the read-only memory based on patch contexts: A method for patching a read-only memory (ROM) includes providing multiple patch contexts in a patch contexts memory, with the ROM providing information for a data processing system. Each patch context defines a different set of patches, with each patch comprising a patch address and corresponding patch data. The patch... Agent: Eschweiler & Associates, LLC National City Bank Building

20070294601 - Watchdog processors in multicore systems: Systems and methods are provided for securing a multicore computer chip with a watchdog processor. In a system with a watchdog process and any number of other processors and components, the watchdog processor monitors bus communications between the second processor and at least one third component. The watchdog processor may... Agent: Woodcock Washburn LLP (microsoft Corporation)

20070294604 - Multiple subsystem error reporting: To log errors of a plurality of subsystems, a master reporting tool provides a table identifying the subsystems and their interface protocol addresses with respect to a network. A subsystem reports errors, via the network, to the master reporting tool, and the reporting subsystem identifies and reports other subsystems associated... Agent: John H. Holcombe IBM Corporation,IPLaw Dept.

20070294564 - High availability storage system: Methods and systems are described for a storage system including at least two controllers configured to handle write requests and a non-volatile cache connected to both controllers that stores data received from the controllers. The non-volatile cache is accessible by the first and second controllers using an interface technology permitting... Agent: Hewlett Packard Company

20070294565 - Simplified parity disk generation in a redundant array of inexpensive disks: A method for efficiently writing data to a redundant array of inexpensive disks (RAID) includes: writing an entire slice to the RAID at one time, wherein a slice is a portion of the data to be written to each disk in the RAID; and maintaining information in the RAID for... Agent: Volpe And Koenig, P.C. Net App

20070294569 - Method and apparatus of recording data in the optical recording medium: A recording medium and apparatus and method for managing defective areas are discussed. According to an embodiment a controller determining whether or not to replace a defective block with a replacement block when a writing or reading data to or from the optical recording medium, based upon a data type... Agent: Birch Stewart Kolasch & Birch

20070294571 - Method and apparatus of recording data in the optical recording medium: A system of recording or reading data are discussed. According to an embodiment, the system includes: a host device transmitting a write or read command and data to be written or receiving data based on the read command; and a recording/reproducing device, operatively coupled to the host device via interface,... Agent: Birch Stewart Kolasch & Birch

20070294572 - Adaptive sas phy configuration: A SAS expander adaptively configures a Serial-Attached-SCSI (SAS) PHY to accommodate varying lengths of a cable coupling the PHY to a remote PHY. The expander (a) configures the SAS PHY with settings of an entry of a table of PHY configuration settings, each entry in the table having different PHY... Agent: Huffman Law Group, P.C.

20070294573 - Method and system for improving the availability of software processes utilizing configurable finite state tables: The invention provides a system and method for providing a high availability application at low cost for a wide range of solution architectures. A user runs a simplistic web-based wizard to install the high availability application. Then, a user designs the high availability application's logic for an individual process or... Agent: Cardinal Law Group

20070294576 - Method and apparatus to insert special instruction: A method and apparatus to insert special instruction. At least one of the illustrative embodiments is a method comprising converting a first representation of a computer program to a second representation, and inserting into the second representation a special instruction not needed to implement functionality in the first representation. The... Agent: Hewlett Packard Company

20070294575 - Method and system for maintaining backup copies of firmware: A method and system for maintaining backup copies of firmware. More particularly, embodiments of the present invention provide a method that includes monitoring an execution of at least one firmware component, and causing a backup copy of the at least one firmware component to be generated if the at least... Agent: Sawyer Law Group LLP

20070294581 - System and method for distributing system tests in parallel computing environments: A mechanism for the distribution of a test vector for a system test to a parallel computing environment is discussed. A test vector which controls the parameterization of a system test being conducted is provided as an input parameter to a function. In one implementation, the test vector is declared... Agent: Lahive & Cockfield, LLP

20070294582 - Reporting software raid configuration to system bios: An operating system (OS) agent may write information about hard disk drives associated with a software RAID and/or those hard disk drives being boot configured to a non-volatile memory of an information handling system. Then during power on self test (POST) of the information handling system a determination is made... Agent: Baker Botts, LLP

20070294584 - Detection and isolation of data items causing computer process crashes: Described herein is technology for, among other things, detecting a data item that causes a process running within a computer system processing multiple data items to crash when the data item is processed. The technology involves associating a unique identifier with each data item prior to the data item being... Agent: Microsoft Corporation

20070294583 - Device and method for analyzing embedded systems for safety-critical computer systems in motor vehicles: The invention describes an analyzing device for an embedded system (9), which has at least one CPU (1), at least one CPU bus (2), and at least one memory (3). The device includes a communication module (4) for the input or output of analysis data using a test interface (5),... Agent: Continental Teves, Inc.

20070294585 - Method and system of a processor-agnostic encoded debug-architecture in a pipelined environment: A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having... Agent: Texas Instruments Incorporated

20070294589 - Invalidation of storage control unit cache metadata: Method, apparatus and program product are provided for the invalidation of faulty metadata in a storage controller coupled to a host device. Faulty metadata may include metadata which no longer matches the associated customer data tracks stored on a DASD or other storage device. When faulty metadata is detected, metadata... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070294588 - Performing a diagnostic on a block of memory associated with a correctable read error: In one embodiment, a block of memory associated with a read error is assigned to a suspect state to wait until there is processing capacity available to perform a diagnostic. If there is processing capacity available to perform the diagnostic, the block of memory can be assigned to a diagnostic... Agent: Trop Pruner & Hu, PC

20070294591 - Method and apparatus for identifying a failure mechanism for a component in a computer system: One embodiment of the present invention provides a system that identifies a failure mechanism for a component. The system first constructs a library of failure signatures from a set of components, wherein each failure signature in the library characterizes a known failure mechanism associated with a component in the set... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070294595 - Detecting errors in transmitted data: This invention relates to methods and apparatus for detecting errors in transmitted data. In one embodiment, a method includes the steps of transmitting data, accumulating a transmit sum, receiving the data, accumulating a receive sum, comparing the transmit and receive sums; and evaluating the result of the comparison for determining... Agent: Epson Research And Development Inc Intellectual Property Dept

20070294602 - Fault tolerant data processing: A method of identifying a valid version of a data value and voting on separate instances of the data value is described. A processor receives an instance of the data value generated by one processor and a transmitted version of that generated instance transmitted by another processor and compares the... Agent: Osha Liang L.L.P.

20070294600 - Method of detecting heartbeats and device thereof: A method of detecting heartbeats and the device thereof are applied to a cluster server. It includes a first controller, a second controller, and a detecting module. The detecting module does the counting according to a first predetermined period. If the detecting module receives a first reset signal of the... Agent: Birch Stewart Kolasch & Birch

20070294603 - Method for responding to errors occurring during operation of a networked medical system: In a method for responding to errors that occur during operation of a medical system, having a number of computer workstations connected via a network, upon failure of a system component that is necessary for proper operation of a system program, while the system program is running on one of... Agent: Schiff Hardin, LLP Patent Department

20070294605 - Circuit configuration with serial test interface or serial test operating-mode procedure: The invention relates to a circuit configuration with a serial test interface (TIF) to control a test operation mode, a freely programmable digital processor (CPU), a housing (G) for the accommodation of a test interface (TIF) and the processor (CPU) with terminals or connectors (C0, C1) for data and/or signal... Agent: Maginot, Moore & Beck Chase Tower

20070294606 - Accelerating scan test by re-using response data as stimulus data: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the... Agent: Texas Instruments Incorporated

20070294607 - Ldpc-code generating method, communication apparatus, and code-string generating method: An order-ensemble searching unit classifies a distribution of reception signals at each bit position of a modulation symbol, and searches an order ensemble of a parity check matrix that minimizes an SNR threshold value. A code generating unit generates a parity check matrix and a generation matrix, based on the... Agent: Birch Stewart Kolasch & Birch

20070294608 - Plasma process power delivery system and method with event-controlled data storage: A plasma process power delivery system includes one or more event-ascertaining devices within the plasma process power delivery system, a controller in communication with the one or more event ascertaining devices, a first memory, a second memory, a data transmission connection, and a plasma process monitoring system. The data transmission... Agent: Fish & Richardson PC

20070294609 - Recording medium, recording method and apparatus, reproducing method and apparatus, data transmitting method, and data decrypting method: A recording medium having an area in which data that has been encoded with a first error correction code is recorded, wherein data that can be decoded with a second error correction code that is different from the first error correction code is recorded to the area along with the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070283188 - Diagnosis in automotive applications: A system and method for constructing a diagnosis function for mapping a symptom of a fault in an electromechanical system onto the fault by simulating the electromechanical system in at least a fault mode and a node fault mode, and learning a classifier function from the collected simulation results for... Agent: Darby & Darby P.C.

20070283193 - Soft error location and sensitivity detection for programmable devices: Circuits, methods, and apparatus that detect whether a soft error that occurs in stored configuration data is a false positive that can be ignored such that reloading configuration data or other remedial measures are not unnecessarily performed. One example provides an integrated circuit including an error detection circuit and a... Agent: Townsend And Townsend And Crew LLP/ 015114

20070283186 - Virtual array failover: Failover is provided between groups of logical units of storage presented as virtual arrays. A primary virtual array has at least one primary virtual port coupled to a fabric, each primary virtual port having a source virtual port name and a source virtual port address. A secondary virtual array has... Agent: Guerin & Rodriguez, LLP

20070283187 - Bios for saving and restoring operational state in the absence of ac power: A system is provided with a basic input/output system (BIOS) with the ability to intervene, when a suspend process is initiated in response to an AC failure condition to place the system in a suspended to memory state, to initiate a number of data transfer operations to save a persistent... Agent: Schwabe, Williamson & Wyatt, P.C.

20070283189 - Method and a device for diagnosing technical equipment: The subject of the invention is a method and a device for diagnosing technical equipment, in which the equipment condition is assessed on the basis of the results of various technical verification tests. In this method the configuration of individual measuring tests is stored in separate templates, the component elements... Agent: Abb Inc. Legal Department-4u6

20070283190 - Runtime reconfiguration of reconfigurable circuits: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070283192 - Automated threat analysis: An automated threat analysis system comprising a core in an isolated environment, the core associated with an input interface and an output interface. The core comprises one or more core components and an operating system having at least one library hooked to at least one of the one or more... Agent: Eric D. Cohen

20070283191 - Integrated circuit with debug support interface: A high speed debug support interface has circuits to interface on-chip debug support circuits to a high bandwidth communications port means located on the surface of a system integrated circuit (101) and to on-chip debug support circuits (100). The communication port means can be realised by bonding or integrating special... Agent: Blakely Sokoloff Taylor & Zafman

20070283194 - Log collection, structuring and processing: The present invention generally relates to log message processing such that events can be detected and alarms can be generated. For example, log messages are generated by a variety of network platforms (e.g., Windows servers, Linux servers, UNIX servers, databases, workstations, etc.). Often, relatively large numbers of logs are generated... Agent: Marsh, Fischmann & Breyfogle LLP

20070283195 - Fault detection using redundant virtual machines: A technique to detect errors in a computer system. More particularly, at least one embodiment of the invention relates to using redundant virtual machines and comparison logic to detect errors occurring in input/output (I/O) operations in a computer system.... Agent: Intel Corporation C/o Intellevate, LLC

20070283196 - Flash memory device and data i/o operation method thereof: A flash memory device comprises a memory cell array, an input buffer unit, an output driver unit, a first page buffer unit, a second page buffer unit, a first data I/O unit, and a second data I/O unit. The memory cell array includes two or more memory banks. During a... Agent: Townsend And Townsend And Crew, LLP

20070283197 - Mapping logic for controlling loading of the select ram of an error data crossbar multiplexer: Methods and circuits for efficient configuration an error data crossover configuration circuit of an integrated circuit tester allows simultaneous DUT channel configuration for multiple identical DUTs for an error data control circuit.... Agent: Verigy

20070283199 - Method and apparatus for entering special mode in integrated circuit: A method and an apparatus for entering special mode in integrated circuit (IC) or logic circuit are provided. The IC or logic circuit receives a plurality of data bits and a reset signal, wherein the reset signal is used to reset the IC or the logic circuit. The apparatus includes... Agent: Jianq Chyun Intellectual Property Office

20070283198 - Parallel bit test circuits for testing semiconductor memory devices and related methods: An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first... Agent: Myers Bigel Sibley & Sajovec

20070283203 - Semiconductor apparatus and method of disposing observation flip-flop: A semiconductor apparatus includes a functional block to observe a state of a signal line in the apparatus. The functional block includes a signal transfer section to receive, transmit and output the state of the signal line, and an observation flip-flop to store a state of an input terminal or... Agent: Mcginn Intellectual Property Law Group, PLLC

20070283202 - Compactor independent fault diagnosis: Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In certain disclosed embodiments, methods for diagnosing faults from compressed test responses are provided. For example, in one exemplary embodiment, a circuit description of an at least partially scan-based circuit-under-test and a compactor for compacting test responses captured in... Agent: Klarquist Sparkman, LLP

20070283201 - Functional frequency testing of integrated circuits: A method and circuits for testing an integrated circuit at functional clock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency.... Agent: Schmeiser, Olsen & Watts

20070283200 - Scan compression architecture for a design for testability compiler used in system-on-chip software design tools: A scan compression architecture for a design for testability compiler used in system-on-chip software design tools includes a first scan architecture including a first scan compressor/decompressor configuration connected to a first predetermined set of pins, and a second scan architecture including a second scan compressor/decompressor configuration connected to a subset... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070283204 - Method and system for deterministic bist: Methods, systems and articles of manufactures are provided for built-in self-testing of high-performance circuits configured to generate and apply test patterns to a circuit under test (CUT). A logic structure in communication with the CUT and a memory device generates a plurality of test patterns from original test seeds, wherein... Agent: Driggs, Hogg & Fry Co. L.p.a.

20070283205 - System and method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies: A system and method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies are provided. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070283206 - Reliability evaluation device, reliability evaluation method, and computer program product: A reliability evaluation device includes a route acquiring unit that acquires a route from a starting point to a verification point of an application procedure as a group of paths indicative of relation between objects used for identity verification at each step based on data that includes the paths, a... Agent: Staas & Halsey LLP

20070283208 - Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus diagnostic features: Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code for transfer over a bus in two or more transfers Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A symbol... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070283207 - Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with bus timing improvements: Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070283209 - Loading the input memory of an ldpc decoder with data for decoding: An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N-K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to... Agent: Seed Intellectual Property Law Group PLLC

20070283210 - Design of spherical lattice codes for lattice and lattice-reduction-aided decoders: Methods and apparatus for designing spherical lattice codebooks for use in data transmission systems are provided. A spherical lattice codebook is constructed by determining the channel statistics of one or more channels, which can be accomplished by observing a sufficiently large set of channel realizations. After determining the channel statistics,... Agent: Nec Laboratories America, Inc.

20070283211 - System and method for communicating data using iterative equalizing and decoding and recursive inner code: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing... Agent: Christopher F. Regan, Esquire Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.

20070283212 - System and method for communicating data using iterative equalizing and decoding and recursive inner code: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070283216 - Apparatus and method for transmitting/receiving signal in a communication system: A signal transmission apparatus in a communication system is disclosed. A channel interleaver generates an interleaved vector by channel-interleaving a Low Density Parity Check (LDPC) codeword according to a channel interleaving rule, and a modulator generates a modulation symbol by modulating the interleaved vector according to a modulation scheme. The... Agent: The Farrell Law Firm, P.C.

20070283217 - Correction of data errors in a memory buffer: Methods, circuits, and disk drive that correct errors in data that is temporarily stored in a memory buffer are disclosed. An error detection code and an error correction code are generated for data. The data, the error detection code, and the error correction code are stored in the memory buffer.... Agent: Myers Bigel Sibley & Sajovec, P.A.

20070283214 - Corruption-resistant data porting with multiple error correction schemes: To export (e.g., store or transmit) input data, only the input data are encoded separately according to first and second encoding schemes to provide first and second encoded data. The first encoded data and the second encoded data are exported. Upon importing (e.g., retrieving or receiving) representations of the exported... Agent: Mark M. Friedman

20070283213 - Method and apparatus for self-compensation on belief-propagation algorithm: A self-compensation method includes: firstly using a min-sum algorithm to derive multiple output values in order to approach a operational result of the checking side of a belief-propagation; and then checking the present iteration number of decoding based on a checking rule; and finally, if in the previous step the... Agent: Bucknam And Archer

20070283215 - Parity check decoder architecture: A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.... Agent: Texas Instruments Incorporated

20070283221 - Apparatus and method for coding/decoding block low density parity check code in a mobile communication system: A method for generating a parity check matrix of a block LDPC code. The parity check matrix includes an information part corresponding to an information word and a first parity part and a second parity part each corresponding to a parity. The method includes determining a size of the parity... Agent: The Farrell Law Firm, P.C.

20070283219 - Apparatus and method for transmitting/receiving signal in communication system: An apparatus and method for encoding/decoding a non-binary low density parity check (LDPC) code in a communication system. The apparatus and method includes receiving an information vector; generating a non-binary LDPC code by encoding the information vector into a non-binary LDPC code according to a non-binary LDPC encoding scheme.... Agent: The Farrell Law Firm, P.C.

20070283218 - Low density parity check code decoder: An error correction system for decoding transmitted data in multichannels is disclosed. The system uses low density parity check nodes. A method of error correction using LDPC is also disclosed.... Agent: Hedman & Costigan P.C.

20070283220 - Method, apparatus and computer program product providing soft iterative recursive least squares (rls) channel estimator: Disclosed is an apparatus having a detector for an iterative LDPC-coded MIMO-OFDM system, where the detector is configured to use a structured irregular LDPC code in conjunction with a belief propagation algorithm. Also disclosed is an apparatus having a detector for a structured irregular LDPC-coded MIMO-OFDM system, where the detector... Agent: Harrington & Smith, PC

20070283222 - Apparatus, system, and method for dynamic recovery and restoration from design defects in an integrated circuit: An apparatus, system, and method are disclosed for the recovery from a design defect in an integrated circuit. The apparatus includes an error check module, a control settings module, a retry module, and a recovery module. The error check module discovers that an error has occurred during an operation. The... Agent: Kunzler & Mckenzie

20070283224 - System and method for efficient uncorrectable error detection in flash memory: A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is... Agent: Pitney Bowes Inc. 35 Waterview Drive

20070283223 - Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code with all checkbits transferred last: Systems, method, and computer program products for providing a nested two-bit symbol bus error correcting code scheme for transfer over a bus in two or more transfers. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code including original checkbits. A... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070283225 - Coding system and decoding system: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070283226 - Coding system and decoding system: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070283227 - Error correction decoding by trial and error: A representation of a codeword is decoded by applying a first decoder of the codeword to the representation of the codeword. If applying the first decoder fails to decode the representation of the codeword then a second decoder of the codeword is applied to the representation of the codeword. Preferably,... Agent: Mark M. Friedman

20070283228 - Coding system and decoding system: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070283229 - Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code: Systems, methods and computer program products for providing a nested two-bit symbol bus error correcting code. Methods include constructing a nested error correcting code (ECC) scheme. The method includes receiving a Hamming distance n code. A symbol correcting code H-matrix is created by iteratively adding rows of H-matrix bits on... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070283230 - System and method for decreasing decoder complexity: A technique for implementing a radio receiver to reduce complexity involves utilizing a reduced-complexity decoding technique for a shortened Hamming (15, 10) block code.... Agent: Perkins Coie LLP

20070283231 - Multi-standard scramble code generation using galois field arithmetic: This invention is a method of using a Fibonacci form linear feedback shift register. The Fibonacci form linear feedback shift register having an initial state and a set of taps is converter into an equivalent Galois form linear feedback shift register. The Galois form linear feedback shift register state is... Agent: Texas Instruments Incorporated

20070283232 - Method for near maximum-likelihood sequential decoding: A method for near maximum-likelihood sequential decoding is provided. According to the method, paths unlikely to become the maximum-likely path are deleted during decoding through a level threshold to reduce decoding complexity. Besides, the method performs maximum-likelihood decoding through sequential decoding by adopting a metric, so that a received signal... Agent: Jianq Chyun Intellectual Property Office

20070283233 - Apparatus and method for receiving image: An image communication apparatus includes a transmitter that transmits an e-mail with data attached, via a computer network, a receiver that receives an e-mail with data attached, via the computer network, and a controller that converts the attached data into image data. The controller judges whether or not the received... Agent: Greenblum & Bernstein, P.L.C

20070283234 - Image data management and management program: A management program for managing a plurality of image data recorded on the recording section by storing the image data into a destination recording section according to a unit of recording medium or image data type, wherein original image data as a basis for the missing or modified image data... Agent: Frishauf, Holtz, Goodman & Chick, PC