Error detection/correction and fault detection/recovery inventions 11/07

20070277059 - Storage device, control device, and error reporting method: A storage device performs a reading process or a writing process based on a command received from an upper-level device, and when an error occurs in the reading process or the writing process, generates a predetermined sense according to a result of a retry, and reports the predetermined sense to... Agent: Greer, Burns & Crain

20070277060 - Use of alternative value in cell detection: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible... Agent: Fish & Richardson P.C.

20070277055 - Stored memory recovery system: Various embodiments of systems and methods for preserving saved memory states to which a computer system can be restored are disclosed. In certain embodiments, the systems and methods intercept write operations to protected memory locations and redirect them to alternate memory locations. Embodiments of the systems and methods include creation... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070277056 - Transparent checkpointing and process migration in a distributed system: A distributed system for creating a checkpoint for a plurality of processes running on the distributed system. The distributed system includes a plurality of compute nodes with an operating system executing on each compute node. A checkpoint library resides at the user level on each of the compute nodes, and... Agent: Mcdermott Will & Emery LLP

20070277057 - Method and control device for displaying diagnosis data of a printer or copier: In a method for outputting data of a diagnosis data stream of a printer or copier, the diagnosis data stream comprises first data of a first data type and at least second data of the second data type, the first data and the second data each including structure date and... Agent: Schiff Hardin, LLP Patent Department

20070277058 - Scalable method of continuous monitoring the remotely accessible resources against the node failures for very large clusters: The notion of controlling, using and monitoring remote resources in a distributed data processing system through the use of proxy resource managers and agents is extended to provide failover capability so that resource coverage is preserved and maintained even in the event of either temporary or longer duration node failure.... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070277061 - System, method, computer program product and article of manufacture for remote fault diagnosis and correction in a computer system: A method for fault diagnosis in a computer system comprises producing a log file of a user's interaction with a Graphical User Interface (GUI) of a user computer, omitting from the log file any text entered by the user during the interaction, and diagnosing the fault by reviewing the log... Agent: Gordon & Jacobson, P.C.

20070277062 - Connection error avoidance for apparatus connected to a power supply: According to a first general aspect of the present invention, there is provided a logic arrangement for reducing incidence of errors in connections between a power consumer apparatus and a power supply apparatus, the logic arrangement comprising: a pattern-generating component for generating an identifiable pattern in a load to be... Agent: Zilka-kotab, PC

20070277063 - Eye width characterization mechanism: An eye width characterization mechanism determines a pass setting of a sampling phase positioned within an eye width of received data. The sampling phase is incremented in a first direction from the pass setting until the sampling phase is outside the eye width of the received data. The sampling phase... Agent: Blakely Sokoloff Taylor & Zafman

20070277064 - Reconfigurable convolutional interleaver/deinterleaver using minimum amount of memory and an address generator: An address generator applied to a convolutional interleaver/deinterleaver generates an address for reading/storing data symbols from/to a memory. The memory conceptually divides into branches, segments and cells. The address generator maintains cyclic counters including a cyclic branch counter, a cyclic cell counter, N cyclic segment counters for counting the branch,... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070277065 - Test apparatus and test method: A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory... Agent: Osha Liang L.L.P.

20070277066 - System and method for more efficiently using error correction codes to facilitate memory device testing: A memory device includes an ECC and test circuit. In a normal mode, the circuit performs ECC conventional functions. In a test mode, the least significant bit of received data is used to generate test data. If the received bit is “0,” the test data bits are all “0,” and... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070277067 - Fault detection method and apparatus: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the... Agent: Bourque & Associates Intellectual Property Attorneys, P.A.

20070277068 - System and method of state point correspondence with constrained function determination: A system and method for determining scan chain correspondence including defining a reference scan chain having reference latches and a reference constraint, each of the reference latches having a reference latch logic cone, the reference constraint having a reference constraint logic cone and being associated with one of the reference... Agent: Ibm Corp. (clg) C/o Cardinal Law Group

20070277069 - Serializer/deserializer circuit for jitter sensitivity characterization: Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output,... Agent: Ibm Microelectronics Intellectual Property Law

20070277070 - Apparatus and method for checking an error detection functionality of a data processor: An apparatus for checking an error detection functionality of a data processing circuit, comprising an arithmetic logic unit, which provides an output datum based on an input datum, and an error detection circuit that executes the error detection functionality and detects an error based on the output datum during correct... Agent: Dickstein Shapiro LLP

20070277071 - Write-side calibration for data interface: Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry,... Agent: Townsend And Townsend And Crew LLP/ 015114

20070277072 - Method to suspend automatic repeat request (arq) reset: A method (100) of operating an Automatic Repeat Request (ARQ) transmitter (102) and an ARQ receiver (104) suspends an ARQ reset under circumstances where an ARQ reset would be superfluous. When a transmitter has a final currently-available data block, it deactivates its transmitter ARQ sync loss timer (172) and transmits... Agent: Motorola Inc

20070277073 - Communication device, communication system, method of operating a communication device and arq feedback message: An ARQ feedback message provides feedback information on a series of sequential data blocks received by a receiver (26). The ARQ feedback message comprises an information element (900). The information element (900) indicates for each sequence of a plurality of sequences of the series of sequential data blocks whether each... Agent: Motorola Inc

20070277074 - Sonar collision avoidance system: A method for generating a feedback message for ARQ, the method including: a) recording an ACK type in a first field; b) estimating the last block sequence number of successively ACKed blocks and recording the estimated last block sequence number in a second field; c) recording the number of groups... Agent: The Farrell Law Firm, P.C.

20070277075 - Method of generating parity information using low density parity check: A method of independently generating row parity information and column parity information in an encoding process using a low density parity check (LDPC) matrix includes generating code word vectors by generating column parity information using a parity check matrix and message information; selecting code word bits for generating row parity... Agent: Stein, Mcewen & Bui, LLP

20070277076 - Semiconductor memory device: A semiconductor memory device in which data is not written in a transfer destination under a state including an error when an error occurs at the time of reading data at the transfer destination. The semiconductor memory device (1) comprising a nonvolatile memory (2) having a data writing unit smaller... Agent: Greenblum & Bernstein, P.L.C

20070277077 - Burst transmission in a digital broadcasting network: A multiprotocol encapsulation forward error correction (MPE-FEC) frame comprising datagrams and FEC data is shown wherein an MPE encapsulator places datagrams in MPE sections and FEC data in MPE-FEC sections. A time slicing block forms a sequence of bursts and dividing the MPE-FEC frame between bursts, such that MPE sections... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070277078 - Signal decoding apparatus and signal decoding method: A signal decoding apparatus preventing substantial noise from being produced when transmission error occurs during decoding of scalable-coded information. In this signal decoding apparatus, a coded information operation section (601) performs error detection for base layer coded information, first enhancement layer coded information and second enhancement layer coded information using... Agent: Stevens, Davis, Miller & Mosher, LLP

20070277080 - Method for decoding multiword information: A method for decoding multiword information comprises steps (a) to (e). In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g.,... Agent: Connolly Bove Lodge & Hutz LLP

20070277079 - Method for error correction of program-associated data: For error correction of program-associated data in frames, e.g., DAB data packets, with code words being used over multiple data packets, redundancy information for error correction is added while retaining the original frame structure. The information about the length of the program-associated data is additionally protected by a code.... Agent: Kenyon & Kenyon LLP

20070277081 - Dynamic power adjusting device for viterbi decoder: A dynamic power adjusting device for a Viterbi decoder is disclosed. The device includes a processing unit for receiving a plurality of data to be decoded, detecting whether the data to be decoded have any bit errors, and estimating a number of the bit errors of the data. The device... Agent: Birch Stewart Kolasch & Birch

20070277082 - Retransmission control method and communications device: A retransmission control method comprising: generating N parity check matrices; generating a generator matrix containing a check symbol generator matrix contained in the first parity check matrix; transmitting the codeword generated by using the generator matrix to another communications device; generating, when the communications device receives a NAK in response... Agent: Birch Stewart Kolasch & Birch

20070277083 - Data handling device that corects errors in a data memory: A data handling device is provided with a data memory (10) with an address input and a data output, for outputting multi-bit words. The data memory (10) has a structure that gives rise to potential errors at correlated positions in words from a group of words. An erasure memory unit... Agent: Philips Intellectual Property & Standards

20070277084 - Method and system for error detection for improving data integrity in protocol offloading: Aspects of a method and system are provided for error detection for improving data integrity in protocol offloading. Aspects of the invention may enable receiving a block of data having a modulo-based input error detection code and an error correction term appended thereto, calculating an output error detection code of... Agent: Mcandrews Held & Malloy, Ltd

20070277085 - Error detection device for an address decoder, and device for error detection for an address decoder: An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the... Agent: Dickstein Shapiro LLP

20070271480 - Method and apparatus to conceal error in decoded audio signal: A method and apparatus to decode audio data constructed with a plurality of layers. An error concealment method of process a decoded bitstream selects one of a frequency domain and a time domain in order to conceal the errors, detects a position where the errors exist in a frame when... Agent: Stanzione & Kim, LLP

20070271481 - Storage controller: The present invention provides a storage control unit having dual control units wherein a controller in one control unit, that has received an I/O request from a host, issues an I/O request to an initiator in another control unit using a control path between the controllers in the control units,... Agent: Sughrue Mion, PLLC

20070271482 - Programmable address space built-in self test (bist) device and method for fault detection: A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by... Agent: Walker & Sako, LLP

20070271483 - Method and system for dynamically invoking and/or checking conditions of a computer test program: A method and system for dynamically invoking and/or checking conditions of a computer test program. Test cases that verify class/component functionality are automatically created from the DbC contracts. When the classes/components that contain DbC contracts are added to the system, the invention automatically verifies whether the system uses them correctly.... Agent: Christie, Parker & Hale, LLP

20070271484 - Method, system and network entity for detecting a connection fault: A method, a system, and a network entity enable a detection of a connection fault and perform the switch-over in less than 50 ms. CV packets are being sent, for example, 1/10 ms (1 CV packet per 10 ms) or 1/15 ms (1 CV packet per 15 ms). The interval... Agent: Young & Thompson

20070271485 - Method and device for error detection for a cache memory and corresponding cache memory: A method for error detection in a cache memory for storing data, the access to the data stored in the cache memory taking place by addresses assigned to them, wherein for the addresses assigned to the stored data, at least one first test signature made up of at least one... Agent: Kenyon & Kenyon LLP

20070271486 - Method and system to detect software faults: The present invention is directed to a system and method for actively auditing a software system to determine the status. The software system includes a plurality of processes executed in an active processor domain. An active message is generated for processing in the active processor domain. Each process receiving the... Agent: Ropes & Gray LLP Patent Docketing 39/41

20070271487 - Method of detecting scratch defect in circumferential direction and magnetic disk certifier: In the present invention, an inspection area for sampled defect data is set which has a predetermined width in the radial direction of a magnetic disk and a length round the circle of the magnetic disk in the circumferential direction thereof or a predetermined length in the circumferential direction thereof,... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070271488 - Semiconductor integrated circuit and test method therefor: A first path for directly inputting a control signal from the outside to a data signal processor and a second path for inputting a control signal generated by a bus interface to the data signal processor can be selectively switched by a switching portion. At the test time of a... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070271489 - Apparatus and method for verifying custom ic: An apparatus for verifying a custom IC including a test pattern generating unit for generating a test pattern for verifying a function of the custom IC. The test pattern is output to a master IC and a test IC. The apparatus further includes a comparing unit connected to receive operation... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070271490 - Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol: Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking... Agent: Ibm (rps-blf) C/o Biggers & Ohanian, LLP

20070271491 - Apparatus for descrambling a data retrieved from an optical storage medium, and method therefor: An apparatus for descrambling a data retrieved from an optical storage medium comprises a decoder, a memory and a descramble engine. The decoder decodes the data and generates address information corresponding to an address on the optical storage medium, wherein the address responding to a part of the data having... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20070271493 - Unequal error protection method and apparatus using the same: An unequal-error-protection method is disclosed. The method includes performing error-correction coding in parallel; and performing symbol mapping by applying one of a plurality of gains to each of the plurality of error-correction-coded bit streams.... Agent: Sughrue Mion, PLLC

20070271492 - Information recording medium, data sorting device and data reproduction device: The present invention provides an information recording medium in which an access unit including basic data and extension data is recorded, so as to allow a decoder that decodes only basic data to process the access unit which includes the basic data and the extension data for the next generation.... Agent: Wenderoth, Lind & Ponack L.L.P.

20070271494 - Error correction coding for multiple-sector pages in flash memory devices: A flash memory system, including a flash memory device and a controller, and having improved efficiency error correction coding (ECC), is disclosed. Each page in the flash memory device has the capacity to store multiple sectors' worth of data. However, partial page programming (i.e., followed by a later write to... Agent: Anderson, Levine & Lintel L.L.P.

20070271495 - System to detect and identify errors in control information, read data and/or write data: An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored... Agent: Deniro/rambus

20070271496 - 3-stripes gilbert ldpc codes: A method and apparatus are provided for a coding process of a communication signal. A 3-stripes parity-check matrix is generated from a parity-check matrix of a Gilbert low density parity-check code, where the parity-check matrix of the Gilbert low density parity-check code has a first stripe containing identity matrices and... Agent: Schwegman, Lundberg & Woessner, P.A.

20070266271 - Error response by a data processing system and peripheral device: In a computer system a peripheral device executes commands that are issued by a main processor. The peripheral device executes the command and detects whether an error occurs during execution of the command. If so, the peripheral device transfers an error response program from the peripheral device (104) to the... Agent: Philips Intellectual Property & Standards

20070266272 - Graphically extensible, hardware independent method to inspect and modify state of test equipment: A hardware independent and graphically extensible tester state browsing technique for observing and modifying operating state of test equipment includes accessing a descriptor file describing an architecture of the test equipment, invoking a set of plugins associated with one or more subsystems of the test equipment, and displaying a map... Agent: Verigy

20070266273 - Operation error detection device, equipment including the device, operation error detection method and equipment evaluation method: An input section (101) receives a manipulation input of a user (50). A biological signal detection section (102) measures an event-related potential of electroencephalogram of the user (50). An operation error judgment section (103) judges using the event-related potential of the electroencephalogram of the user (50) at around 300 ms... Agent: Gregory A. Stobbs

20070266274 - Interleaver and de-interleaver: An interleaver employs a generalized method of generating a mapping. The mapping is generated for interleaving bits of a data block and associated error detection/correction information. The data block is of length N, and the length of the error detection/correction information is P. An (N+P)×(N+P) square matrix is formed and... Agent: Mendelsohn & Associates, P.C.

20070266275 - Clock recovery system with triggered phase error measurement: A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock recovery system receives an input signal and recovers a clock signal from the input signal. The measurement module is coupled to... Agent: Agilent Technologies Inc.

20070266276 - Memory block testing: A memory device is tested by programming a plurality of pages of a memory block of the memory device, determining a programming time for each page, determining a total programming time for the memory block, passing the memory block if the total programming time for the memory block is less... Agent: Attn: Tod A. Myrum Leffert Jay & Polglaze, P.A.

20070266277 - Memory diagnostic method: A storage device can reduce time for diagnosis and allows the diagnosis to be conducted on the entire area of a memory. The storage device includes a temporary memory that temporarily stores for a storage medium, data written to and/or read from a host system by the storage medium; a... Agent: Greer, Burns & Crain

20070266278 - Method for at-speed testing of memory interface using scan: A method and a circuit of testing of a memory interface associated with an embedded memory in a semiconductor circuit involves writing to two memory locations in succession; reading the two memory locations in succession in the same order in which the two memory locations were written; capturing output data... Agent: Ridout & Maybee LLP

20070266279 - Semiconductor memory device to which test data is written: A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070266281 - Integrated circuit chip packaging: An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.... Agent: Mcginn Intellectual Property Law Group, PLLC

20070266280 - Method and apparatus to test the power-on-reset trip point of an integrated circuit: Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of... Agent: Sierra Patent Group, Ltd.

20070266283 - Method and apparatus for testing an integrated circuit: Disclosed is an apparatus and method for testing an IC having a plurality of scan chains. A test input is transmitted over a tester channel to at least one scan chain during a time interval. Specifically, a memory element stores a first test input transmitted during a first time interval... Agent: Nec Laboratories America, Inc.

20070266282 - Fault-tolerant architecture of flip-flops for transient pulses and signal delays: A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20070266284 - System and method for testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device: A system and method for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device. With the system and method, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070266285 - Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode: The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock... Agent: Mark P. Kahler

20070266286 - Test semiconductor device in full frequency with half frequency tester: An integrated circuit includes a double frequency clock generator and a double input generator to test semiconductor devices at full frequency using a half frequency tester. A clock generator circuit and a test data generator circuit provides differential clock signals and test data signals at a normal rate (1× mode)... Agent: Jonathan O. Owens Haverstock & Owens LLP

20070266288 - Re-configurable architecture for automated test equipment: An adaptive test system includes one or more reconfigurable test boards, with each test board including at least one re-configurable test processor. The re-configurable test processors can transmit communicate with one another using an inter-processor communications controller associated with each re-configurable test processor. The communications include configuration information, control information,... Agent: Verigy

20070266287 - Spatial frequency response measurement method: A spatial frequency response (SFE) measurement method applied for measuring an SFR of a specific area of an image module is disclosed. The method includes: utilizing the image module to obtain an image of a test pattern, wherein the test pattern includes a plurality of test areas, each test area... Agent: Birch Stewart Kolasch & Birch

20070266290 - Test apparatus, test method, and program: There is provided a test apparatus that tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the... Agent: Osha Liang L.L.P.

20070266289 - Testing mobile wireless devices during device production: A system and method of testing a wireless communication device during device production comprises designating as a data log buffer when the device is being produced, at least part of random access memory (RAM) of the device that is allocated for virtual machine and/or application usage when the device is... Agent: Gowling Lafleur Henderson LLP

20070266291 - Semiconductor memory device: A semiconductor memory device including an error detection and correction system, wherein the error detection and correction system has a first operation mode for correcting one number-bit (for example 2) errors and a second operation mode for correcting another number-bit (for example 1) error(s), which are exchangeable to be set... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20070266292 - Method and apparatus for reduced data block transmission in an automatic repeat request system: A wireless transceiver apparatus (201, 203) and a method of operation in an Automatic Repeat Request (ARQ) mode is disclosed. On the transmitter side a packet of data (113) is fragmented into a series of sequential data blocks and each data block is assigned a block sequence number (601). At... Agent: Motorola Inc

20070266293 - Apparatus and method for high speed data transceiving, and apparatus and method for error-correction processing for the same: An apparatus and a method for high-speed data transceiving, and an apparatus and a method for error-correction processing for the same are provided. The high speed data transmitting apparatus includes an error-correction coding unit which performs error-correction coding of input data in parallel, and a radio-transmitting unit which processes the... Agent: Sughrue Mion, PLLC

20070266294 - Forward error correction decoders: Elements of a coding table which are error-free are found at S2. At S3, corresponding elements in an erasure information table are completed, indicating that the elements in the coding array are correct. A counter is initialised at Nmax, which is the maximum number of errors that can be corrected,... Agent: Harrington & Smith, PC

20070266298 - Apparatus for improving data access reliability of flash memory: An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a comparator, an arbitrator, and a decoder. The instruction register and... Agent: Rosenberg, Klein & Lee

20070266297 - Controller and storage device having the same: A controller for controlling an access of a non-volatile memory having an error-correcting code area and a data area is provided. The controller includes an error-correcting module and a first inverting circuit electrically connected to the error-correcting module for inverting data and error-correcting codes corresponding to the data. When the... Agent: Jianq Chyun Intellectual Property Office

20070266295 - Convolutional coding methods for nonvolatile memory: Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be... Agent: Winston & Strawn, LLP

20070266296 - Nonvolatile memory with convolutional coding: Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be... Agent: Winston & Strawn, LLP

20070266299 - Decoding apparatus and method therefor: A decoding apparatus adapted for an optical access system comprises an interface, a detection element, and an error correction element. The interface receives a data from an optical storage medium. The detection element executes an error detection on the data received from the interface before the data is buffered to... Agent: Ladas & Parry

20070266300 - Error correction device, encoder, decoder, method, and information storage device: An encoder divides the data in which sector data is adjacently connected to a first RS parity generated in Reed Solomon encoding into blocks to and subjects each of the blocks to cyclic Hamming encoding so as to generate Hamming parities. Subsequently, the data in which the Hamming parities are... Agent: Greer, Burns & Crain

20070266301 - Techniques for generating cyclic redundancy check (crc) values: Techniques for generating cyclic redundancy check (CRC) values are provided. Bit messages that are to be transmitted to recipients are aligned to desired byte boundaries for purposes of generating CRC values, which are to be sent with the bit messages. The CRC values are rewound or adjusted back to values... Agent: Schwegman, Lundberg & Woessner, P.A.

20070266302 - Method and apparatus for dedicated hardware and software split implementation of rate matching and de-matching: In the method of rate-matching, software is used to calculate at least one rate-matching parameter for data, and dedicated hardware is used to perform at least one of a puncturing and repetition process on data based on the calculated rate-matching parameter. In rate de-matching, software is again used to calculate... Agent: Harness, Dickey & Pierce, P.L.C

20070266303 - Viterbi decoding apparatus and techniques: Viterbi decoding techniques that include multi-stage Viterbi decoding of encoded signals. Such techniques include radix-4 two stage decoding. The encoded signals may include soft decision signals. A Viterbi decoder may include a branch metric generator, a trellis interconnect, an add-compare element, a path metric memory, and a traceback element. The... Agent: Qualcomm Incorporated

20070260908 - Method and system for transaction recovery time estimation: To generate a recovery time estimate in a transaction environment, a system includes a recovery manager, a recovery file containing recovery data, a store of historical restart data, and a recovery time estimation component. The recovery manager includes a component which is operable to measure the volume of active data... Agent: Ibm Corporation

20070260912 - Method of achieving high reliability of network boot computer system: In a network computer system, recovery may be impossible from a fault when the fault occurs in a network switch in a network or a device such as an external disk device. Provided is a computer system that includes a plurality of servers, a plurality of networks, a plurality of... Agent: Townsend And Townsend And Crew, LLP

20070260918 - Storage apparatus and storage apparatus power supply failure management method: A storage apparatus according to the present invention can store information related to a power supply abnormality after shutting down the principal functions of a data processing board when a power supply abnormality occurs in a data processing board. A power supply controller of a data processing board mounted in... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070260923 - Program dynamically burnt system and method: A program dynamically burnt method is provided. The method includes the following steps: dividing a system program into a first part system program and a second part system program; linking a diagnostic program, the second system program and the first system program orderly to form an integration program; burning the... Agent: North America Intellectual Property Corporation

20070260925 - Semiconductor memory device: A semiconductor device includes a plurality of first pads; a plurality of ports for performing a serial data communication with external devices through the first pads; a plurality of banks for performing a parallel data communication with the plurality of ports; a plurality of global data buses for supporting the... Agent: Blakely Sokoloff Taylor & Zafman

20070260941 - Information processing apparatus and information processing method: An information processing apparatus detects an error which occurred in a system and stores a system status that the error occurred in association with error information indicating the error. The information processing apparatus outputs guidance information according to a system status, a system status stored in the storage unit, and... Agent: Canon U.s.a. Inc. Intellectual Property Division

20070260911 - Communication network management system for automatic repair of failures: The invention relates to a management system (NMS) for a communication network (N) comprising a diagnostic module (MD) capable of determining a diagnosis (D) based on information (A) provided by network elements (N1, N2, N3, N4), this diagnosis identifying a failure within the network. The management system also comprises a... Agent: Sughrue Mion, PLLC

20070260909 - Computer hardware fault administration: Methods, apparatus, and computer program products are disclosed for computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network... Agent: Ibm (roc-blf)

20070260913 - Fail over method through disk take over and computer system having failover function: When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the servers boot an operation system from the external disk device, task processing is taken over from the primary server to a... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070260910 - Method and apparatus for propagating physical device link status to virtual devices: A method, apparatus, and computer instructions are provided for propagating a physical device's link status to one or more virtual devices associated with the physical device. Link status information about the physical device indicating a failure in the physical device is identified using partition management firmware. The link status information... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070260914 - Personal computer bus protocol with error correction mode: An integrated circuit device has a function block to perform a core function, a bus controller through which the function block is to communicate with another device over an attachment bus, and an error correction module (ECM). The ECM adapts a bus protocol to a failure in the bus, so... Agent: Blakely Sokoloff Taylor & Zafman

20070260915 - Identifying one or more storage devices causing a failure condition during discovery of storage devices: A failure condition caused during discovery of storage devices on a storage network having at least one primary bus interconnecting the storage devices is detected. In response to detecting the failure condition, interaction is performed with the storage devices over a secondary bus separate from the primary bus to identify... Agent: Hewlett Packard Company

20070260916 - System and method for failure recovery in a shared storage system: A system and method is disclosed for failure recovery and communications in a shared storage system. The shared storage system includes at least two host nodes, each of which includes two ports. Each of the ports of each of the nodes is coupled to input ports of a storage enclosure.... Agent: Roger Fulghum Baker Botts L.L.P.

20070260917 - Driving method of storage apparatus and disk subsystem including such storage apparatus: Provided is a highly reliable storage apparatus for supplying power to a plurality of memory mediums. This storage apparatus has a plurality of hard disks separately disposed in groups of eight; a plurality of power supply units for supplying power to each of the eight hard disks belonging to each... Agent: Stanley P. Fisher Reed Smith LLP

20070260919 - Paging-triggered corrupted file recovery: When a user-mode inpage error occurs after the system has booted up, the inpage error handling method attempts to prevent future crashes by repairing the faulting file. The fault may be a corrupt file or may be a disk I/O problem. The next time the now-repaired file is requested, execution... Agent: Marshall, Gerstein & Borun LLP (microsoft)

20070260920 - Method of restoring communication state of process: An embodiment of a method of restoring a communication state of a process includes creating a new socket for a socket saved as part of a checkpoint of the communication state. The new socket is initialized with an adjusted transmission control protocol state saved as part of the checkpoint. The... Agent: Hewlett Packard Company

20070260921 - Intelligent switch and method for retransmitting a lost packet to decoder(s): An intelligent switch and method are described herein which help to effectively retransmit a lost packet that is associated with a television broadcast stream to one or more set-top box(es) (STBs). In one embodiment, the intelligent switch functions as follows: (a) receives, from one of the STBs, a request for... Agent: Alcatel Lucent Intellectual Property & Standards

20070260922 - Method of protecting data in cache memory of storage system: A method of protecting data in the cache memory of a storage system is used to protect the data stored in the cache memory of a first storage system and a second storage system coupled together and with the battery backed function. When the first storage system and the second... Agent: Birch Stewart Kolasch & Birch

20070260924 - Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof: A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory... Agent: J.c. Patents, Inc.

20070260926 - Static and dynamic learning test generation method: Exemplary embodiments include a static and dynamic test generation and simulation method including: analyzing a logic model; identifying a logic structure in the logic model whose input/output signal can be assigned to a particular logical value and remain fixed during a fault simulation test; and running the fault simulation test... Agent: Cantor Colburn LLP - IBM Rochester Division

20070260927 - Methods, systems and computer program products for providing an internet protocol based device health check: Methods, systems and computer program products provide an IP based device health check. The methods include initiating a health check to be performed at a customer location. The results of the health check are received and stored as an install state. A current state that was created in response to... Agent: Cantor Colburn LLP - Bellsouth

20070260929 - Pluggable debugging interface for graphical notation diagrams: A low-level process, which was mapped from a high-level graphical notation diagram, is debugged using the high-level graphical notation diagram. To debug the low-level process, a debugging interface allows a user to set and track breakpoints and other debug events from the high-level graphical notation diagram. When a breakpoint or... Agent: Hickman Palermo Truong & Becker, LLP And Sun Microsystems, Inc.

20070260930 - Selective alteration of shell utility return code: In a shell utility computer program code configured to cause at least one computer processor comprising one host computer system to connect to a second host computer system, and to cause the second host computer system to execute at least one command provided to one host computer system, the computer... Agent: John H. Holcombe IBM Corporation,IPLaw Dept.

20070260928 - System and method for engineered decoupling in a development environment: A system and method for providing engineered decoupling in a development environment. According to an embodiment of the invention, an infrastructure framework is configured to process one or more service requests from a frontend application, an actual runtime engine is associated with the infrastructure framework and configured to implement functionality... Agent: Kenyon & Kenyon LLP

20070260932 - Event log management system: The present invention is an event log management system and method for monitoring the reliability of test systems. An event log management system includes a data store which stores at least one tester configuration file, a hardware independent event capture function which captures events from at least one monitored tester... Agent: Verigy

20070260931 - Merging multi-line log entries: A system and method for building merged events from log entries received from multiple devices. Multiple log events generally contribute to a single merged event. In the described embodiment, the mapping module receives log entries associated with specific merged events and maps them to fields in the merged event data... Agent: Fenwick & West LLP

20070260933 - Recording analog characteristics of data from a data line in a protocol analyzer: This disclosure relates to systems and methods for recording analog characteristics of data. In one example embodiment, a method for recording and outputting a waveform in a protocol analyzer includes receiving analog data, converting the analog data to digital data that represents variations in a signal characteristic of the analog... Agent: Workman Nydegger

20070260934 - Automated hardware parity and parity error generation technique for high availability integrated circuits: A technique wherein High Availability (HA) hardware is used to automatically validate control and configuration registers, e.g. automatically generate parity, detect parity errors, and report errors within software-written configuration and control registers of ASIC and IC products. Parity control logic and Masking Registers are utilized to facilitate automatic parity generation... Agent: Tucker Ellis & West LLP

20070260938 - Method, code, and apparatus for logging test results: In one embodiment, a method for logging test results, has steps for: A) accessing a stream of test data associated with a tester performing tests on a number of devices under test; B) selecting items of the test data to be logged to a data store, the selecting being performed... Agent: Verigy

20070260935 - Methods, systems, and computer program products for compensating for disruption caused by trace enablement: A method for compensating for disruption caused by trace enablement is provided. The method includes receiving a selected target to run a program, receiving a selected program that has been identified as having a problem, and receiving a selected trace type. The method also includes enabling a trace compensator for... Agent: Cantor Colburn LLP - IBM Rochester Division

20070260936 - Systems and methods for assigning identifiers to test results for devices within a group: There are disclosed systems and methods for coordinating test results of devices within a group. In an embodiment, the system may include code to assign identifiers to test results of a first test execution, receive a user-specified beginning point, and assign identifiers to test results of a second test execution.... Agent: Verigy

20070260937 - Systems and methods for selectively logging test data: There are disclosed systems and methods for selectively logging test data. In an embodiment, a system includes code to monitor test data generated by a plurality of devices and to generate statistics related to the test data; and code to in response to the statistics related to the test data,... Agent: Verigy

20070260940 - Automatic protection switching and error signal processing coordination apparatus and methods: Automatic Protection Switching (APS) and error signal processing coordination apparatus and methods are disclosed. If a communication module that enables communication signals and error signals to be exchanged with a remote communication module is configured in an APS protection group, error signal processing by the communication module is restricted. This... Agent: Eckert Seamans Cherin & Mellott, LLC.

20070260939 - Error filtering in fault tolerant computing systems: A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor, a fault detection processor responsive to the main processor, the fault detection processor further comprising a voter logic circuit, three or more logic devices responsive to the fault detection processor,... Agent: Honeywell International Inc.

20070260942 - Transactional memory in out-of-order processors: Methods and apparatus to provide transactional memory execution in out-of-order processors are described. In one embodiment, a stored value corresponds to the number of transactional memory access requests that are uncommitted. The stored value may be used to provide nested recovery in case of an error, fault, etc. in accordance... Agent: Caven & Aghevli C/o Intellevate

20070260943 - Proactive server-side error subsystem for interactive objects: A software error subsystem is provided that can log, report, and may optionally correct defective interactive objects in a virtual game environment. The subsystem may form part of a larger and more general logging and error catching system. By automatically correcting certain defects, recourse to redevelopment efforts can be postponed... Agent: Mayer & Williams PC

20070260944 - Decoding ldpc (low density parity check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph: Decoding LDPC (Low Density Parity Check) code and graphs using multiplication (or addition in log-domain) on both sides of bipartite graph. A means for decoding LDPC coded signals is presented whereby edge messages may be updated using only multiplication (or log domain addition). By appropriate modification of the various calculations... Agent: Garlick Harrison & Markison

20070260945 - Method for accuracy improvement allowing chip-by-chip measurement correction: A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within... Agent: Howison & Arnott, L.l.p

20070260947 - Measuring apparatus, measuring method, testing apparatus, testing method, and electronic device: There is provided a measuring apparatus for measuring a signal-under-test, having a comparator for sequentially comparing voltage values of the signal-under-test with a threshold voltage value fed thereto at timing of strobe signals sequentially fed thereto, a strobe timing generator for sequentially generating the strobe signals placed almost at equal... Agent: Smith, Gambrell & Russell

20070260946 - Nonvolatile memory device comprising a programming and deletion checking option: A method and circuitry for checking the programming (P) and deletion (L) operations of memory cells (5) in a nonvolatile memory device (1). Parallel to the programming (P) or deletion (L) operations of the actual memory cells (5) the respective programming or deletion process is carried out on at least... Agent: O'shea, Getz & Kosakowski, P.C.

20070260948 - Driver ic and inspection method for driver ic and output device: A driver IC including: a plurality of output pads; and a plurality of signal switch circuits, each of the signal circuits being provided on one of signal paths respectively connected to the output pads, wherein each of the signal switch circuits switches between a first state (or a use state)... Agent: Harness, Dickey & Pierce, P.L.C

20070260952 - Dft techniques to reduce test time and power for socs: A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores... Agent: Wade James Brady Iii Texas Instruments Incorporated

20070260950 - Method and apparatus for testing a data processing system: A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if... Agent: Freescale Semiconductor, Inc. Law Department

20070260949 - Trading propensity-based clustering of circuit elements in a circuit design: An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070260951 - Uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit: A method and/or system of uncompromised standard input set-up time with improved enable input set-up time characteristics in a storage circuit are disclosed. In one embodiment, a storage circuit includes a master latch coupled to a slave latch where each undergoes data transmission at an opposite transition edge of a... Agent: Texas Instruments Incorporated

20070260953 - Scan test: An electronic circuit includes a group of devices which facilitate scan testing of at least one part of the electronic circuit. Those devices include a scan test device. The circuit further includes a state machine which operates to transfer data from an input pin of the circuit which is dedicated... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070260954 - Integrated circuit with low-power built-in self-test logic: An integrated circuit with low-power built-in self-test logic (“IC-LPBIST”) is disclosed. The IC-LPBIST may include combinational logic and a loading circuit enabled to load a shift test pattern of data into the loading circuit without powering the combinational logic of the IC-LPBIST, wherein the shift test pattern of data is... Agent: Mcandrews Held & Malloy, Ltd

20070260955 - Test auxiliary device in a memory module: Methods and apparatus for applying a test pattern to cells in a memory module. A test auxiliary device in a memory module contains a test pattern selection device for selecting a test pattern from at least two elementary M-bit test patterns. The test pattern is applied to a group of... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070260956 - Method and system for supporting multiple hybrid automatic repeat request processes per transmission time interval: A method and system for supporting multiple hybrid automatic repeat request (H-ARQ) processes per transmission time interval (TTI) are disclosed. A transmitter and a receiver include a plurality of H-ARQ processes to transmit and receive multiple transport blocks (TBs) simultaneously per TTI. The transmitter generates a plurality of TBs and... Agent: Volpe And Koenig, P.C. Dept. Icc

20070260957 - Encoded transmission: Significant improvement in Raptor codes and punctured LDPC codes are obtainable by use of the invention. In both a transmission scheme for Raptor-encoded or LDPC-encoded information, a dynamic adjustment approach is employed. A fraction of a codeword or information frame is transmitted. A feedback signal is sent from the receiver... Agent: Hitt Gaines, PC Alcatel-lucent

20070260960 - Error correction system and related method thereof: Disclosed is an error correction system, which comprises: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly PI syndrome generator, coupled to the demodulator, for generating a PI syndrome according to the ECC block from the demodulator; a data buffer for storing... Agent: North America Intellectual Property Corporation

20070260961 - Error correction system and related method thereof: Disclosed is an error correction system, comprising: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly PI ECC decoder, coupled to the demodulator, for performing a PI ECC operation on the ECC block; a data buffer, for storing the ECC block; a... Agent: North America Intellectual Property Corporation

20070260959 - Log-likelyhood ratio (llr) computation using piecewise linear approximation of llr functions: Techniques for efficiently and accurately computing log-likelihood ratio (LLRs) for code bits are described. A set of code bits may be mapped to a modulation symbol in a signal constellation. Different code bits in the set may be associated with different LLR functions. A receiver obtains received symbols for a... Agent: Qualcomm Incorporated

20070260958 - Wireless communication method and system for bit interleaved coded modulation and iterative decoding: A wireless communication method and system for performing bit-interleaved coded modulation and iterative decoding. The system includes a transmitter and a receiver. The transmitter encodes incoming bits to generate coded bits, punctures the coded bits in accordance with a predetermined puncturing pattern to generate surviving channel bits and stolen bits... Agent: Volpe And Koenig, P.C. Dept. Icc

20070260962 - Methods and apparatus for a memory device with self-healing reference bits: A memory device, such an MRAM device, includes self-healing reference bits (104) associated with a set of array bits (102). The memory performs an error detection step (e.g., using an error-correction coding (ECC) algorithm, to detect the presence of a set of errors within the data bits. One of the... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20070260963 - Error correction system and related method thereof: Disclosed is an error correction system, comprising: a demodulator for receiving and demodulating raw data to generate an ECC block; an on the fly EDC check device for performing an EDC operation according to data of the ECC block from the demodulator to generate an EDC result; a data buffer... Agent: North America Intellectual Property Corporation

20070260964 - Semiconductor memory: In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects... Agent: Steptoe & Johnson LLP

20070260965 - Error detection in physical interfaces for point-to-point communications between integrated circuits: An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode... Agent: Silicon / Blakely Blakely Sokoloff Taylor & Zafman

20070260966 - Error correction method and apparatus for low density parity check: An apparatus for and a method of correcting an error using a low density parity check (LDPC) matrix. A resultant matrix is generated by performing XOR and modular 2 operations with respect to the LDPC matrix and a code word vector and a number of 1 bits in the resultant... Agent: Stein, Mcewen & Bui, LLP

20070260967 - Safe information transmission via non-safety approved equipment: A method of detecting communications errors by coding messages as pictures is provided. Also provided is a communications method useable to safely communicate a message or a signal from a first safety approved entity (210) to a second safety approved entity (230) via a third, non-safety approved entity (220), comprising... Agent: Albihns Stockholm Ab

20070255980 - Method and apparatus for detecting false operation of computer: A program to be executed by a computer is divided into a plurality of code blocks, and, a unique code block ID is allotted to each code block. At the moment when the execution of the program is started, the code block ID corresponding to the execution start address is... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070255977 - System and method for application monitoring and automatic disaster recovery for high-availability: Stable and automated recovery of an application executing on a primary computer system by transitioning to secondary computer system is provided. Intelligent agents installed on a primary client server allow the primary environment to be replicated on a host, secondary environment. This creates continuous availability of applications executing on the... Agent: Dubois, Bryant, Campbell & Schwartz, LLP

20070255978 - Retroactive verbose logging: Retroactive verbose error logging may be provided. Loggable event entries associated with software installation during installation may be saved. Each of the loggable event entries may have a first level or a second level. In addition, the loggable event entries associated with the first level and the second level may... Agent: Merchant & Gould (microsoft)

20070255979 - Event trace conditional logging: Use of configuration information to specify particular conditions under which trace events are to be logged. When accessing trace events generated by various modules, configuration data is referred to specifying condition(s) under which the trace events should be logged. If the log condition(s) are satisfied, the trace events are logged.... Agent: Workman Nydegger/microsoft

20070255981 - Redundancy-function-equipped semiconductor memory device made from ecc memory: A semiconductor memory device includes a memory configured to input/output first data and second data in parallel, the first data being all or part of a predetermined number of bits, and the second data being comprised of a number of bits necessary to correct error of the predetermined number of... Agent: Arent Fox PLLC

20070255982 - Memory device testing system and method having real time redundancy repair analysis: A memory device test system includes a signal generator providing memory command, address and write data signal to write data in a memory device and then read the data from the memory device. Each item of read data is compared to the corresponding item of write data, and fail data... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070255985 - Method and apparatus for disabling and swapping cores in a multi-core microprocessor: In some embodiments, a method and apparatus for disabling and swapping cores in a multi-core microprocessor are presented. In this regard, a test agent is introduced to disable a core, to configure a mode, and to configure a site. Other embodiments are also disclosed and claimed.... Agent: Intel Corporation C/o Intellevate, LLC

20070255983 - Semiconductor integrated circuit and electronic device: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20070255984 - Test mode for pin-limited devices: A pin-limited device includes a pattern-recognition circuit that detects a predetermined signal pattern transmitted on a supply pin of the device. The predetermined signal pattern is generated within the acceptable operating voltage range of the IC device (e.g., between the minimum and maximum acceptable system voltage levels utilized to control... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070255986 - Wrapper testing circuits and method thereof for system-on-a-chip: A wrapper testing circuit of system-on-a-chip for electrical tests of at least a core circuit of an integrated circuit and a wrapper testing method thereof are provided. A controller outputs control signals and test signals and receives result signals executed by the core circuit. The wrapper testing circuit comprises a... Agent: Birch Stewart Kolasch & Birch

20070255988 - Computer-aided design (cad) multiple-capture dft system for detecting or locating crossing clock-domain faults: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method... Agent: Jim Zegeer, Esq.

20070255987 - Control signal synchronization of a scannable storage circuit: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a digital system includes any number of storage circuits interconnected together with logic circuitry to form at least a portion of a functional circuit. Each of the storage circuits may include... Agent: Texas Instruments Incorporated

20070255989 - Systems, methods and apparatus for synthesizing state events for a test data stream: In one embodiment, a method of has the steps of A) accessing a stream of test data comprising 1) a number of state events and 2) a number of data events interspersed with the ones of the state events; B) upon accessing one of the data events, determining if the... Agent: Verigy

20070255990 - Test access port switch: A Test Access Port (TAP) switch provides a centralized serial test interface between an electronic system and a resource external to the electronic system. The electronic system includes the TAP switch and a plurality of electronic circuit components, each electronic circuit component having a TAP coupled to the TAP switch.... Agent: Qualcomm Incorporated

20070255991 - Monitoring a thermal processing system: A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table to detect, diagnose and/or predict fault conditions and/or degraded performance. The method includes positioning a plurality of wafers in a processing chamber in the thermal processing system, performing a self test process, determining... Agent: Wood, Herron & Evans, LLP (tokyo Electron)

20070255992 - Semiconductor integrated circuit system, semiconductor integrated circuit, operating system, and control method for semiconductor integrated circuit: A semiconductor integrated circuit system has a control target circuit executing a program, a system information monitor unit for outputting system information indicating a state of the control target circuit, a circuit characteristic monitor unit for determining a circuit characteristic of the control target circuit and outputting the circuit characteristic... Agent: Mcdermott Will & Emery LLP

20070255993 - Automatic retransmission request control system and retransmission method in memo-ofdm system: An automatic retransmission request control system in OFDM-MIMO communication system. In this system, an ACK/NACK output part (320) of a receiver transmits, to a transmitter, a feedback information of positive or negative response based on the result of a cyclic redundancy check. An error data stream decision part (310) of... Agent: Stevens, Davis, Miller & Mosher, LLP

20070255994 - Decoding method: A decoding method for decoding information content in at least one data packet, which is transmitted from a sender to a receiver via a data link. The information is represented by a bit sequence, which is transformed into a transmittable redundancy version. The information is initially transmitted for a first... Agent: Lerner Greenberg Stemer LLP

20070255995 - Information recording/reproducing apparatus, and information recording medium: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively.... Agent: Drinker Biddle & Reath (dc)

20070255996 - Information recording/reproducing apparatus, and information recording medium: In an information recording, a first data processor divides input data into a plurality of frames so as to arrange the plurality of frames for each unit block. The unit block is a unit of error-correction with respect to the input data and the frames include first identification information, respectively.... Agent: Drinker Biddle & Reath (dc)

20070255997 - Multi-thread parallel segment scan simulation of chip element performance: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware... Agent: International Business Machines Corporation

20070255998 - Memory command unit throttle and error recovery: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the... Agent: Squire, Sanders & Dempsey L.L.P.

20070255999 - Memory arrangement and method for error correction: A method of error correction for a memory arrangement includes dividing information to be written to the memory arrangement into n data blocks of m bits each, writing the n data blocks to at least one memory module of the memory arrangement, determining a redundant data block based on the... Agent: Dicke, Billig & Czaja

20070256000 - Redundancy protection for data recorded across multiple layers of recording media: Improved reliability for multi-layer media is providing by the present invention. A data stream U is received for recording to a multi-layer rotating storage medium, the data stream U comprising a sequence of data bits. Each data bit U(J) is encoded into X representation bits. A first representation bit B(1,J)... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070256001 - Fec (forward error correction) decoder with dynamic parameters: FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly... Agent: Garlick Harrison & Markison

20070256002 - Error correction and error detection method for reading of stored information data and a storage control unit for the same: An error correction and/or error detection method reads of stored information data from a storage device; wherein in addition to the information data, code data is read from the storage device. Syndrome data is formed from the information data and the code data in order to determine errors and/or error... Agent: Maginot, Moore & Beck Chase Tower