Error detection/correction and fault detection/recovery inventions 10/07

20070250738 - Disaster recovery within secure environments: Systems and processes include a disaster recovery system for a production site. The disaster recovery site may include replications of at least a portion of information and/or applications from the production site. Requests for the production site may be redirected to the disaster recovery site according, as appropriate. The disaster... Agent: Fish & Richardson P.C.

20070250739 - Accelerating software rejuvenation by communicating rejuvenation events: A computer readable medium is provided embodying instructions executable by a processor to perform a method for triggering a software rejuvenation system or method, the method includes receiving a request for resources at a node, determining an estimated response time to the request for resources, determining that the estimated response... Agent: Siemens Corporation Intellectual Property Department

20070250737 - Method and apparatus for aligned data storage addresses in a raid system: A method includes providing a redundant array of inexpensive disks (RAID) array having at least a stripe sector unit (SSU) of data written to it. A request is received to perform a write operation to the RAID array beginning at a starting data storage address (DSA) that is not aligned... Agent: Duane Morris LLPIPDepartment (agere)

20070250740 - System and method for conducting bist operations: A built in self test (BIST) system for a storage controller comprises a processor, a test access port (TAP) controller that communicates with a TAP interface that is external to the storage controller, and a BIST controller that selectively performs a BIST based on information received from each of the... Agent: Harness, Dickey & Pierce P.L.C

20070250741 - Selective bit error detection at a bus device: In one aspect, a data transmission rate of a message signal representing a bus message at a bus and a propagation delay between an occurrence of the message signal at a transmission output to the bus and an occurrence of the message signal at a receive input from the bus... Agent: Larson Newman Abel Polansky & White, LLP

20070250742 - Systems and methods for interleaving and deinterleaving data in an ofdma-based communication system: In an exemplary embodiment, a base station includes an antenna for transmitting signals on a downlink to a plurality of user devices. The base station also includes a processor, and memory in electronic communication with the processor. Interleaving instructions are stored in the memory. The interleaving instructions are executable by... Agent: Madson & Austin

20070250743 - Test apparatus, adjustment apparatus, adjustment method and adjustment program: A test apparatus that test a device under test includes a plurality of signal input/output units each of which has a signal output section and a signal input section that: firstly, adjusts each of the signal input/output units such that the phase difference between a time at which the signal... Agent: Osha Liang L.L.P.

20070250744 - Method and apparatus for testing the connectivity of a flash memory chip: In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan... Agent: Dla Piper US LLP

20070250745 - Method and system for testing a memory device: A system and method for testing a memory device is disclosed. One embodiment includes a plurality of memory cells. Each of the memory cells can be controlled by an address. A test memory for storing test results is provided. An address comparing unit is configured to determine whether the address... Agent: Dicke, Billig & Czaja

20070250746 - Testing cmos ternary cam with redundancy: A method for testing an CMOS ternary content addressable memory (TCAM) device includes a match line test to identify stuck match lines, a pull down test to identify weak pull downs (from the match line to ground), and a row-by-row match test. During the row-by-row match test a failed cell... Agent: Dickstein Shapiro LLP

20070250747 - Semiconductor integrated circuit: A semiconductor integrated circuit, includes a first external terminal which inputs a test signal, a second external terminal which external inputs a clock signal, a self-test circuit which conducts a self-test based on the clock signal which is input through the second external terminal, a third external terminal which outputs,... Agent: Mcdermott Will & Emery LLP

20070250748 - Logic circuit protected against transitory perturbations: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to... Agent: Basinski & Associates

20070250749 - Test generation methods for reducing power dissipation and supply currents: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state... Agent: Klarquist Sparkman, LLP

20070250750 - Error detection apparatus and method: A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and... Agent: Advanced Micro Devices, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20070250751 - Automatic repeat request (arq) scheme: During operation each ACK/NAK feedback (200) comprises two fields (201-204). Each field corresponds to the status of previously-received data (e.g., slot, frame, TTI, . . . , etc.). In a first embodiment, field 1 corresponds to the current received data status, while field 2 corresponds to the previous received data... Agent: Motorola, Inc.

20070250752 - Transmitter for transmitting information data and receiver for receiving information data: A transmitter for transmitting information data present in a plurality of data sets comprises an assigner for assigning offset information to one or more data sets of the plurality of data sets, the offset information indicating where the data set is to be written in a memory of a receiver.... Agent: Glenn Patent Group

20070250753 - Method of decoding code blocks and system for concatenating code blocks: In a multiple access environment, to improve decoding efficiency for small code blocks by a constituent decoder, multiple code blocks may be concatenated to form a single larger code block. Example embodiments of the present invention concatenate code blocks for turbo codes I and II. Example embodiments of the present... Agent: Harness, Dickey & Pierce, P.L.C

20070250754 - System and method of correcting video data errors: The present disclosure is directed to a system and method of correcting video data errors. In a particular embodiment, the method includes receiving a plurality of Internet Protocol (IP) video data packets at a generator of a video acquisition system. The method also includes calculating a first error correction code... Agent: Toler Schaffer, LLP

20070250757 - Method and data storage devices for a raid system: A method of controlling a RAID system including a plurality of disk devices is provided. The method allows for reading data recorded onto an area adjacent to an area where a write error occurs when the write error is detected while data is written into the disk device. When an... Agent: Staas & Halsey LLP

20070250755 - Dormant error checker: In accordance with some embodiments, an error checking scheme to check for an error in a memory unit during a dormant state is provided herein.... Agent: Intel Corporation C/o Intellevate, LLC

20070250756 - High reliability memory module with a fault tolerant address and command bus: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a... Agent: Francis J. Thornton

20070250758 - Recording method for recording data on a recording medium: If a large minimum data unit for recorded data is used to record a small data amount of management information, the recording time is long, and furthermore when a WO (write once) is used as the recording medium, the number of recording operations which can be performed is restricted. To... Agent: Mcdermott Will & Emery LLP

20070250759 - Margin decoding communications system: A margin decoding communications system includes a circuit receiving a message encoded by an iterative code and processing the message into scores. A normalization process module receives the scores and iteratively approximates log-map normalization factors of the scores to generate approximation normalization factors. An element receives the message and the... Agent: Harness, Dickey & Pierce, P.L.C

20070250760 - Extended convolutional codes: A system and method for providing increased forward error correction by providing extended convolutional coding for packets/frames or superframes used in wireless transmission. A wireless system having an extended convolutional encoder/decoder therein, includes a wireless network, a server having an extended convolutional encoding/decoding module, one or more clients, at least... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070245167 - Managing failover of j2ee compliant middleware in a high availability system: A method, system, and program for managing failover of J2EE compliant middleware in a high availability system are provided. A primary node and a secondary node each run the same J2EE compliant middleware stack comprising layers including a load balancer, a web server, a web application server, a message control... Agent: Ibm Corp (ap) C/o Amy Pattillo

20070245168 - Associative memory capable of searching for data while keeping high data reliability: A CAM unit has a memory array for storing storage data, and a RAM unit has a memory array for storing the same storage data and check bits added thereto for determining whether the storage data in its memory array has an error. An error correction circuit uses the check... Agent: Buchanan, Ingersoll & Rooney PC

20070245169 - Location based diagnostics method and apparatus: A method and system for use with an enterprise operation and at least one processor linked to the operation, the method for requesting service from a most optimal enterprise user when at least one interesting condition related to the operation occurs, the method comprising the steps of providing a wireless... Agent: Rockwell Automation, Inc./(qb)

20070245170 - Computer boot operation utilizing targeted boot diagnostics: An apparatus, program product and method utilize targeted boot diagnostics in connection with a boot operation to automate the handling of hardware failures detected during startup or initialization of a computer. In particular, in response to detection of a failure after initiation of and during performance of a boot operation,... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20070245171 - Methods and apparatus to perform distributed memory checking: Methods and apparatus to perform distributed memory checking for distributed applications are disclosed. An example method comprises sending data from a first process to a second process, and sending distributed memory check data to the second process, wherein the distributed memory check data represents an initialization state of the data... Agent: Hanley, Flight & Zimmerman, LLC

20070245172 - Method, apparatus, and computer program product in a performance monitor for sampling all performance events generated by a processor: A method, apparatus, and computer program product are disclosed for sampling all performance event signals generated by a processor. A performance monitor is included in the processor. The performance monitor receives performance event signals from the processor. These performance event signals indicate the current full event state of the processor.... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070245173 - Enclosure-based raid parity assist: In a RAID storage system, a parity value is generated. The storage system includes a RAID adapter, a plurality of disk array processors managing corresponding sets of RAID storage drives, and a connecting fabric. The RAID adapter initiates a parity generation operation, parallel instructions are dispatched for the array processors... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070245174 - Diagnostics for remote computer systems: A system for use in an environment having a remote computer system, a user associated with the remote computer system, and an error detection component for detecting errors associated with the remote computer system comprises a storage component for computer programs that performing diagnostics errors associated with the remote computer... Agent: Ibm Corporation

20070245175 - Method of, apparatus and graphical user interface for automatic diagnostics: The present invention includes a method, apparatus and graphical user interface (GUI) that allows a simple, precise, thorough, automatic and interactive diagnostic system for electronic devices. The present invention fully automates every test item, as a memory device including the diagnostic test items is inserted into the electronic device and... Agent: Haverstock & Owens LLP Attn: Jonathan O. Owens

20070245176 - Ber monitoring circuit: In a BER monitoring circuit, error cycles of input data are detected by a parity check portion and an error cycle detecting portion, a maximum (average/median) value is detected from among the error cycles by an error cycle memory and an error cycle maximum (average/median) value retrieving portion. The value... Agent: Bingham Mccutchen LLP

20070245177 - Method and apparatus for determining the total power margin available for an hfc network: The available power margin in a network is determined by increasing the transmission power levels of selected network elements while transmitting a test signal. The quality of the test signal is measured during the successive increases in power level of the selected network elements by measuring the error rate of... Agent: General Instrument Corporation Dba The Connected Home Solutions Business Of Motorola, Inc.

20070245178 - Parallel processing apparatus dynamically switching over circuit configuration: A parallel processing apparatus dynamically switching over a circuit configuration includes a plurality of computing elements, a network establishing connections between the plural computing elements, a plurality of selectors provided corresponding to the plurality of computing elements within the network and controlling outputs from the computing elements, first local memories... Agent: Staas & Halsey LLP

20070245179 - Manufacturing method of semiconductor device and semiconductor device corresponding to loop back test: The testing device is provided with the first element having one end coupled to an input terminal, and the other end coupled to an output terminal, and attenuating a direct-current component, and the second element having one end coupled to the input terminal, and attenuating an alternating current component. The... Agent: Mcdermott Will & Emery LLP

20070245180 - Circuitry and method for an at-speed scan test: An integrated circuit has a plurality of clock domains and a plurality of memory cells being configurable as operational memory cells or as scan test memory cells for testing the integrated circuit. A pulse generator of the integrated circuit generates pulses for triggering the memory cells when being configured as... Agent: Timothy R. Wyckoff Infineon Technologies Ag - Patent Dept.

20070245181 - Memory system and method of writing into nonvolatile semiconductor memory: A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070245182 - Semiconductor memory device: A semiconductor memory device is disclosed, which includes a memory cell array including a plurality of memory cells, a built-in self-test circuit which writes test pattern data including binary 0 and binary 1 in the memory cells in units of a page to perform a test for the memory cells,... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070245185 - Flip-flop, shift register, and scan test circuit: A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of the first feedback circuit, based on the logic level of a first clock... Agent: Young & Thompson

20070245186 - Semiconductor integrated circuit device and method of testing the same: A semiconductor integrated circuit device includes a control circuit configured to generate a control code to control a parameter of a predetermined circuit and outputs the control code to the predetermined circuit; and a latch circuit connected with an output of the control circuit to latch the control code in... Agent: Young & Thompson

20070245189 - Testing system and testing system control method: A testing system includes: a plurality of test applying portions that operate a test device to make an output signal from the test device; a plurality of testing portions that test the output of the test device; and a test applying portion having a test device to output a tested... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070245187 - Testing system, testing system control method, and test apparatus: A testing system includes: a plurality of test applying portion that operate a test device to make an output signal from the test device; a plurality of testing portions that test the output of the test device; and a switch portion that switches the output signal between the test applying... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070245188 - Testing system, testing system control method, and test apparatus: A testing system includes: a plurality of test applying portions that operate a test device to make an output signal from the test device; a plurality of testing portions that test the output of the test device; and a switch portion that switches the output signal between the test applying... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070245190 - Intelligent binning for electrically repairable semiconductor chips: The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures are determined. In the... Agent: Trask Britt, P.C./ Micron Technology

20070245184 - Method and system for generating validation workflow: Systems and methods are provided that relate to a platform, techniques, and processes for verifying the precision, sensitivity, accuracy, reproducibility, and other characteristics of biological tests, such as DNA identification or other tests or assays. According to various embodiments, a logic engine can guide a user to, arrange, conduct, and... Agent: Kilyk & Bowersox, P.l.l.c.

20070245183 - Method and system for optimizing an integrated circuit: A method and system for optimizing an integrated circuit is described. The method includes generating (102) a characteristic table of the integrated circuit. The method further includes selecting (104) a functional module from one or more functional modules. Moreover, the method includes receiving (106) at least an input load or... Agent: David Tichane

20070245192 - Semiconductor integrated circuit device and delay fault testing method: A semiconductor integrated circuit device includes a plurality of flip-flops configured to form a scan chain in a scan path test to operate as a shift register. The first flip-flop of the plurality of flip-flops latches a first input signal in synchronization with a clock signal, outputs a first output... Agent: Foley And Lardner LLP Suite 500

20070245191 - At-speed transition fault testing with low speed scan enable: A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of... Agent: Texas Instruments Incorporated

20070245193 - Liquid crystal display and shift register unit thereof: A liquid crystal display and a shift register unit thereof are provided. The shift register unit includes a first switch, a second switch, and a level shift circuit. The first switch has a first input terminal, a first control terminal, and a first output terminal. The second switch has a... Agent: Rabin & Berdo, PC

20070245194 - Failure detection apparatus and failure detection method for a semiconductor apparatus: A failure detection apparatus for a semiconductor apparatus includes a clock line to transmit a clock signal, a shield line to shield the clock line, an inverted signal setting unit to supply signals inverted to each other to the clock and shield lines in a failure detection mode, and a... Agent: Mcginn Intellectual Property Law Group, PLLC

20070245195 - Method, system and program product for boundary i/o testing employing a logic built-in self-test of an integrated circuit: A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070245196 - Method for the evaluation of a first analog signal and a second analog signal, and evaluation circuit corresponding therewith: Two analog signals are substantially sinusoidal and out-of-phase by about 90° relative to each other when an element moves in a temporally uniform manner in relation to a stationary element. The two analog signals make it possible to determine the actual position of the moving element relative to the stationary... Agent: Siemens Corporation Intellectual Property Department

20070245197 - Method and apparatus for identifying paths having appropriate lengths for fault simulation: A fault analysis apparatus includes: an extracting unit that extracts a segment including a point of fault from a plurality of paths in a target circuit; a detecting unit that detects a candidate path that extends, via the segment, from an upstream circuit element to a downstream circuit element; a... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070245199 - Application specific distributed test engine architecture system and method: An Application Specific Distributed Test Engine (ASDTE) that provides an optimized set of test resources for a given application. The test engine resources, configuration, functionality, and even the number of test engines can be changed as different devices are tested, or as different test methodologies are used with the system.... Agent: Fenwick & West LLP

20070245200 - Semiconductor apparatus and test method therefor: A SiP includes a logic chip and a memory chip. The memory chip includes a memory circuit to be tested, and the logic chip includes an internal logic circuit and a test processor electrically connected therewith. The test processor is connected with an access terminal of the memory circuit and... Agent: Mcginn Intellectual Property Law Group, PLLC

20070245198 - Method and apparatus for interactive generation of device response templates and analysis: A device response template generator software program includes an interactive graphical-user-interface (GUI) for sending commands to devices under test and to capture and display the command responses. The GUI allows patternization of the command response to that the information contained in the response can be read, in the form of... Agent: Rajeev Madnawat Tm Patent Group

20070245203 - Apparatus and method for performing harq transmission in a wireless communication system: An apparatus and method for optimizing a data rate in a wireless communication system supporting Hybrid Automatic Repeat reQuest (HARQ) are provided. The method includes estimating Channel State Information (CSI) of a signal to be transmitted, by using other CSIs received in a previous cycle; determining an instantaneous data rate,... Agent: The Farrell Law Firm, P.C.

20070245202 - Hybrid automatic repeat request method in a mobile communication system and transmission/reception method and apparatus using the same: A Hybrid Automatic Repeat reQuest (HARQ) method performed in a receiver of a mobile communication system. The HARQ method includes receiving from a transmitter an initial transmission subpacket among a plurality of subpackets; sending a request for transmission of a retransmission subpacket to the transmitter upon failure to decode the... Agent: The Farrell Law Firm, P.C.

20070245201 - Method and system for implementing hybrid automatic repeat request: A receiver sends hybrid automatic repeat request (H-ARQ) feedback for a current packet and at least one previous packet, whereby an error is detected based on the H-ARQ feedback. The receiver sends H-ARQ feedback with an identification of the packet or a sequence number of a packet that the receiver... Agent: Volpe And Koenig, P.C. Dept. Icc

20070245205 - Automatic repeat request (arq) apparatus and method of multiple input multiple output (mimo) system: Automatic Repeat reQuest (ARQ) apparatus and method of a Multiple Input Multiple Output (MIMO system are provided. The ARQ method includes decoding, when one or more packets are received, the received packets and trying to detect the decoded packets; and storing, when error is detected from the packets, the corresponding... Agent: The Farrell Law Firm, P.C.

20070245204 - Retransmitting apparatus and method using relay station in a multi-hop network: An apparatus and method for retransmitting data using an RS in a multi-hop network are provided. When retransmitting data in a BS, the BS transmits data and activates a timer therefor. The BS monitors receipt of a response message for the data until the timer expires. The BS receives the... Agent: The Farrell Law Firm, P.C.

20070245206 - Method for transmitting a radio navigation signal: The invention relates to a method of transmitting a radionavigation signal which comprises coded and interleaved data; the signal comprises a pathway modulated by the coded and interleaved data and another pathway not modulated by these data, and the pathway not modulated by these data comprises a known code Cp... Agent: Lowe Hauptman & Berner, LLP

20070245209 - Decoding method for tail-biting convolutional codes using a search depth viterbi algorithm: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and... Agent: Stmicroelectronics, Inc.

20070245207 - Digital broadcasting transmission apparatus and inserting method of information for receiver demodulation thereof: A digital broadcasting transmission apparatus and an inserting method of information for receiver demodulation thereof. The digital broadcasting transmission apparatus includes: a turbo coder performing turbo coding on a transport stream (TS) a field sync signal generator inserting information for receiver demodulation into a reserved area of a field sync... Agent: Stein, Mcewen & Bui, LLP

20070245208 - Erasures assisted block code decoder and related method: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes,... Agent: Howrey LLP

20070245217 - Low-density parity check decoding: Low Density Parity Check encoded signals propagated over a channel are decoded by iteratively producing messages representative of the a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation. The check-node update computation is performed as a MIN-SUM approximation and... Agent: Seed Intellectual Property Law Group PLLC

20070245215 - Method and apparatus to data encode and decode, storage medium having recorded thereon program to implement the method, and system to drive the storage medium: A method of and apparatus to data encode and decode for improving the reliability of data that is compatible with a conventional error correction code (ECC) block format, a storage medium, a system to drive the storage medium, and a method of generating an extra parity ECC block, the data... Agent: Stein, Mcewen & Bui, LLP

20070245214 - Multi-level signal memory with ldpc and interleaving: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes... Agent: Schwabe, Williamson & Wyatt, P.C.

20070245213 - Reproduction device and reproducing method: A reproduction device for improving reading performance. A storage processing unit includes a detection circuit for detecting a sync code from read data, which includes alternately arranged sync codes and data segments. An analysis circuit analyzes a read status of the sync code detected by the detection circuit. A storage... Agent: Arent Fox PLLC

20070245212 - Encoding method, transmitter, network element and communication terminal: The invention relates to a transmitter comprising: means (304) for arranging information bits in an information matrix; means (304) for encoding rows of the information matrix for generating a base code matrix; means (304) for generating a parity check row for the base code matrix to obtain an extended code... Agent: Squire, Sanders & Dempsey L.L.P.

20070245216 - Method and apparatus for detecting synchronization of broadcasting channel in an asynchronous mobile communication system: An apparatus for detecting synchronization of a Broadcasting Channel (BCH) in an asynchronous mobile communication system. A Viterbi decoder calculates a zero state path metric and a minimum path metric through an Add-Compare-Select (ACS) process and a trace-back process while decoding a frame of a received BCH. A Cyclic Redundancy... Agent: The Farrell Law Firm, P.C.

20070245211 - Method for encoding/decoding concatenated ldgm code: A decoding method in a concatenated low-density generator matrix (LDGM) code-based transmission system for detecting a signal using a parity check matrix including a systematic bit part mapped to systematic bits and a parity check part mapped to parity bits. The decoding method includes generating an outer code parity check... Agent: Dilworth & Barrese, LLP

20070245210 - Quiescence for retry messages on bidirectional communications interface: A mechanism to obtain a quiescence state for a component coupled to a bidirectional communications interface is obtained. A transition to quiescence may be may by activating a first defeature in the component to cause messages received over a communication bus coupled between the component and another component to be... Agent: Blakely Sokoloff Taylor & Zafman

20070245218 - Semiconductor integrated circuit and record player: The present invention provides a technique capable of performing a process for encoding data read from a first storing medium and writing the encoded data to a second storing medium seemingly at high speed and, moreover, excellently protecting the copyright of the data. A semiconductor integrated circuit includes: a first... Agent: Miles & Stockbridge PC

20070245219 - Data decoding method and apparatus and receiver and communication system applying the same: A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20070245220 - Error correction apparatus: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged... Agent: Greer, Burns & Crain

20070245221 - Multi-mode processor: An apparatus is configured to perform both Fourier transform processing and Golay code processing. Each of a plurality of processing elements comprises a delay element configured for providing a predetermined delay to at least a first input signal, at least one seed vector insertion element configured for multiplying at least... Agent: Steven J Shattil

20070245222 - Lip synchronization system and method: A system and method for correcting so-called “lip sync” errors is provided, using a synchronization test signal comprising a video signal including a colourbar signal that is periodically interrupted by a series of consecutive defined black frames and an audio signal comprising a tone periodically interrupted by a period of... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.

20070240017 - Storage apparatus power supply unit and storage apparatus management method: In a power supply unit for a storage apparatus according to the present invention, it is possible to detect a power supply abnormality inside a device of another company, for which environment information is not directly acquirable. For a load device provided by a vendor that differs from the vendor... Agent: Reed Smith LLP

20070240020 - Serialization of hardware and software debug data: An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing... Agent: Mendelsohn & Associates, P.C.

20070240014 - Storage subsystem and information processing system: According to the invention, techniques for detecting and recovering from errors occurring in disk drive subsystems having a controller and drive units connected by a fibre channel loop. Specific embodiments can provide storage subsystems, methods and apparatus for use in information processing environments, for example. Embodiments can determine when each... Agent: Townsend And Townsend And Crew, LLP

20070240015 - Method for safely interrupting blocked work in a server: A method for safely interrupting blocked work in a server including: creating a registry; registering a potential blocking event in the registry; executing the potential blocking event; determining that the potential blocking event is not responding; accessing a registry entry corresponding to the blocking event; and taking an corrective action... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070240016 - Arbitration method and system for redundant controllers, with output interlock and automatic switching capabilities: An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070240018 - Functional level reset on a per device/function basis: A device within a system, or an individual function of the device, may be reset to a known state while all other devices in the system or other functions of the device that are not being reset remain operational.... Agent: Intel Corporation C/o Intellevate, LLC

20070240019 - Systems and methods for correcting errors in i2c bus communications: Systems, methods and media for clearing a hung I2C bus are disclosed. In one embodiment, a monitor monitors the I2C bus data and clock lines and detects if a hung bus occurs. The monitor times packet transactions on the bus to determine if a maximum transaction time has elapsed while... Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson PLLC

20070240021 - Method, system and program product for autonomous error recovery for memory devices: An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070240022 - Analysis apparatus and analysis method: There is provided an analysis apparatus 30 for analyzing test results of testing, by using a test apparatus, a plurality of devices under test having the same configuration. The analysis apparatus 30 includes: an acquiring unit 300 that acquires a judgment result of comparing, to an expected value, a value... Agent: Osha Liang L.L.P.

20070240024 - Scan driving circuit and organic light emitting display using the same: A scan driving circuit includes a first scan driver including a plurality of first units, the first units receiving an input signal or an output voltage of a previous first unit and first and second clock signals to output a scan signal, and a second scan driver having a plurality... Agent: Lee & Morse, P.C.

20070240023 - Data shift capability for scannable register: A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070240025 - Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit: A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's... Agent: Heslin Rothenberg Farley & Mesiti P.C.

20070240026 - method evaluating threshold level of a data cell in a memory device: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus;... Agent: Texas Instruments Incorporated

20070240027 - Forward error correction decoders: An erasure information table includes one element for each column of a data frame, stored in an IP datagram buffer and in an RS data buffer, instead of an element for each element of that column. Thus, CRC checking is performed against datagrams, instead of individual elements, of a received... Agent: Harrington & Smith, PC

20070240028 - Vehicle including a processor system having fault tolerance: A vehicle includes a high assurance processing system including a plurality of data processors coupled in parallel, a bridge coupled to the input/output processor, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor... Agent: Paul D. Durkee Daly, Crowley, Mofford & Durkee, LLP

20070234115 - Backup system and backup method: Provided is a method causing a node of a local site or of a remote site to take over a file server when a failure occurs to a node of the local site. The method includes the steps of: setting a priority of the failover to the respective nodes of... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070234119 - Forced termination condition monitoring device, forced termination condition monitoring method and storage medium embodying forced termination condition monitoring program: To terminate startup of an application on an ASP side irrespective of checking on a user side whether or not the application is in the middle of processing. A monitoring device includes means monitoring an operating status of an information processing device for providing a service by starting up an... Agent: Staas & Halsey LLP

20070234132 - System and method for indicating errors of a motherboard: An exemplary method for indicating errors of a motherboard is provided. The method includes: setting a flicker count for indicating different error types occurred on a motherboard, and inserting the flicker count and corresponding error types in an error information index; resetting or clearing statuses information of the motherboard from... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070234101 - Information error recovery apparatus and methods: Information error recovery apparatus and methods are disclosed. Responsive to an error detected in information retrieved from an information store for use by a processor in a software execution flow, the software execution flow of the processor is suspended. Use of the information store by the processor is also disabled.... Agent: Arnold B. Silverman Eckert Seamans Cherin & Mellott, LLC

20070234102 - Data replica selector: There is provided a method and system for replicating data at another location. The system includes a source node that contains data in a data storage area. The source node is coupled to a network of potential replication nodes. The processor determines at least two eligible nodes in the network... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco Pl

20070234103 - Method and system for performing recovery of a single-threaded queue: A method, system and computer program product for performing recovery of a single-threaded queue are disclosed. The method includes scanning a set of elements of the single-threaded queue to detect a cycle containing a first element, and, in response to detecting the cycle, determining a size of the cycle in... Agent: Dillon & Yudell LLP

20070234104 - Computer platform setup configuration data backup handling method and system: A computer platform setup configuration data backup handling method and system is proposed, which is designed for use in conjunction with a computer platform for providing the computer platform with a configuration data memory backup handling function, and which is characterized by the capability of making a backup copy of... Agent: Edwards Angell Palmer & Dodge LLP

20070234107 - Dynamic storage data protection: A method, system and computer program product are provided for increasing the level of protection for data in a redundant storage system. A non-catastrophic error in a component in a redundant storage system is detected. Then, data exposed by the non-catastrophic error is identified and unallocated space in a storage... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070234105 - Failover to asynchronous backup site in connection with triangular asynchronous replication: Handling failure of a primary group at a first data center that is part of plurality of data centers providing triangular asynchronous replication includes creating a data mirroring relationship between at least one storage volume at a second data center having a synchronous backup group that is part of the... Agent: Muirhead And Saturnelli, LLC

20070234108 - Failover to synchronous backup site in connection with triangular asynchronous replication: Handling failure of a primary group at a first data center that is part of plurality of data centers providing triangular asynchronous replication, includes creating a data mirroring relationship between at least one storage volume at a second data center having a synchronous backup group that is part of the... Agent: Muirhead And Saturnelli, LLC

20070234106 - Resumption of operations following failover in connection with triangular asynchronous replication: Handling failure of a primary group at a first data center that is part of plurality of data centers providing triangular asynchronous replication includes creating a data mirroring relationship between at least one storage volume at a second data center having a synchronous backup group that is part of the... Agent: Muirhead And Saturnelli, LLC

20070234109 - Virtual disk drive system and method: A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070234110 - Virtual disk drive system and method: A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070234111 - Virtual disk drive system and method: A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain... Agent: Dorsey & Whitney LLP Intellectual Property Department

20070234113 - Path switching method: Provided is a computer system including at least one host computer; and at least one storage system, characterized in that: the storage system has a disk drive and a disk controller, and provides a storage area of the disk drive as at least one logical unit; upon detecting a failure... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070234112 - Systems and methods of selectively managing errors in memory modules: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors.... Agent: Hewlett Packard Company

20070234116 - Method, apparatus, and computer product for managing operation: When a server RM detects a failure in an operating server, a system resource manager selects a substitute server from a pool of a server domain to which a failed server belongs, based on information in a system resource DB, disconnects the failed server from a business network and a... Agent: Greer, Burns & Crain

20070234114 - Method, apparatus, and computer program product for implementing enhanced performance of a computer system with partially degraded hardware: Enhanced performance is provided for a computer system with partially degraded hardware. A performance deconfiguration event is identified for a hardware item. The hardware item is marked in a performance deconfiguration state. When there is at least one fully working spare available for the hardware item of the performance deconfiguration... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070234117 - Apparatus and method to convert data from a first sector format to a second sector format: An apparatus is disclosed to convert data from a first sector format to a second sector format. The sector format conversion device includes a processor, and microcode which causes the processor to overlay (N) first sectors having a first sector format onto (M) second sectors having a second sector format,... Agent: Dale F. Regelman

20070234118 - Managing communications paths: Communications paths are managed. An error is detected on a first storage processor. It is determined that the error resulted from a peer-to-peer communication from a second storage processor. The error on the first storage processor is handled by taking action short of causing the first storage processor to reset.... Agent: Richard M. Sharkansky

20070234120 - Semiconductor storage device: A testing device for a semiconductor storage device which suppresses the increase in the circuit size, provides for facilitated accommodation to a test with frequent changes in the test pattern, and which improves testability of the semiconductor storage device. A plural number of holding circuits (103) are provided holding write... Agent: Young & Thompson

20070234121 - Method and system for automated testing of a graphic-based programming tool: A method and a system for automated testing of a graphic-based programming tool. The present invention includes a computer-implemented method that allows a developer to easily generate scripts for automatically testing a graphic-based programming tool using generic reusable building blocks of test code and separate decoupled parameter data. The method... Agent: Kenyon & Kenyon LLP

20070234122 - Computer program runtime bottleneck diagnostic method and system: A computer program runtime bottleneck diagnostic method and system is proposed, which is designed for use in conjunction with a computer platform for providing a BIOS (Basic Input/Output System) POST (Power On Self Test) runtime bottleneck diagnostic function, which is characterized by the capability of recording the runtime length of... Agent: Fulbright And Jaworski LLP

20070234124 - Management function setting method for intelligent platform management interface: A management function setting method for dynamically setting a plurality of management functions of an intelligent platform management interface (IPMI) of a computer system, allows a system manager to obtain a system status through the IPMI, and set customized commands for selecting needed function modules for execution. Through the establishment... Agent: Edwards Angell Palmer & Dodge LLP

20070234123 - Method for detecting switching failure: A method for detecting a switching failure, applied to a system having a Base Management Controller (BMC), a BIOS and a CPU under an Intelligent Platform Management Interface (IPMI), so as to avoid failure when the BMC switches from a Fault Resilient Booting (FRB) 3 mechanism to a FRB 2... Agent: Edwards Angell Palmer & Dodge LLP

20070234125 - Logic soft error rate prediction and improvement: A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070234126 - Accelerating the testing and validation of new firmware components: New firmware versions may be tested more efficiently and more quickly by making an analysis of how a change in the firmware affects components, protocols, and drivers. Based on a determination of the dependencies between the changed components, drivers, and protocols, a list of tests that need to be undertaken... Agent: Trop Pruner & Hu, PC

20070234128 - Method and a circuit using an associative calculator for calculating a sequence of non-associative operations: An apparatus and method that use an associative calculator for calculating a sequence of non-associative operations on a set of input data, comprising: using the associative calculator to calculate from the set of input data an evaluated value of each operation of said sequence as if the non-associative operations were... Agent: Ladas & Parry

20070234127 - Methods and systems for automated testing of applications using an application independent gui map: Methods and systems for the automated testing of applications using an application independent GUI map are disclosed. A method includes receiving a command to change a physical description of an object of a general class in the GUI map. A physical description of the object of general class is changed... Agent: Marger Johnson & Mccollom, P.C.

20070234129 - Asynchronous fault handling in process-centric programs: Asynchronous fault handling for a workflow. A state automaton for an activity in the workflow is defined. The state automaton includes at least an executing state, a faulting state, and a closed state and classifies an execution lifetime of the activity. The activity is defined to include work items and... Agent: Senniger Powers (msft)

20070234130 - Managing system components: System components are managed. Based on a first communication path to a component, first identification information for the component is determined. Based on a second communication path to the component, second identification information for the component is determined. Based on the first identification information and the second identification information, an... Agent: Richard M. Sharkansky

20070234131 - Server inspecting method and system: A server inspecting method and system for inspecting a module to be inspected of a server is disclosed. This provides a time-saving and labor-saving inspecting method for users, and reduces the consumption of human resources and improves the working efficiency of inspecting personnel. Moreover, the system and method can further... Agent: Edwards Angell Palmer & Dodge LLP

20070234133 - Device and method for testing memory access time using pll: A device and method for testing memory access times of a memory using a phase-locked loop (PLL) are described. The device for testing the memory access time of a memory may include a PLL and a test unit, and may also include a memory controller. The PLL may generate a... Agent: Harness, Dickey & Pierce, P.L.C

20070234134 - Method and system for enhancing transmission reliability of video information over wireless channels: A method and system for enhancing transmission reliability of video information over a wireless channel is provided. The video information includes pixels, each having a plurality of components and each component including video information bits that are placed in sub-packets within a packet. Error detection information is determined for one... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20070234136 - Method and apparatus for detecting the presence of errors in data transmitted between components in a data storage system using an i2c protocol: A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage... Agent: David E. Huang, Esq. Bainwood Huang And Associates LLC

20070234135 - Systems and methods for visualizing bit errors: Systems and methods for analyzing the performance of a digital network include capturing a stream of digital data, e.g., internet protocol (IP) packets, that represent streaming video, identifying which of the IP packets include bit errors, determining to which of a plurality of pixels the IP packets including bit errors... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070234138 - Semiconductor integrated circuit and method for testing semiconductor integrated circuit: A check computation circuit executes a computation corresponding to a computation for generating confidential CRC data, with respect to confidential data read from a non-volatile device. A comparison circuit compares the result of the computation in the check computation circuit with confidential CRC data read from the non-volatile device. When... Agent: Mcdermott Will & Emery LLP

20070234137 - Semiconductor integrated circuit and method of production of same: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of... Agent: Rader Fishman & Grauer PLLC

20070234139 - Method and apparatus for verifying the correctness of ftap data packets received on the flo waveform: Systems and methodologies are described that facilitate verifying correctness of FLO test application protocol (FTAP) data packets. According to various aspects, systems and/or methods are described that enable generating an expected test signature at an FTA client (e.g., mobile device), receiving FTAP flow data packets and/or effectuating comparisons between received... Agent: Qualcomm Incorporated

20070234140 - Method and apparatus for determining relative relevance between portions of large electronic documents: A technique for determining the relative relevance of electronic documents based on metadata/content associated with the document as a whole and/or metadata/content associated with one or more subdivisions of the electronic document. Metadata is associated with the document and various subdivision markers in the code of the document. A comparison... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070234141 - Concept for testing an integrated circuit: An integrated circuitry operable in a normal and test mode has a processing circuit, an output circuit associated with the processing circuit and a storage with a plurality of memory cells. The output circuit is formed to process in normal mode an output signal of the processing circuit and to... Agent: Baker Botts, L.L.P.

20070234142 - Memory system, memory system controller, and a data processing method in a host apparatus: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070234143 - Semiconductor memory devices and methods of testing for failed bits of semiconductor memory devices: A semiconductor memory device includes a flash memory including a plurality of M-byte memory pages, and a buffer memory that includes a first M-byte buffer and a second M-byte buffer and that is configured to receive expected data used to test for failed bits in the flash memory. The semiconductor... Agent: Myers Bigel Sibley & Sajovec

20070234144 - Smart verify for multi-state memories: A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number... Agent: Davis Wright Tremaine LLP - Sandisk Corporation

20070234149 - Checking the integrity of programs or the sequencing of a state machine: A method and a circuit for protecting the execution of a calculation by an electronic circuit, conditioning a result of the calculation to states of bits indicative of executions of steps of access in read mode and/or in write mode to storage elements.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070234148 - Early detection of storage device degradation: An apparatus operable with a host and a data storage component for detecting a storage device susceptible to failure under I/O workload is provided. The apparatus includes a selector component for selecting a pair of storage devices in the data storage component. A data migration control component is provided for... Agent: International Business Machines Corporation

20070234147 - Circuit analysis device: A circuit analysis device comprises a first storing unit operable to store an execution object which can operate on a real processor and includes information of a logical circuit, an analyzing unit operable to analyze operation which is based on the function of the logical circuit and is coordinated with... Agent: Wenderoth, Lind & Ponack L.L.P.

20070234145 - Reduced pattern memory in digital test equipment: A test system and method of configuring therefor. A test system includes a plurality of interface circuits for communicating with a device under test (DUT). The test system further includes a first memory for storing test vectors, a second memory for storing selection codes, and a third memory for storing... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070234146 - Test method, test system and assist board: A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory ; reading sequentially the written test... Agent: Osha Liang L.L.P.

20070234153 - Semiconductor integrated circuit apparatus and control method thereof: A semiconductor integrated circuit apparatus includes an internal logic circuit unit, a first memory, a second memory and a control circuit unit. The internal logic circuit unit includes scan chains which test circuit normality. The first memory is accessed by the internal logic circuit. The second memory stores valid bits... Agent: Foley And Lardner LLP Suite 500

20070234151 - Thin film transistor array substrate and electronic ink display device: A thin film transistor array substrate suitable for being applied in an electronic ink display device is provided. The thin film transistor array substrate includes a substrate, scan lines, data lines, thin film transistors, pixel electrodes and testing signal lines. The data lines and the scan lines are disposed and... Agent: Sheehan Phinney Bass & Green, PA C/o Peter Nieves

20070234152 - Data driver and flat panel display device using the same: A flat panel display device including: a display region including pixels connected to scan lines and data lines; a dummy display region including dummy pixels connected to at least two dummy scan lines and the data lines; a scan driver for providing scan signals and dummy scan signals to the... Agent: Christie, Parker & Hale, LLP

20070234150 - Scan tests tolerant to indeterminate states when employing signature analysis to analyze test outputs: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving... Agent: Texas Instruments Incorporated

20070234155 - Probeless testing of pad buffers on wafer: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.... Agent: Texas Instruments Incorporated

20070234154 - Scan testing using scan frames with embedded commands: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan... Agent: Texas Instruments Incorporated

20070234156 - Electronic circuit comprising a test mode secured by the breaking of a test chain, and associated electronic circuit: An electronic circuit includes configurable cells with a test input and an output. The configurable cells are capable of being connected to one another in a chain in a predefined order via the test inputs and the outputs to form a test shift register if they receive a chaining command... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070234157 - Multi-stage test response compactors: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about... Agent: Klarquist Sparkman, LLP

20070234158 - Method of testing a semiconductor memory device, method of data serialization and data serializer: A semiconductor memory device is tested responsive to an output clock signal. Parallel test data in the semiconductor memory device are generated and a plurality of data output clock signals are generated by selectively activating one of the data output clock signals according to a test mode. The parallel test... Agent: Marger Johnson & Mccollom, P.C.

20070234160 - Self test device and self test method for reconfigurable device mounted board: A self test device includes an operational element determining unit that calculates, based on operation parameters for the time of operation of a board on which a reconfigurable device is mounted, operational elements used in the devices of the board for the operation, and non-operational elements; an element assignment determining... Agent: Katten Muchin Rosenman LLP

20070234159 - Method and apparatus for testing a ring of non-scan latches with logic built-in self-test: A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070234164 - Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20070234162 - Integrated semiconductor memory and methods for testing and operating the same: In the context of functional tests a check is made to ascertain whether an integrated semiconductor memory satisfies specified operating parameters. In this case, operating parameters, such as the externally applied operating frequency or the externally applied operating voltage, are varied within specific limits. Integrated semiconductor memories which function without... Agent: Edell, Shapiro & Finnan, LLC

20070234163 - On-chip comparison and response collection tools and techniques: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about... Agent: Klarquist Sparkman, LLP

20070234161 - Using neighborhood functions to extract logical models of physical failures using layout based diagnosis: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined... Agent: Jones Day

20070234166 - Inverter and display device having the same: A display device and an inverter therefor are disclosed. The inverter has a main circuit board having a plurality of first circuit patterns and a plurality of second circuit patterns formed on a first side thereof, and a sub circuit board having first connecting patterns corresponding to the plurality of... Agent: Macpherson Kwok Chen & Heid LLP

20070234165 - Input circuit of semiconductor memory device and test system having the same: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled... Agent: Marger Johnson & Mccollom, P.C.

20070234167 - Semiconductor device: A disclosed semiconductor device includes one or more test terminals; a test control circuit configured to receive signals as one or more inputs thereof from the one or more test terminals to test an internal circuit by changing a status of the internal circuit according to the signals; a non-volatile... Agent: Ladas & Parry LLP

20070234169 - Generating masking control circuits for test response compactors: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about... Agent: Klarquist Sparkman, LLP

20070234168 - Semiconductor integrated circuit device and inspection method therefor: A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected... Agent: Mcdermott Will & Emery LLP

20070234170 - Method and system for communication of video information over wireless channels: A method and system for transmitting video information from a sender to a receiver over a wireless channel is provided. Video information bits are placed into one or more data packets at the sender, and each data packet is transmitted from the sender to the receiver over a wireless channel... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20070234171 - Fault tolerant decoding method and apparatus including use of quality information: Units of forward error correction (FEC) encoded bits each represent a one-bit data value and include correctness bits that together reflect a probability that the one-bit data value represented by the unit is correct. The units of FEC encoded bits are decoded by using the correctness bits to perform soft-decision... Agent: Roberts, Mardula & Wertheim, LLC

20070234172 - Apparatus and method for transmitting and recovering encoded data streams across multiple physical medium attachments: A method includes generating an encoded data block, dividing the encoded data block into a plurality of sub-blocks, and transmitting the plurality of sub-blocks over a plurality of physical medium attachments. The encoded data block may be generated using 64B/66B encoding, and the data being encoded could first be decoded... Agent: Lisa K. Jorgenson, Esq. Stmicroelectronics, Inc.

20070234173 - Byte level protection in pci-express devices: Method and system for protecting data in a PCI-Express device is provided. The method includes adding error correction code (ECC) to every byte of data that enters a PCI-Express Transaction Handler (“PTH”) Module and is destined for a host system memory or destined to another device, before the data is... Agent: Klein, O'neill & Singh, LLP

20070234174 - Method and device for error handling in the transmission of data via a communications system: A method and a device for error handling in the transmission of coded data in the form of at least one data word via a communications system, for the at least one data word a code data word being selected according to a specifiable coding rule, the data being represented... Agent: Kenyon & Kenyon LLP

20070234175 - Methods and apparatus for interleaving in a block-coherent communication system: Methods and apparatus for communication over a block-coherent communication system are described. The present invention is directed to methods of interleaving coded bits that are encoded by codes, e.g., LDPC codes, having graph structures largely comprised, e.g., of multiple identical copies of a much smaller graph.... Agent: Qualcomm Incorporated

20070234176 - Fast decoder and method for front end of convolutionally encoded information stream: A system and method enable the fast decoding of a front end of data (e.g., a header) that is convolutionally encoded by treating the front end as a block code.... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070234177 - Method and apparatus for checking pipelined parallel cyclic redundancy: A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is... Agent: Sughrue Mion, PLLC

20070234179 - Method and system for providing short block length low density parity check (ldpc) codes in support of broadband satellite applications: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or... Agent: The Directv Group Inc

20070234178 - Soft information scaling for interactive decoding: Methods and apparatus for scaling soft values as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for... Agent: Qualcomm Incorporated

20070234180 - High spread highly randomized generatable interleavers: Methods and apparatus for generating and performing digital communications using a randomized generatable interleaver. In accordance with one exemplary embodiment of the invention, a pseudo random interleaver of size n*m with excellent randomness and spread properties may be generated from a set of seed values. The interleaver of size N=n*m... Agent: Robert F. Gazdzinski. Esq. Gazdzinski & Associates

20070234183 - Multi-bit memory device and memory system: A nonvolatile memory device, memory system and read method are disclosed. The memory device comprises a memory cell array comprising a plurality of memory blocks each having a plurality of memory cells adapted to store N bits, where N is an integer greater than 1, a page buffer configured to... Agent: Volentine & Whitt PLLC

20070234182 - Error checking and correction (ecc) system and method: A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The... Agent: Hewlett Packard Company

20070234181 - Error correction device and methods thereof: A device for error correction and methods thereof are disclosed. The method includes retrieving raw data from a memory device during a first operational phase of the error correction device. The raw data is retrieved by a bus interface device that interfaces with a variety of memory devices. During a... Agent: Larson Newman Abel Polansky & White, LLP

20070234184 - Methods and apparatus for reducing error floors in message passing decoders: An iterative message passing decoder, e.g., an LDPC decoder, operating in conjunction with a soft input-soft output signal processing unit, e.g., an ISI detector, has an error floor performance region influenced by the decoder's sub-optimal message passing nature. Error floor reduction is achieved by a simple message re-initialization mechanism. Decoder... Agent: Qualcomm Incorporated

20070234185 - Fault tolerant decoding method and apparatus: Units of forward error correction (FEC) encoded bits each represent a one-bit data value and include correctness bits that together reflect a probability that the one-bit data value represented by the unit is correct. The units of FEC encoded bits are decoded by using the correctness bits to perform soft-decision... Agent: Roberts, Mardula & Wertheim, LLC

20070234186 - Packet transmission apparatus and method using optimized punctured convolution codes: A method of communication between or among a plurality of devices in a communication system using one or more frames to transmit a plurality of bits includes encoding the plurality of bits in accordance with a first puncture code in a first device of the plurality of devices, transmitting the... Agent: Ratnerprestia

20070234187 - Scheduling pipelined state update for high-speed trellis processing: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating... Agent: Townsend And Townsend And Crew, LLP

20070234188 - Maximum likelihood decoding device, signal evaluating method, and reproducing apparatus: A maximum likelihood decoding device including Viterbi detecting means performing bit detection from a reproduced signal in which bit information is reproduced, the Viterbi detecting means variably setting reference levels used for branch metric calculation according to level of the reproduced signal, Euclidean distance calculating means calculating a Euclidean distance... Agent: Rader Fishman & Grauer PLLC

20070234189 - System and method for reducing false alarm in the presence of random signals: System and methods for reducing false alarm in the presence of random signals are disclosed. Various embodiments are operable to receive via a data interface a data block having at least one frame, normalize soft bits of the data block and re-encode decoder output bits of the data block, calculate... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070234190 - Viterbi decoding apparatus and viterbi decoding method: In a Viterbi decoding apparatus, deterioration in error correcting capability before and after a terminated code is controlled. A termination timing detection unit (103) detects a termination timing of a Viterbi code, a compulsion generation unit (105) generates a compulsion value so as to pass a specific path at the... Agent: Steptoe & Johnson LLP

20070234191 - Methods and apparatus for dynamically reconfigurable parallel data error checking: In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in... Agent: Ibm Corporation, Intellectual Property Law