Error detection/correction and fault detection/recovery inventions 09/07

20070226538 - Apparatus and method to manage computer system data in network: A data-management apparatus and method, the apparatus including: a display unit to display a user interface that includes management options for a plurality of load-balancing cluster-based devices connected through a network; an input unit to receive a selection value; and a control unit to manage the plurality of load-balancing cluster-based... Agent: Stein, Mcewen & Bui, LLP

20070226541 - Memory-based trigger generation scheme in an emulation environment: A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory... Agent: Klarquist Sparkman, LLP

20070226532 - Network node, switch, and network failure recovery method: A switch includes a reference log storage table for storing a plurality of reference logs for performing normal connection processing between network nodes, a connection candidate log search program for searching for a connection candidate log from among a plurality of reference logs based on a failure log acquired when... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070226534 - Disk device, control circuit, data-writing control method, command control method, and computer product: A degree-of-multiplexing calculating unit receives a capacity restriction command including information for specifying a recording capacity used to write data on a disk from a host computer and calculates degree of multiplexing of the data based on the recording capacity. A writing unit writes data received from the host computer... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070226533 - System and method for servicing storage devices in a bladed storage subsystem: A bladed storage servicing system comprising a RAID layout facilitates the removal of one or more functional storage devices in a tray of the bladed storage subsystem in order to service a failed storage device. Upon removal of the tray from the bladed storage subsystem, the system designates the functional... Agent: Shimokaji & Associates, P.C.

20070226535 - Systems and methods of unified reconstruction in storage systems: Systems and methods for reconstructing unified data in an electronic storage network are provided which may include the identification and use of metadata stored centrally within the system. The metadata may be generated by a group of storage operation cells during storage operations within the network. The unified metadata is... Agent: Mcdermott Will & Emery LLP

20070226536 - Apparatus, system, and method for information validation in a heirarchical structure: An apparatus, system, and method are disclosed for validating information in a hierarchical structure of redundant devices. A first plurality of redundant devices is examined to determine if status information residing within each of the redundant devices is consistent with each other. If the status information is inconsistent, the first... Agent: Kunzler & Mckenzie

20070226537 - Isolating a drive from disk array for diagnostic operations: A storage system includes a RAID adapter, disk array switches, sub-processors, and hard disk drives (HDDs). The system permits the isolation of a suspected faulty HDD to allow diagnostics to be performed without impacting operation of the rest of the system. Upon detection of a possible fault in a target... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070226539 - Integrated circuit and processing system with improved power source monitoring and methods for use therewith: A processing system includes a direct current to direct current (DC-DC) converter for generating a supply voltage when coupled to a battery. A memory module stores a plurality of operational instructions. A processing module receives power from the DC-DC converter and executes the plurality of operational instructions. A power monitor... Agent: Garlick Harrison & Markison

20070226540 - Knowledge-based diagnostic system for a complex technical system, comprising two separate knowledge bases for processing technical system data and customer complaints: The present document describes a diagnostic system for localizing faults in diagnostics in a workshop. The diagnostic system takes into account both trivial and costly intermittent fault situations. It is characterized by a structured module concept for the software architecture. Division into localization of quasi-steady-state and intermittent faults is carried... Agent: Fitch, Even, Tabin & Flannery

20070226542 - Simulated message generation for simulation testing of a node operation: In a distributed data processing domain including a plurality of data processing nodes, a simulation data processing node is operated as a participant in a simulation testing of a node operation to determine a simulation job and a simulation command responsive to the simulation testing of the node operation. The... Agent: Frank C. Nicholas Cardinal Law Group

20070226543 - User customizable expert system for communications testing: A user customizable expert system for communications testing has an Editor program for creating a test package file by an expert for transferral to a measurement instrument, and a Player program for running the test package file on the measurement instrument according to a guide provided to a technician. The... Agent: Matthew D. Rabdau Tektronix, Inc.

20070226544 - Generation of trace elements within a data processing apparatus: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises logic producing a series of data elements, indicative of the operation or state of all or part of the logic. Trace logic is provided for receiving indications of these data elements, and for... Agent: Nixon & Vanderhye, PC

20070226545 - Methods and systems for generating and storing computer program execution trace data: Methods and systems for generating and storing computer program execution trace data are disclosed. A method includes receiving a signal that enables the generation of computer program execution trace data in accordance with data stored in a register. The computer program execution trace data is generated and stored in memory.... Agent: Marger Johnson & Mccollom, P.C.

20070226546 - Method for determining field software reliability metrics: The invention includes a method for determining a software reliability metric, including obtaining testing defect data, obtaining test case data, determining testing exposure time data using the test case data, and computing the software reliability metric using testing defect data and testing exposure time data. The defect data includes software... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20070226547 - Disk controller and controlling method of the same: Disclosed is a disc controller, which includes a network controlling unit for receiving a data input/output request sent from an external device through a network, and a disc controlling unit formed in the same circuit board in which the network controlling unit is formed, the disc controlling unit coupling the... Agent: Townsend And Townsend And Crew, LLP

20070226548 - System for booting from a non-xip memory utilizing a boot engine that does not have ecc capabilities during booting: A booting system is disclosed for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting. The booting system includes: a non-XIP memory for storing a boot loader code and a plurality of operation system (OS) images, wherein the OS images in the... Agent: North America Intellectual Property Corporation

20070226549 - Apparatus for detecting errors in a communication system: A communication network switch comprises a control module having a control processor and a plurality of communication modules connected to the control module via a control interface. Each communication module comprises a detector for detecting errors associated with communication signals such as read and write access requests received from the... Agent: Eckert Seamans Cherin & Mellott, LLC.

20070226550 - Method and apparatus for generating non-binary balanced codes: A decoder comprises a grouping module that groups an input signal into a plurality of blocks and a plurality of permutation symbols, wherein the plurality of blocks include N symbols and wherein each of said N symbols has one of q symbol values, where q and N are integers greater... Agent: Harness, Dickey & Pierce P.L.C

20070226551 - Apparatus and method for checking an error recognition functionality of a memory circuit: An apparatus for checking an error recognition functionality of a memory circuit, wherein the memory circuit includes a memory circuit that stores a datum and a check value circuit that executes the error recognition functionality and a monitoring circuit, wherein the memory circuit provides the datum to the check value... Agent: Dickstein Shapiro LLP

20070226552 - Semiconductor integrated circuit and the same checking method: A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses programmed in accordance with identification information for specifying a chip mounting the cell array, a plurality of second fuses programmed in accordance with the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070226553 - Multiple banks read and data compression for back end test: Methods and apparatus that may be used to increase back-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the compression that may be achieved in back-end testing, particularly when only an indication of whether a device has passed or failed is... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070226560 - Electronic circuit and integrated circuit including scan testing circuit, and power consumption reducing method used for integrated circuit: An integrated circuit with a scan testing circuit which enables reducing power consumption in normal operation mode is provided. A power-supply controller applies a power-supply voltage to internal and external transmission circuits in scan test mode and stops applying the power supply voltage in normal operation mode. Thus, power consumption... Agent: Young & Thompson

20070226559 - Multimedia device testing method: A multimedia device testing method is provided. The multimedia device testing method includes providing test files of each test signal according to parameters of each test signal via a computer; combining the files of each test signal into one file with a composite test signal via the computer; compiling the... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070226555 - Graphical presentation of semiconductor test results: Methods and apparatus for graphically presenting test results of a circuit device under test are presented. Test results of a circuit device under test are acquired. Graphical diagrams comprising representations of at least a portion of the circuit device under test and having circuit components and associated circuit component terminals... Agent: Verigy

20070226554 - High-efficiency time-series archival system for telemetry signals: In one embodiment, a method and apparatus for high-efficiency time-series archiving for computer server telemetry signals is disclosed. The method includes selecting one or more telemetry signals of a plurality of telemetry signals by a sequential probability ratio test (SPRT) algorithm, the SPRT algorithm identifying the one or more telemetry... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20070226556 - Methods and systems for repairing an integrated circuit device: Provided are systems for repairing an integrated circuit device. The systems include detection logic configured to locate a defective portion of an integrated circuit device, a supplemental integrated circuit component configured to functionally replace the defective portion, and logic configured to identify an interface location. Also provided are methods for... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070226557 - Semiconductor integrated circuit and semiconductor integrated circuit device: An LSI chip has an internal logic, power supply control circuit and module control circuits, mounted thereon. External modules are provided outside the LSI chip. A power supply circuit for supplying power to the internal logic is composed of the module control circuits and external modules, that is, the power... Agent: Stanley P. Fisher Reed Smith LLP

20070226558 - Semiconductor integrated circuit device: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of... Agent: Miles & Stockbridge PC

20070226562 - Method and apparatus for secure scan testing: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan... Agent: Larson Newman Abel Polansky & White, LLP

20070226561 - Testing of data retention latches in circuit devices: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan... Agent: Larson Newman Abel Polansky & White, LLP

20070226563 - Test method and test device for testing an integrated circuit: A test method and a test device for testing an integrated circuit are configured to allow for a test device which dispenses with the hardware provision of the boundary scan cells in the device. For this purpose, the boundary scan cells are reproduced by way of a boundary scan program.... Agent: Lerner Greenberg Stemer LLP

20070226564 - Efficient scan chain insertion using broadcast scan for reduced bit collisions: Disclosed is a method of inserting scan elements onto scan chains of broadcast scan structures to minimize the number of collisions in a plurality of logic cones. Each logic cone is selected and evaluated to identify all of the scan elements that provide inputs thereto. The identified scan elements are... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070226565 - Semiconductor integrated circuit device and method of testing same: Disclosed is a circuit in which for conducting the scan path test, test clock terminals are provided in a number smaller than that of user clock domains, and a test clock control circuits on respective test clock lines to control whether the pulses of the test clock are propagated or... Agent: Sughrue Mion, PLLC

20070226566 - Iterative process for identifying systematics in data: An iterative process for identifying systematics in data is provided. In general, a set of data is processed based on a signature definition to create a set of signature data. The set of signature data is then analyzed to identify common signatures. The set of signature data is modified, using... Agent: Hoffman, Warnick & D'alessandro LLC

20070226567 - High speed bist utilizing clock multiplication: A system and method of performing high speed built-in self test (BIST) using clock multiplication. A system is provided for testing a high speed integrated circuit using a low speed tester, comprising: a built-in self test (BIST) engine coupled to the integrated circuit; a clock multiplier adapted to derive a... Agent: Hoffman, Warnick & D'alessandro LLC

20070226568 - Semiconductor integrated circuit and design apparatus thereof: According to the present invention, there is provided a semiconductor integrated circuit comprising: a logic circuit which operates upon receiving a clock; a logic built-in self test circuit which executes a built-in self test of said logic circuit, said logic built-in self test circuit having a pattern generator which generates... Agent: Amin, Turocy & Calvin, LLP

20070226569 - Film-type semiconductor package and method using test pads shared by output channels, and test device, semiconductor device and method using patterns shared by test channels: Provided are a film-type semiconductor package and method using test pads shared by output channels, a test device, and a semiconductor device and method using patterns shared by test channels. The semiconductor device includes a film-type semiconductor package and a test device. The film-type semiconductor package outputs test signals through... Agent: Mills & Onello LLP

20070226570 - Speeding up defect diagnosis techniques: Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test... Agent: Klarquist Sparkman, LLP

20070226571 - Protocol analyzer for consumer electronics: A protocol analyzer for analyzing traffic on a bus. A tap card is used to tap into a bidirectional bus. The tap provides a pass through connection from the card to the host and taps off of the bus. While tapping off the bus, stubs lengths are minimized and input... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070226573 - System on chip having test circuit: A system on chip processor, that is, a semiconductor integrated circuit in which a processor, a cache memory and the like are integrated into one chip, includes a test controller, and a trace memory. The test controller generates test control signals in response to test flag signals generated from a... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070226574 - Automated high voltage defibrillator tester: The present invention is directed to an automated high voltage (HV) defibrillator tester system that is able to asynchronously test a plurality of devices (e.g. defribillators etc.). The HV defibrillator tester system includes a first field programmable gate array (FPGA) connected to a set of tester modules. Each tester module... Agent: Medtronic, Inc.

20070226572 - Soft error rate analysis system: A method for improving reliability of an electronic system by evaluating a soft error rate is disclosed. A gate-level representation of the electronic system is converted to a graph, the graph having vertices and edges that correspond to nodes and gates of the electronic system. Input vectors are generated, which... Agent: Brinks Hofer Gilson & Lione

20070226576 - Channel sensing based on self-signal suppression: A method and apparatus for channel sensing in a wireless communication device is provided. A self-signal intentionally transmitted to a first wireless device by another wireless communication device is detected in a signal received by the first wireless device. An original self-signal transmitted by the second wireless device is reconstructed... Agent: Docket Clerk

20070226575 - Error correction scheme for a disc-playing system: The present invention discloses a player. The player comprises reading means, controlling means, sending means, receiving means and decoding means. The player according to the present invention acquires the original content corresponding to a missed or damaged portion required for correcting an error by being connected to the network, and... Agent: Philips Intellectual Property & Standards

20070226577 - Error control in multicast video distribution: An embodiment of the invention includes an efficient error-control system and method for recovering packet losses, especially losses in distributing multicast video over broadband residential networks. Preferably, unlike most existing error-control algorithms designed for Internet multicast, the system and method does not employ substantial feedback suppression. Preferably, the system and... Agent: Fish & Richardson, PC

20070226578 - Method and apparatus for providing reduced memory low density parity check (ldpc) codes: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without... Agent: The Directv Group Inc

20070226581 - Error codes for products: An example system and method for generating an error code involve detecting an error condition of a product and generating an error code by combining information indicative of the detected error condition with an identifier associated with, the product.... Agent: Nixon & Vanderhye, P.C.

20070226586 - Apparatus and method for receiving signal in a communication system: An apparatus and method is provided for receiving a signal in a communication system. The signal reception apparatus includes a receiver for receiving a signal, and a decoder for decoding the received signal according to a Low Density' Parity Check (LDPC) decoding scheme. The LDPC decoding scheme includes check node... Agent: The Farrell Law Firm, P.C.

20070226585 - Apparatus and method for receiving signal in communication system: Disclosed is an apparatus for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme, in which elements of a Galois field are expressed by an exponent representation, thereby minimizing the memory capacity required... Agent: The Farrell Law Firm, P.C.

20070226587 - Apparatus and method for receiving signal in communication system: Provided are an apparatus and a method for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a Low Density Parity Check (LDPC) decoding scheme in which the sequence of check node operations is scheduled, thereby improving the decoding performance of the... Agent: The Farrell Law Firm, P.C.

20070226583 - Apparatus and method for transmitting/receiving signal in a communication system: In a communication system, a signal transmission apparatus includes an encoder for encoding an information vector into a low density parity check (LDPC) codeword with an LDPC coding scheme, and a puncturer for puncturing the LDPC codeword according to a coding rate using a puncturing scheme. A signal reception apparatus... Agent: Dilworth & Barrese, LLP

20070226584 - Apparatus and method for transmitting/receiving signal in a communication system: A signal transmission/reception apparatus of a communication system. The signal transmission apparatus receives an information vector, encodes the information vector into a structured Low Density Parity Check (LDPC) codeword using a structured LDPC coding scheme, and transmits the generated structured LDPC code to the signal reception apparatus. Then the signal... Agent: The Farrell Law Firm, P.C.

20070226588 - Memory device and bit error detection method thereof: A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070226579 - Memory replay mechanism: Embodiments of the invention are generally directed to systems, methods, and apparatuses for memory replay mechanisms. In some embodiments, the replay logic includes reset logic to reset at least some of the links in a point-to-point memory interconnect. In addition, the replay logic may include a replay queue to store... Agent: Intel Corporation C/o Intellevate, LLC

20070226582 - Systems and methods for achieving higher coding rate using parity interleaving: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070226580 - Validating data using processor instructions: In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy... Agent: Trop Pruner & Hu, PC

20070226591 - Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit: An integrated device comprises a functional circuit, a test circuit for testing the functional circuit and for providing an error data item and a register element for storing the error data item and for outputting the error data item at an error data output of the integrated device responsive to... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070226590 - Semiconductor memory in which error correction is performed by on-chip error correction circuit: A synchronous semiconductor memory which performs a pipeline operation includes an error correction circuit, an output circuit, and first and second write circuits. The first write circuit is configured to overwrite at least a portion of externally input write data on data read out from a memory cell and corrected... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070226589 - System and method for error correction in cache units: A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first... Agent: Pearl Cohen Zedek Latzer, LLP

20070226592 - Variable sector-count ecc: Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices by increasing the data area of user data being covered by the ECC code. This averages any possible bit errors over a larger data area and allows a... Agent: Attn: Andrew C. Walseth Leffert Jay & Polglaze, P.A.

20070226593 - Performing multiple reed-solomon (rs) software error correction coding (ecc) galois field computations simultaneously: Performing multiple Reed-Solomon (RS) software error correction coding (ECC) Galois field computations simultaneously in a RISC processor. A novel apparatus and a novel method are presented by which multiple Galois field computations are performed in parallel thereby speeding up the decoding processing and enhancing performance. Processor, memory, and plurality of... Agent: Garlick Harrison & Markison

20070226594 - Error correcting decoding for convolutional and recursive systematic convolutional encoded sequences: The invention relates to error-correcting coding and correct restart of decoding after errors of sequences that are coded by convolutional coders or LFSR based descramblers. The signals can be binary or multi-valued signals. Methods and apparatus to convolutional encode and decode sequences of binary and n-valued symbols are disclosed. The... Agent: Glen M. Diehl Diehl Servilla LLC

20070226595 - Method for characterizing a bit detection event: A bit detection event within a read period is characterized by sub-dividing each read period into elementary time intervals. Certain ones of the elementary intervals are selected to for a window and a counting operation for a number of bits detected during the intervals within the window is performed. The... Agent: Jenkens & Gilchrist, PC

20070226596 - Apparatus and method for reduced power consumption communications over a physical interconnect: A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second... Agent: Intel Corporation C/o Intellevate, LLC

20070226597 - Semiconductor memory having embedded microcomputer with ecc function: There is provided a semiconductor device of which the circuit scale does not significantly increase even with an ECC function. A microcomputer having an internal flash memory inserts one weight in a sense amplifier activation signal only when an error detection signal is on the H level at a given... Agent: Miles & Stockbridge PC

20070226598 - Encoding and decoding methods and systems: An encoder for use in information processing applications includes an input configured to provide information bits to be encoded and a feedforward convolutional outer code encoder configured to encode the information bits to generate encoded information bits including the information bits and parity bits. The encoder may also include at... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070226599 - Symbol by symbol map detection for signals corrupted by colored and/or signal dependent noise: Symbol by symbol MAP detection for signals corrupted by colored and/or signal dependent noise. A novel means is presented for recursive calculation of forward metrics (α), backward metrics (β), and corresponding soft information (e.g., which can be provided as LLRs (log likelihood ratios)) within communication systems in which a trellis... Agent: Garlick Harrison & Markison

20070226601 - Method and system for generating parallel codes: A method for generating parallel codes is provided that includes generating a plurality of pairs of outputs for each clock cycle using a single code generator and generating a code based on each pair of outputs using the single code generator.... Agent: Docket Clerk

20070226600 - Semiconductor integrated circuit with flip-flops having increased reliability: A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops configured to latch input data in synchronization with a common clock... Agent: Arent Fox PLLC

20070226602 - Measuring device and method for measuring relative phase shifts of digital signals: K being a constant and Idx(i) corresponding to the number n which is either the first sampled value after a test signal zero crossing during the reference signal's ith period or the last sampled value before a test signal zero crossing during the reference signal's ith period. Either only rising... Agent: Baker Botts, L.L.P.

20070226603 - Method and system for indicating an executable as trojan horse: A method and system for indicating an executable as Trojan Horse, based on the CRC values of the routines of an executable. The method comprising a preliminary stage in which the CRC values of the routines of known Trojan Horses are gathered in a database, and a stage in which... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070220305 - Multiplex server system and server multiplexing method: A multiplex server system is provided for processing events from clients in accordance with a plurality of set rules, with the intention of reducing the cost of a computer system which comprises spare servers. In the multiplex server system, a plurality of servers are provided, and a primary server and... Agent: Young & Thompson

20070220315 - Data auto backup system and method: A data auto backup system and method is proposed, applicable in a computer system connected with an external storage device for backing up data of the external storage device to the computer system during a power-off state of the computer system. The computer system includes a bus interface, a storage... Agent: Ishimaru & Zahrt LLP

20070220323 - System and method for highly available data processing in cluster system: Provided is a method of managing an active server in a computer system. According to this method, the standby server receives, from one of the active servers, a request for registration of the active server, the request including information about the active server and information about a recovery program that... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070220327 - Dynamically controlled checkpoint timing: The timing of one or more checkpoints that are recorded during execution of a computer process may be controlled based at least in part on the amount of one or more computer resources that are being used by the computer process. Related programs, systems and processes are also set forth.... Agent: Mcdermott Will & Emery LLP

20070220337 - Microcomputer: A microcomputer includes: a memory; a CPU which decodes memory data stored in the memory to execute an instruction; a debug control section for instructing the microcomputer to perform a debug operation according to an instruction from an external debug instruction device which is connected to the microcomputer; and an... Agent: Mcdermott Will & Emery LLP

20070220336 - System and method for testing an integrated circuit: A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface is suggested, wherein the memory area is adapted to be written by the interface. The system includes a test device connected... Agent: Dicke, Billig & Czaja

20070220351 - Method and apparatus for testing execution flow of program: A method and apparatus for testing an execution flow of a program are provided. The method includes measuring the execution flow that reflects instruction values constituting the program and an execution order of the instructions; and verifying the measured execution flow.... Agent: Sughrue Mion, PLLC

20070220355 - Method for a checkpoint library to detect corruption by an application: A method of identifying the source of a memory corruption error during operation of a checkpoint library includes receiving an error detection request and, in response to the request, write protecting all memory regions allocated to a checkpoint library. The method further includes detecting when a memory region is accessed... Agent: Mcdermott Will & Emery LLP

20070220356 - Method for checkpointing a system already engaged in a concurrent checkpoint: Concurrent checkpointing for rollback recovery for system failures is disclosed. The system includes a stable database, and a processor configured to receive and process a checkpoint request while a first thread performs a process and a second thread stores contents of memory regions listed in a first list to the... Agent: Mcdermott Will & Emery LLP

20070220358 - Customer traffic forwarding continues while control plane is reset: A method and apparatus selectively resetting a control plane in a network element is described. One embodiment of the invention is a network element with a selective reset controller that can reset the control plane of the network element without interrupting the data traffic processing of the data plane of... Agent: Blakely Sokoloff Taylor & Zafman

20070220357 - Flow control methodology for digital retiming devices: A network diagnostic device or component such as a network analyzer or a jammer that is placed in-line between two nodes in a network to perform a flow control operation transparently without the requirement of a separate link layer implementation. The network diagnostic device may include a diagnostic module configured... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070220359 - Image forming apparatus: An image forming apparatus capable of executing a plurality of functions is provided with operating portion to which an operation instruction is inputted by an operator; display portion for displaying an operation guide to the operator; error detecting portion for detecting an occurrence of an operation error; and display controller... Agent: Casella & Hespos

20070220363 - Method and apparatus for rendering game assets in distributed systems: The invention includes a method and apparatus for attempting to synchronize delivery of information at a plurality of receiving systems. The method includes generating, at a sending system, a plurality of current messages adapted for rendering an asset within an application space of a respective plurality of receiving systems, determining... Agent: Patterson & Sheridan, LLP/ Lucent Technologies, Inc

20070220364 - Method for capturing a display frame of a computer crashing: A method for capturing a display frame of a computer crashing. When the computer crashes, the display frame of the computer crashing is captured and saved. Thus, users can analyze the reason for causing the computer crashing later.... Agent: Rabin & Berdo, PC

20070220373 - Method for performing a defective-area management in an optical media: The present invention discloses a method for performing a defective-area management adaptive to a slipping replacement algorithm in an optical media with segmented sector/blocks, by either keeping buffering a read user data of the sector/block to a buffer memory, regardless of the read sector/block is defective, or keeping buffering the... Agent: Madson & Austin Gateway Tower West

20070220298 - Method and apparatus for providing fault-tolerance in parallel-processing systems: A system that provides fault tolerance in a parallel processing system. During operation, the system executes a parallel computing application in parallel across a subset of computing nodes within the parallel processing system. During this process, the system monitors telemetry signals within the parallel processing system. The system analyzes the... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070220299 - Method and system for optimized instruction fetch to protect against soft and hard errors: A method of detecting error during transfer of instructions from a data memory to a computer processor. At the time of the commencement of transmission of the instructions, the raw data signal is checked for an error detection code indicating data corruption. If the error detection code indicates no data... Agent: Law Office Of Delio & Peterson, LLC.

20070220303 - Failure recovery system and server: A server 200 includes a scenario table in which object to-be-monitored information that indicates one or more network devices A, B and C being objects for failure recovery, failure information for identifying contents of failures, countermeasure information against failures, and frequence information that indicates the number of times of the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070220300 - Method and system for error correction utilized with a system for distribution of media: A method and system for correcting errors in a receiving system is disclosed. The method and system comprises analyzing and identifying errors in a media in the receiving system and communicating with a network center to download fixes to correct errors in the media.... Agent: Sawyer Law Group LLP

20070220301 - Remote access control management module: A method of operating a remote access control unit which comprises first and second units each having an Ethernet port for remotely controlling modules of a server system, comprises the steps of powering up the server system; initializing the first unit into master mode thereby establishing a remote access through... Agent: Baker Botts, LLP

20070220304 - Restoring a client device: Disclosed is a method of restoring a client device following failure of the client device, the client being connectable to a network comprising a server device. The method comprises saving to the server device a configuration state of the client device, the saved configuration state comprising client network interface configuration... Agent: Hewlett Packard Company

20070220302 - Session failover management in a high-availability server cluster environment: A system for session failover management in a server cluster environment, the system including one or more clusters, each cluster having one or more servers, each server having one or more partition, each partition identified by a partition ID and grouping one or more sessions, and a failover manager configured... Agent: Hoffman, Warnick & D'alessandro LLC

20070220306 - Method and system for identifying and recovering a file damaged by a hard drive failure: A method and system for identifying and recovering a file damaged by a hard drive failure. The method includes monitoring event logs, mapping at least one failing sector to at least one corresponding corrupted file if a hard drive failure is detected, and performing a selected remedial procedure based on... Agent: Lenovo (united States) Inc.

20070220307 - Storage system and control method thereof: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and... Agent: Stanley P. Fisher Reed Smith LLP

20070220308 - System and method for automatically restoring hard drives on failure: Systems and method for automatically restoring a hard drive after failure are provided. Disk recovery data may be collected and stored from an operational, online hard drive. When the hard drive subsequently fails, a client-specific recovery media may be generated, which may include a lightweight recovery environment. Restoration tasks may... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070220310 - Apparatus and methods for an appliance to synchronize with a storage device: Disclosed is a data recovery mechanism associated with a data writing process in a storage area network (SAN). In general, a data writing mechanism is provided so that a particular host can write data to a storage device in a particular SAN session. One specific example of a data writing... Agent: Beyer Weaver LLP

20070220312 - Apparatus, system, and method for switching a volume address association in a point-in-time copy relationship: An apparatus, system, and method are disclosed for switching a volume address association in a point-in-time copy relationship. A copy module creates a point-in-time copy structure of a source volume at a target volume. A migration module copies data from the source volume to the target volume. A detection module... Agent: Kunzler & Mckenzie

20070220314 - Backup/recovery system and methods regarding the same: A backup/recovery system and methodology that securely protects data in a computer system. According to the invention, in one embodiment of the invention, backup/recovery system is installed in the computer system. The backup/recovery system includes at least a backup unit, a storage means and a recovery unit. The backup unit... Agent: Arent Fox PLLC

20070220309 - Continuous data protection of block-level volumes: A continuous data protection system, and associated method, for point-in-time data recovery. The system includes a consistency group of data volumes. A support processor manages a journal of changes to the set of volumes and stores meta-data for the volumes. A storage processor processes write requests by: determining if the... Agent: Hogan & Hartson LLP

20070220311 - Cross tagging of data for consistent recovery: A system for consistent data recovery, including a storage area network (SAN) of initiator nodes and target nodes, wherein initiator nodes issue I/O requests and target nodes respond to I/O requests, the SAN being represented logically as a plurality of consistency groups of nodes, G1, . . . , Gn,... Agent: Blakely Sokoloff Taylor & Zafman

20070220316 - Method and apparatus for power-efficient high-capacity scalable storage system: Systems and methods for providing scalable, reliable, power-efficient, high-capacity data storage, wherein large numbers of closely packed data drives having corresponding metadata and parity volumes are individually powered on and off, depending upon their respective usage. In one embodiment, the invention is implemented in a RAID-type data storage system which... Agent: Trellis Intellectual Property Law Group, PC

20070220313 - Storage control device and data recovery method for storage control device: The present invention efficiently recovers an error drive by suppressing futile copying. When the number of errors of the disk drive is equal to or more than a first threshold, data stored in the disk drive is copied to a spare drive by a drive copy section. When the number... Agent: Stanley P. Fisher Reed Smith LLP

20070220317 - System and method for providing a software installation or removal status display: A method includes initiating an installation of software on a device or a removal of software from the device. The installation or removal of the software involves a plurality of installers capable of installing software components on or removing the software components from the device. The method also includes presenting... Agent: Honeywell International Inc.

20070220319 - Automatic classification of backup clients: A method of automatically classifying clients into different backup policy groups according to pre-selected criteria, such as type of client, whether the client is a server, a desktop or a mobile computer, the department or business unit, or even the user. The method uses information obtained from the client itself... Agent: Law Offices Of Barry N. Young

20070220320 - Managing backup solutions with light-weight storage nodes: A backup system in accordance with an implementation of the present invention includes one or more light-weight (i.e., stateless) storage nodes that are positioned close enough to one or more assigned production servers to enable as rapid and efficient a data recovery as possible. The one or more light-weight storage... Agent: Workman Nydegger/microsoft

20070220322 - Method for displaying pair state of copy pairs: The present invention is to provide a method for displaying a copy pair in which a distinction can be made between change of pair state performed intentionally by a user and change of pair state performed not intentionally by the user. When a backup instruction for PVOL is transmitted from... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070220321 - Method, apparatus and program product for a point-in-time recovery of a computing system: A method for detecting a failure in a computing system and for restoring the system is provided. The method comprises providing a system connected to a network communications channel, creating, using a configured backup automation tool, a full system backup image and incremental archive logs of the system before attempting... Agent: Silvy Anna Murphy

20070220318 - Spare device management: Provided are techniques for spare device management. Candidate devices are sorted into spare coverage groups by type. One or more candidate devices having closest fitting characteristics of a desired type are identified from the spare coverage groups. The identified one or more candidate devices are assigned to be spare devices... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37

20070220324 - Component indicators used during extended power-off service: A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power... Agent: Lily Neff IBM Corporation - Ms P386

20070220325 - Method for identifying power supply modules: A method for identifying power supply modules is adopted for use on a backup-type power supply system that includes real power supply modules and a dummy power supply module structured in a N+1 architecture to output power. By altering PG signal issue time and identifying PG signal delivery time difference... Agent: Birch Stewart Kolasch & Birch

20070220326 - Storage system and recovery method thereof: There is provided a storage system having a host computer for transmitting and receiving data, and a plurality of storage apparatus provided with volumes for storing the data sent by the host computer including a check point setting unit for setting check points as markers during recovery of each volume... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070220329 - Passenger transportation system especially an escalator or moving walk: A passenger transportation system, such as an escalator or moving walk, contains a circulating band, a driving station, and a reversing station. The driving station is arranged in the area of a first end of the passenger transportation system and has a slave control unit. The reversing station in the... Agent: Schweitzer Cornman Gross & Bondell LLP

20070220328 - Shutdown recovery: Aspects of the subject matter described herein relate to shutdown recovery for resource replication systems. In aspects, a mechanism is described in which a machine having replicated data thereon can recover from a dirty shutdown. First, the machine determines whether a dirty shutdown has occurred. If so, the machine automatically... Agent: Workman Nydegger/microsoft

20070220330 - Computer-supported diagnostic system, based on heuristics and system topologies: The invention relates to a computer-supported diagnostic system in which the physical structure of the technical system to be diagnosed is implemented in the form of a structural model. If a fault code occurs in a component of the technical system which is capable of self-diagnostics, and thus also in... Agent: Fitch, Even, Tabin & Flannery

20070220331 - Processor comprising an integrated debugging interface controlled by the processing unit of the processor: The systems and methods disclosed relate to a processor comprising a processing unit and a debugging interface which can be connected to an external emulator for debugging a program executed by the processor, the debugging interface comprising internal resources at least partially accessible to the external emulator. According to one... Agent: Seed Intellectual Property Law Group PLLC

20070220332 - Configurable error handling apparatus and methods to operate the same: Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the... Agent: Hanley, Flight & Zimmerman, LLC

20070220334 - Debugging system and method for use with software breakpoint: Methods and systems are provided for debugging a program executing on a processor. In a first implementation, a processing system includes a processor configured for switching to a debug mode from a non-debug mode upon executing a software breakpoint. The system may include a program memory configured to hold instructions... Agent: Fish & Richardson P.C.

20070220335 - Hardware function isolating during slow mode initial program loading: A computer implemented method, apparatus, and computer usable program code for performing a diagnostic in a hardware component established in a data processing system. The method includes starting a first slow mode initial program loading in the hardware component, wherein the hardware component contains a first diagnostic routine. A determination... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070220333 - Microcontroller information extraction system and method: A system for debugging a device under test may include a processor register with a program count and a debug program register that receives the program count upon execution of an instruction by a processor. In one implementation, a microcontroller under test by a debugger is accessed using a serial... Agent: Fish & Richardson P.C.

20070220342 - Devices systems and methods for testing software: Certain exemplary embodiments comprise a method comprising rendering a verdict indicative of whether a predetermined software system functions in a predetermined manner. The verdict can he determined based upon machine instructions, The machine instructions can be automatically generated via a module adapted to parse and/or load an Extensible Markup Language... Agent: Siemens Corporation Intellectual Property Department

20070220338 - Method and system for generating checkpoints of hardware description language simulations that include a specific model state together with a software testcase state: A method for performing verification is disclosed. In response to determining that a log replay module operating in a replay mode has received a command from a testcase that is not equal to a next command in a replay log, a determination is made whether the command is a create... Agent: Ibm Corporation

20070220341 - Software testing automation framework: Embodiments of the present invention address deficiencies of the art in respect to software test automation and provide a method, system and apparatus for a reusable software testing framework. In one embodiment of the invention, an automated application test data processing system can include a reusable test automation framework. The... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20070220339 - Testcase generation via a pool of parameter files: A current parameter file is periodically selected at random from an active pool, and testcases are generated and executed from the current parameter file against a device, where the execution of the testcases against the device hits events generated by the device over periods. A determination is made whether a... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070220340 - Using a genetic technique to optimize a regression model used for proactive fault monitoring: One embodiment of the present invention provides a system that optimizes a regression model which predicts a signal as a function of a set of available signals. During operation, the system receives training data for the set of available signals from a computer system during normal fault-free operation. The system... Agent: Sun Microsystems Inc. C/o Park, Vaughan & Fleming LLP

20070220343 - Kernel module compatibility validation: In one embodiment, a method and apparatus for high-efficiency time-series archiving for computer server telemetry signals are disclosed. The method includes maintaining a data structure in a kernel module that identifies information related to a system including the kernel module, the information to be manipulated by the kernel module, comparing,... Agent: Sun Microsystems, Inc. C/o Dorsey & Whitney, LLP

20070220344 - Generating a reliability analysis by identifying causal relationships between events in an event-based manufacturing system: Analyzing an event chronology record to permit identification of periods of a production sequence that correspond to a high probability of failure. Systems and methods include receiving an event chronology for a particular machine in the production sequence and for a particular time interval. A reliability analysis system accesses process... Agent: Senniger Powers (kcc)

20070220345 - System and method of analyzing timing effects of spatial distribution in circuits: Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the... Agent: Greenblum & Bernstein, P.L.C

20070220347 - Automatic testing for dynamic applications: Systems and methods for testing an application having a graphical user interface are disclosed. A function library having a plurality of functions is provided, each function corresponding to a user action within the graphical user interface. User actions within the graphical user interface are developed independent of the operation of... Agent: Mintz, Levin, Cohn, Ferris, Glovsky & Popeo, P.C.

20070220350 - Memory dump method, memory dump program and computer system: A technique for identifying a fundamental cause of a system fault in a system in which a plurality of OSs run on one computer. In a system in which each of a plurality of operating systems executes a process by time-sharing hardware of one computer, a plurality of related OSs... Agent: Mcdermott Will & Emery LLP

20070220346 - Method and apparatus for evaluating paths in a state machine: Methods and apparatus are provided for exploring paths through a graph representation of a program or another entity. According to one aspect of the invention, at least one property of a state machine, such as a graph representing a software program, is evaluated. One or more paths in the state... Agent: Ryan, Mason & Lewis, LLP

20070220348 - Method of isolating erroneous software program components: A computer implemented method, computer program product, and computer usable program code for preventing execution of program components having errors. First, a software application is executed. The software application interacts with a number of programs. Next, an error message is received. The error message indicates an error has occurred in... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070220349 - Software performance testing with minimum iterations: Systems and methods are disclosed for providing software performance testing. The results of a test may be determined valid if the test reached a defined test criteria after performing N number of iterations. If the test has not reached the defined test criteria and if N is less than a... Agent: Merchant & Gould (microsoft)

20070220353 - Managing and utilizing error information relating to image processing: Example embodiments of the present invention relate generally to an apparatus, method, system, computer program and product, each capable of managing error information relating to an image processing job requested by a user, and utilizing the error information to assist the user in performing the image processing job.... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070220352 - Method and apparatus for measuring signals in a semiconductor device: A method and apparatus for testing a semiconductor device captures a first set of digital data in internal memory and captures a second set of digital data in external memory. The first and second sets of collected digital data are time correlated. The time correlated data is presented simultaneously and... Agent: Agilent Technologies Inc.

20070220354 - Error correction device and method thereof: A device and method for error correction are disclosed. The device includes a memory control module to disable error processing for a memory location depending on the state of a status indicator. The status indicator can be set so that error processing is disabled when valid error correction and detection... Agent: Larson Newman Abel Polansky & White, LLP

20070220360 - Automated display of trace historical data: The intuitive display of trace historical data in a manner that processing control transfer between processing entities is represented in the context of trace data from multiple processing entities. For each processing entity, a set of one or more trace entries are identified for that processing entity and displayed in... Agent: Workman Nydegger/microsoft

20070220362 - Generation of trace elements within a data processing apparatus: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to... Agent: Nixon & Vanderhye, PC

20070220361 - Method and apparatus for guaranteeing memory bandwidth for trace data: The present invention provides a way to offload trace data from a processor and store the trace data in external memory. By accumulating trace data in large buffers and sending them to a memory interface controller, the memory interface controller may write trace data to memory as the memory interface... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070220365 - Method for avoiding repetition of user actions by using past users' experiences: A method for assisting a user to correct a problem with a device, such as a printer includes extracting, from records comprising user actions on the device, a string of user actions on the device. The string of user actions is compared with at least one predetermined sequence of user... Agent: Patrick R. Roche Fay, Sharpe, Fagan, Minnich & Mckee, LLP

20070220366 - Method and apparatus for preventing soft error accumulation in register arrays: A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater... Agent: Duke W. Yee

20070220368 - Data-centric monitoring method: Health management of machines and/or equipment, such as gas turbine engines, airplanes, and industrial equipment using a model centric method.... Agent: The Halvorson Law Firm

20070220369 - Fault isolation and availability mechanism for multi-processor system: A method and apparatus are provided for identifying a defective processor of a plurality of processors of a multi-processor system. In such method, a first command is submitted to a first processor and to a second processor within the multi-processor system. The first command is executed by each of the... Agent: International Business Machines Corporation

20070220367 - Fault tolerant computing system: A system for tolerating a single event fault in an electronic circuit is disclosed. The system includes a main processor that controls the operation of the system, a fault detection processor responsive to the main processor, and three or more programmable logic devices responsive to the fault detection processor. The... Agent: Honeywell International Inc.

20070220370 - Mechanism to generate functional test cases for service oriented architecture (soa) applications from errors encountered in development and runtime: A method for autonomically detecting and recreating exceptions occurring in a runtime environment during software development/testing. Dynamically-generated code of an exception detecting and recreating (EDR) utility is inserted into the application programming interface (API) entry points to the server to store method call parameter states by either cloning the objects... Agent: Ibm Corporation

20070220371 - Technique for mapping goal violations to anamolies within a system: A computer and method for problem detection and determination for automated system management in a system, wherein the method comprises monitoring system state, workload, and performance parameters of the system; comparing the monitored parameters against normal system performance behavior of the system, wherein the normal system performance behavior is maintained... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20070220372 - Microcode updating error handling apparatus and method thereof: A method of microcode updating error handling for an electronic device is disclosed. The method includes: providing a status flag to indicate if updating a renewable part of a microcode is complete, wherein the microcode comprises a non-renewable part having an updating error handling code; and detecting the status flag,... Agent: North America Intellectual Property Corporation

20070220374 - Rom data patch circuit, embedded system including the same and method of patching rom data: A read only memory (ROM) data patch circuit replaces ROM data stored in N modified ROM data blocks with patch data stored in N random access memory (RAM) patch blocks based on patch information. The ROM data patch circuit includes a data patch detecting unit, a RAM address generating unit,... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070220375 - Methods and apparatus for a software process monitor: A process monitor is configured to monitor the state of a number of software processes through the use of regular “heartbeat” messages sent by those processes. In the event that expected heartbeats are not received, or are received at unexpected intervals, the process monitor decides what action to take—e.g., whether... Agent: Ingrassia Fisher & Lorenz, P.C.

20070220376 - Virtualization system and failure correction method: Proposed is a virtualization system and failure correction method capable of improving the operating efficiency of maintenance work. This virtualization system has one or more storage apparatuses, and a virtualization apparatus for virtualizing a storage extent provided respectively by each of the storage apparatuses and providing the storage extent to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070220377 - Interleaving apparatus and method in communication system: Provided are an interleaving apparatus and method in a communication system. The interleaving apparatus includes a determiner for determining whether a next index k to be generated is an index to be discarded, and if the next index k is the index to be discarded, generating a skip signal; an... Agent: The Farrell Law Firm, P.C.

20070220379 - Memory device fail summary data reduction for improved redundancy analysis: A method and apparatus is presented for extracting sparse failure information from an error data image of a memory device by scanning the error data image in only two passes. During a first scan pass, the error data image is scanned for failures in a first set of memory cell... Agent: Verigy

20070220378 - Method and apparatus for testing data steering logic for data storage having independently addressable subunits: Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to... Agent: Qualcomm Incorporated

20070220381 - Enhanced diagnosis with limited failure cycles: Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of... Agent: Klarquist Sparkman, LLP

20070220380 - Message system for logical synchronization of multiple tester chips: A message system for logically synchronizing a large number of tester chips includes a message pipeline for multiple sets of tester chips. Each set of tester chips includes a delay unit through which messages are communicated to the message pipeline from the set of tester chips and from the message... Agent: Credance C/o Murabito Hao Barnes, LLP

20070220384 - Isolating the location of defects in scan chains: Techniques for isolating defects in scan chains are disclosed. Diagnostics fault simulation is performed on chosen faults that are consistent with the nature of a scan chain defect, while keeping information about the failures that each fault predicts. Once this information is available, the effects of defects at specific locations... Agent: Orrick, Herrington & Sutcliffe, LLPIPProsecution Department

20070220382 - Negative edge flip-flops for muxscan and edge clock compatible lssd: A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to... Agent: Schmeiser, Olsen & Watts

20070220385 - Semiconductor device provided with function for screening test regarding operating speed: A semiconductor device includes one or more margin detecting circuits, each of which includes a first flip-flop having a first clock signal input node coupled to a clock supply node and a first data input node coupled to a data supply node, a second flip-flop having a second clock signal... Agent: Arent Fox PLLC

20070220383 - Systems and methods for identifying errors in lbist testing: Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment, an LBIST controller enables continuous execution of LBIST test cycles (including functional and scan shift phases) prior to... Agent: Law Offices Of Mark L. Berrier

20070220386 - Verification of the design of an integrated circuit background: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations... Agent: Ibm Microelectronics Intellectual Property Law

20070220388 - Apparatus and method for adjusting an operating parameter of an integrated circuit: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter... Agent: Freescale Semiconductor, Inc. Law Department

20070220387 - Method and apparatus for determining which timing sets to pre-load into the pin electronics of a circuit test system, and for pre-loading or storing said timing sets: In one embodiment, a method includes, providing a test program designed to control a circuit test system. The circuit test system has a plurality of test channels, each test channel of which is configured to be selectively coupled to a plurality of sub-channels under control of the test program. The... Agent: Verigy

20070220389 - Integrated circuit device, diagnosis method and diagnosis circuit for the same: A logical circuit 18 and a self-diagnosis circuit 22 are mounted on an LSI 10. When a test program is loaded to a RAM 28 and a diagnosis command is input to a CPU 26 before shipment, a pattern generation circuit 24 generates a pattern and expected value pattern data... Agent: Stanley P. Fisher Reed Smith LLP

20070220390 - Method and system for verifying equivalence of two representations of a stimulus pattern for testing a design: A method for verifying the equivalence of two representations of a stimulus pattern for testing a design is disclosed. The method includes receiving a base pattern file representing the stimulus pattern in a first file format. A derivative pattern file in a second file format is generated from the base... Agent: Ibm Corporation

20070220391 - Integrated circuit with scan-based debugging and debugging method thereof: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070220392 - Method and apparatus for automatic generation of system test libraries: The present invention provides an apparatus to generate system test libraries for solution testing involving heterogeneous devices from different vendors. It provides a unified user interface, which can use the information input by the user to execute the tests based on provided device and network topology libraries to generate the... Agent: Rajeev Madnawat Tm Patent Group

20070220393 - Transmitting data words: There is provided a method of transmitting data words. The method includes (a) scrambling a first occurrence of a data word to produce a first scrambled data word, (b) block encoding the first scrambled data word to produce a first code word, (c) scrambling a second occurrence of the data... Agent: Hewlett-packard Co. Intellectual Property Administration

20070220394 - Low-complexity and low-power-consumption turbo decoder with variable scaling factor: Provided is a low-complexity and low-power-consumption turbo decoder with a variable scaling factor. The performance of the turbo decoder is enhanced by evaluating a decoding convergence degree of the turbo decoder using a sign difference ratio (SDR) value, limiting the iterative-decoding number, and calculating and applying a variable scaling factor... Agent: Ladas & Parry LLP

20070220396 - Error correction code striping: A method is disclosed which decreases the amount of error correction code data required to detect and correct errors in digital data while still maintaining a specified ability to correct errors in large groups of contiguous data. The present invention accomplishes this by placing distance either in space or in... Agent: Powell And Associates

20070220398 - Ldpc decoding apparatus and method based on node memory: An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs... Agent: The Farrell Law Firm, P.C.

20070220399 - Low density parity check code-based hybrid automatic repeat request method: A transmission method based on a Hybrid Automatic Repeat Request (HARQ) scheme for in a communication system. A codeword is generated using a Low Density Parity Check (LDPC) code. Parity bits of the codeword are classified on a basis of a transmission priority. Parity bits with an identical transmission priority... Agent: The Farrell Law Firm, P.C.

20070220395 - Method and apparatus for encoding and decoding data: A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part... Agent: Motorola, Inc.

20070220397 - Method for transmitting/receiving signals in a communications system and an apparatus therefor: A method for transmitting a signal in a signal transmission apparatus of a communications system including receiving an information vector, and encoding the information vector according to a zigzag B-LDPC encoding scheme to generate a zigzag B-LDPC codeword, thereby advantageously reducing the encoding complexity together with enhanced error correction capability.... Agent: The Farrell Law Firm, P.C.

20070220400 - Semiconductor memory device: A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circuit includes first and second operation parts for performing addition/subtraction with modulo M and modulo N... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070220402 - Auxiliary storage device and read/write method: Embodiments in accordance with the present invention provide an auxiliary storage device that prevents performance degradation and collects data useful for buffer failure analysis. In one embodiment, a data set including user data and cyclic redundancy check (CRC) information is temporarily stored in a buffer. If a CRC error is... Agent: Townsend And Townsend And Crew LLP

20070220401 - Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode: Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type in an error check mode and a non-error check mode. In some embodiments, a memory device includes at least one split bank pair of memory banks. If the memory device is in... Agent: Intel Corporation C/o Intellevate, LLC

20070220404 - Ip-data transmitting apparatus and ip-data transmitting method: An IP-data transmitting apparatus performs an error correction coding by classifying data into a layer indicative of the priority order of the data based on importance and vulnerability of inf