Error detection/correction and fault detection/recovery inventions 06/07

20070150772 - Systems and methods for hazards analysis: A system for hazards analysis includes: a memory device for storing a program; a processor in communication with the memory device, the processor operative with the program to: access the memory device to obtain information specifying a system to be analyzed; build functional block diagrams using the information specifying the... Agent: Siemens Corporation Intellectual Property Department

20070150773 - Extensions to sip signaling to indicate spam: SIP signaling may be used to indicate the presence of SPAM on a multimedia network. A new SIP method type, SIP header, extension to an existing header, SIP error code or SDP message, may all be used to indicate that the session is related to SPAM or to communicate the... Agent: John C. Gorecki, Esq.

20070150774 - Maintaining data integrity in a data storage system: A method of recovering data on a storage medium is provided. A first error correction scheme is performed on a high risk region of the storage medium. A second error correction scheme is performed on a remaining portion of the storage medium.... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.

20070150775 - Apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system: Provided is an apparatus and method for controlling an interleaver/deinterleaver memory in a mobile communication system are provided. In particular, an apparatus and method are provided which can reduce unnecessary time and power consumption by eliminating an unnecessary memory erasure. A write address generator generates write addresses. A memory stores... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070150776 - Qualified anomaly detection: A circuit and method of qualified anomaly detection provides detection and triggering on specific analog anomalies and/or digital data within a qualified area of a serial data stream. A start pattern within the serial data stream, such as a packet header, is detected to generate an enable signal. A stop... Agent: Thomas F. Lenihan Tektronix, Inc.

20070150777 - Memory test circuit and method: A memory test circuit according to an embodiment of the invention executes a test on a memory in accordance with a pattern mode signal designating a sub-test pattern included in a test pattern and including a plurality of test actions for the memory, and stores the pattern mode signal as... Agent: Foley And Lardner LLP Suite 500

20070150778 - Lithographic apparatus and device manufacturing method: Apparatus and methods for compensating for the movement of a substrate in a lithographic apparatus during a pulse of radiation include providing a pivotable mirror configured to move a patterned projection beam incident on the substrate in synchronism with the substrate.... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070150779 - Lithographic apparatus and device manufacturing method: Apparatus and methods for compensating for the movement of a substrate in a lithographic apparatus during a pulse of radiation include providing a pivotable mirror configured to move a patterned radiation beam incident on the substrate in substantial synchronism with the substrate.... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070150781 - Apparatus with programmable scan chains for multiple chip modules and method for programming the same: An apparatus provided with programmable scan chains includes a scan chain having a scan input port and a scan output port, a plurality of first I/O ports, an input port selector for selecting one of the plurality of first I/O ports to be coupled to the scan input port, a... Agent: Paul, Hastings, Janofsky & Walker LLP

20070150780 - Semiconductor integrated circuit and method for controlling the same: A semiconductor integrated circuit includes a target circuit with at least a scan chain having sub scan chains of stages to sequentially shift a test data in response to a clock signal in a scan path test mode, and each of the sub scan chains includes first flip-flops connected in... Agent: Mcginn Intellectual Property Law Group, PLLC

20070150782 - Method and apparatus for affecting a portion of an integrated circuit: In one embodiment, an integrated circuit which uses one or more re-useable modules may use a signature generated by a duplicate state machine or an unmodified state machine to select, control, or otherwise affect a resource on the integrated circuit, where affecting the resource was not part of the original... Agent: Freescale Semiconductor, Inc. Law Department

20070150783 - Methods and apparatus to abstract events in software applications or services: According to some embodiments, a system may be monitored to detect change events. A sequence associated with the detected change events may then be stored. The sequence may then be modified by deleting information associated with a detected change event. The sequence might also (or instead) be modified by adding... Agent: Siemens Corporation Intellectual Property Department

20070150785 - Data-processing system for measurement devices: The present invention provides a data-processing system for measurement devices, which performs a step-by-step sequence of data-processing tasks. In a conventional data-processing system, a failure in one data-processing task also causes the subsequent tasks to be unsuccessful. In such a case, the conventional data-processing system indicates the result of each... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070150784 - Method and system for data and video coding: The invention provides a video coding method. The method may include: receiving a set of video data for transmission; identifying at least two partitions from the video data, a first partition containing at least a portion of decoding information enabling a decoding of the video data, and a second partition... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070150786 - Method for coding, method for decoding, device for coding and device for decoding video data: The invention relates to a method and a device for coding video data comprising means for coding the pictures in data groups. According to the invention, the device comprises means for inserting, into the coded data groups, a message comprising parameters originating from the coding of the said group and... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070150787 - Apparatus and method for transmitting/receiving high speed shared control channel in wideband wireless communication system: Provided is an apparatus and method for transmitting/receiving an HS-SCCH in a wideband wireless communication system. In a method for transmitting control information in an HARQ wireless communication system, an ACK/NACK fed back from a receiver is monitored to determine if an ACK/NACK repetition factor needs to be adjusted. If... Agent: The Farrell Law Firm, P.C.

20070150788 - Acknowledgement signaling for automatic repeat request mechanisms in wireless networks: The present invention purposes an enhanced acknowledgment/non-acknowledgment signaling applicable to automatic repeat request mechanisms. The automatic repeat request (ARQ) mechanisms is operable with a sender of data packets. The signaling comprises a number of ACK/NACK messages, which are dedicated to be transmitted on a time-multiplexed channel, which is partitioned into... Agent: Alston & Bird LLP

20070150789 - Ldpc decoding apparatus and method using type-classified index: Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing... Agent: Blakely Sokoloff Taylor & Zafman

20070150792 - Memory module comprising a plurality of memory devices: A memory module stores data in the form of code words, each code word comprising useful bits and check bits for error correction. The memory module contains a first group of the memory devices including check bits and a second group of the memory devices including useful bits, the second... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070150790 - Method of storing downloadable firmware on bulk media: A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and the parity data is stored with the portions of data, the corrupted data may be reconstructed from the parity data and... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070150791 - Storing downloadable firmware on bulk media: A portion of data stored in a non-volatile memory may be found to be corrupted when it is read. Where parity data is generated from portions of data and the parity data is stored with the portions of data, the corrupted data may be reconstructed from the parity data and... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070150793 - Rewrite strategy and methods and systems for error correction in high-density recording: Strategy and methodology by which the various error sources are taken into account and methods applied to compensate substantially entirely for such errors and/or diminish the effect of such errors.... Agent: Burns & Levinson, LLP

20070150796 - Decoding method for detecting plsc from frames of satellite broadcasting system: Provided is a decoding method for detecting Physical Layer Signaling Codes (PLSCs) from frames of a satellite broadcasting system. The method includes: a) acquiring a summation vector and a subtraction vector from an inputted symbol vector; b) performing parallel Reed-Muller (32,6) decoding onto the summation and subtraction vectors based on... Agent: Blakely Sokoloff Taylor & Zafman

20070150794 - Error correction using finite fields of odd characteristic on binary hardware: Binary data representing a code word of an error-correcting code is used for calculating a syndrome, wherein a given portion of the binary data comprises k groups of data bits and represents a field element of the finite field GF(pk), p being an odd prime number, the field element comprising... Agent: Ericsson Inc.

20070150797 - Partial iterative detection and decoding apparatus and method in mimo system: A partial iterative detection and decoding apparatus in a Multiple Input Multiple Output (MIMO) system includes a detector for detecting signals received through at least one receive antenna to generate a first soft decision value, a decoder for decoding the first soft decision value to generate a second soft decision... Agent: The Farrell Law Firm, P.C.

20070150795 - Performing a cyclic redundancy checksum operation responsive to a user-level instruction: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself... Agent: Trop Pruner & Hu, PC

20070150798 - Method for decoding an ecc block and related apparatus: A method for decoding an error correction code (ECC) block includes: providing a plurality of flags, wherein each flag is utilized to label at least one codeword of the ECC block as an error-free codeword; and detecting whether a flag corresponding to a specific codeword is asserted, and skipping calculating... Agent: North America Intellectual Property Corporation

20070150799 - Robust erasure detection and erasure-rate-based closed loop power control: Techniques for performing erasure detection and power control for a transmission without error detection coding are described. For erasure detection, a transmitter transmits codewords via a wireless channel. A receiver computes a metric for each received codeword, compares the computed metric against an erasure threshold, and declares the received codeword... Agent: Qualcomm Incorporated Patent Department

20070143643 - Testing radio frequency and analogue circuits: A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped up (step 100) and quiescent current measurements are taken at selected values of VDD (step 102) to generate a current signature (step 104). When the power supply is ramped up, all transistors in... Agent: Philips Intellectual Property & Standards

20070143644 - Dynamic determination of signal quality in a digital system: A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (Vref—test)... Agent: Ibm Corporation (syl-rps)

20070143645 - Gpon rogue-onu detector: A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a global error-counter, coupled to the OLT, for counting FEC-correctable errors, for each ONU, from a data stream from the GPON; and a CPU for extracting an ONU status, indicative of a... Agent: Dr. Mark Friedman Ltd. C/o Bill Polkinghorn

20070143646 - Tolerating memory errors by hot-ejecting portions of memory: In an information handling system, when a memory location is accessed and there is a bit error detected in that memory location then the memory location is logged into an error-log. The memory locations of the logged bit errors stored in the error-log are evaluated to determine whether there is... Agent: Baker Botts, LLP

20070143650 - Mechanism for read-only memory built-in self-test: In one embodiment, a method for on-die read only memory (ROM) built-in self-test (BIST) is disclosed. The method comprises testing odd word line entries of a read-only memory (ROM) array by performing two passes through the ROM array to test each odd word line entry for static and delay faults,... Agent: Blakely Sokoloff Taylor & Zafman

20070143648 - Memory timing model with back-annotating: A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each... Agent: Lsi Logic Corporation Timothy R. Croll

20070143647 - Pulsed flop with scan circuitry: In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070143649 - Test patterns to insure read signal integrity for high speed ddr dram: A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arranged within a data... Agent: Stephen B. Ackerman

20070143652 - Test circuit for semiconductor integrated circuit: The present invention provides a test circuit for a semiconductor integrated circuit that can be used for testing plural of logic blocks each having plural input-output terminals. This test circuit is provided with scanning flip-flop (SFF) circuits whose output terminals are connected to the input terminals of the logic blocks.... Agent: Nixon Peabody, LLP

20070143651 - Systems and methods for providing output data in an lbist system having a limited number of output ports: Systems and methods for performing logic tests in digital circuits with means for segmentation and output of data through limited I/O ports. In one embodiment, a system includes test circuitry coupled to target logic under test, where the test circuitry is configured to perform logic tests on the target logic... Agent: Law Offices Of Mark L. Berrier

20070143653 - Reduced pin count scan chain implementation: The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal;... Agent: Texas Instruments Incorporated

20070143657 - Encoder, decoder, methods of encoding and decoding: An information sequence having a code length of N (N=K+M), where K is information length and M is parity length, is encoded into a code sequence by using an LDPC code. The LDPC code is generated based on a matrix H, with M rows and N columns. The matrix H... Agent: Patrick G. Burns, Esq. Greer, Burns & Crain, Ltd.

20070143656 - Ldpc concatenation rules for ieee 802.11n system with packets length specified in octets: An improved LDPC encoding with concatenation rule and code size with packet lengths specified in octets is provided. The LDPC block size is selected to be an integer number of OFDM tones. The concatenation rule is an improvement of the shortening and puncturing scheme for low data rate. The improvement... Agent: Myers Dawes Andras & Sherman, LLP

20070143655 - Ldpc concatenation rules for ieee 802.11n system with packets length specified in ofdm symbols: A method of concatenation for LDPC encoding in an OFDM wireless system selects codewords based on the data packet payload size, wherein the payload size is the number of transmitted information bits in octets. For low transmission rates, shortening and puncturing across all codewords within the packet is applied to... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20070143654 - Method and apparatus for using long forward error correcting codes in a content distribution system: Method and apparatus for using long FEC codes in a content distribution system is described. One aspect of the invention relates to encoding frames of content. Each frame is partitioned into un-coded bits and bits to be encoded. For each frame, an FEC code is applied to the bits to... Agent: General Instrument Corporation Dba The Connected Home Solutions Business Of Motorola, Inc.

20070143659 - Error correction algorithm using interleaved parity check and reed-solomon code: Methods and apparatuses for correcting errors in a data stream are described herein. In one aspect, the error correction process is operable to correct errors in at least two separate types of data streams, each of which utilizes a distinct error correction scheme. The error correction process utilizes Reed-Solomon code... Agent: Morrison & Foerster LLP

20070143658 - System and method for aligning a quadrature encoder and establishing a decoder processing speed: A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of an encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying... Agent: Agilent Technologies Inc.

20070136622 - Auditing system and method: A method and system for auditing information technology used to handle financial statement accounts to secure sensitive financial information against the exploitation of vulnerabilities and ineffective configuration standards. By working with the client organization, an audit team evaluates the way the client organization controls sensitive IT systems. The audit team... Agent: Baker Botts L.L.P.

20070136623 - Memory controller and method for operating a memory controller having an integrated bit error rate circuit: A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and... Agent: Deniro/rambus

20070136624 - Failure recovering method and recording apparatus: A bad sector is detected by activating a bad sector detecting function of a recording apparatus at a predetermined interval. The bad sector is recovered, when the bad sector is detected at the detecting, by overwriting data on the bad sector with a duplication of the data, and when overwriting... Agent: Greer, Burns & Crain

20070136626 - Storage efficient memory system with integrated bist function: A method and system is disclosed for conducting built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result module, the built-in-self-test is conducted for the circuit under test without testing the test... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20070136627 - System and method for testing write strobe timing margins in memory devices: Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a transmitter uses the transmitter clock signals to transmit a write data strobe signal... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070136625 - Test apparatus and test method: There is provided a test apparatus for testing a memory-under-test for storing data strings to which an error correcting code has been added, having a logical comparator for comparing each data contained in the data string read out of the memory-under-test with an expected value generated in advance, a data... Agent: Osha Liang L.L.P.

20070136628 - Testing apparatus and testing method: There is provided a testing apparatus for testing a memory-under-test, having a pin electronics section for inputting/receiving signals to/from the memory-under-test, a pattern generating section for inputting a test pattern to the memory-under-test via the pin electronics section and a judging section for receiving an output signal of the memory-under-test... Agent: Osha Liang L.L.P.

20070136629 - Method for testing semiconductor integrated circuit and method for verifying design rules: Not only defects in DC characteristics and a degeneracy fault but defects in AC characteristics such as SI faults (a crosstalk faults and an IR-DROP fault) and a delay fault, which tend to increase as design rules become finer in recent years, are detected as a measure used when the... Agent: Stevens, Davis, Miller & Mosher, LLP

20070136630 - Semiconductor test system and method: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared... Agent: Texas Instruments Incorporated

20070136631 - Method and system for testing backplanes utilizing a boundary scan protocol: A system is provided for testing connectivity of a backplane having card slots with multiple nets in each card slot. The system includes a processor module that generates test vectors based on a net connectivity configuration for a predetermined backplane architecture. A master control card includes a card slot interconnect... Agent: The Small Patent Law Group LLP

20070136632 - General-purpose procedure input circuit: A general-purpose procedure input circuit receives a procedure input signal and at least one control signal. The general-purpose procedure input circuit includes a multiplexer, a signal attenuator and a ground circuit. The multiplexer includes a plurality of channels and receives the control signal to control one of the channels. The... Agent: Hdsl

20070136633 - Codeword automatic repeat request/decoding method and transmission/reception apparatus using feedback information: A codeword retransmission/decoding method and transmission/receiving apparatus uses feedback information. When a failure to decode data received from a receiving node occurs, the feedback information including success/failure information of the decoding and retransmission information are transmitted to a transmission node. The retransmission success probability may be increased when the retransmission... Agent: Lowe Hauptman Berner, LLP

20070136634 - Reception apparatus and reception method: When a determination section of a reception apparatus determines that a control channel is intended for the reception apparatus, a comparing section of the reception apparatus compares control information transmitted on the control channel with a reception capability of the reception apparatus. A data channel reception section of the reception... Agent: Stevens, Davis, Miller & Mosher, LLP

20070136636 - Data encoding method for error correction: A data encoding method for error correction is provided. Before recording data into a recording media, the data are added with an Error Correction Code (ECC) comprising Check Sum on Row (CSR) and Check Sum on Column (CSC), thereby forming an ECC block. More than one ECC block are integrated... Agent: Morris Manning Martin LLP

20070136635 - Method of generating structured irregular low density parity checkcodes for wireless systems: A method of generating structured irregular LDPC codes for a wireless network such as a wireless local area network (WLAN) system, allowing systematic generation of improved code ensembles using density evolution, and providing essentially the best tradeoff between decoding threshold and decoding complexity. Such an LDPC code has a higher... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20070136637 - Device and method for correcting a data error in communication path: There are provided a transmission and reception device having a function for correcting a data error in a communication path. In the transmission device, a redundant bit addition unit adds a redundant bit to each data bit which has been divided by one bit by a division unit; and an... Agent: Eric Robinson

20070136638 - System and method for checking and correcting bios errors: A system for checking and correcting BIOS errors is provided. The system includes a program loading module (1001) for loading main programs from a BIOS ROM into a RAM; a checksum calculating module (1002) for reading the original checksum, and for calculating a new checksum for the main programs loaded... Agent: North America Intellectual Property Corporation

20070136640 - Defect detection and repair in an embedded random access memory: An integrated circuit comprises a volatile memory array, a non-volatile memory array, a plurality of registers, and a plurality of flip-flops. A portion of the non-volatile memory array is used for storing an address of a defective memory cell of the volatile memory array. The plurality of registers is coupled... Agent: Freescale Semiconductor, Inc. Law Department

20070136639 - Method for adapting a memory system to operate with a legacy host originally designed to operate with a different memory system: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device.... Agent: Parsons Hsue & De Runtz, LLP - Sandisk Corporation

20070136641 - Unified memory architecture for recording applications: An apparatus comprising a first circuit configured to (i) extract video data as data blocks from an input signal and (ii) perform error correction on said data blocks with a delta syndrome based iterative Reed-Solomon decoding, a second circuit configured (i) to decode said video data into a video format... Agent: Lsi Logic Corporation

20070136642 - Conditional access to store content using non-standard media: A data carrier with at least one data recording area (2, 6) in which data recording area data are stored in accordance with a predefined data recording standard, comprises at least one defective area (3, 7) in the data recording area (2, 6), which defective area is designed in such... Agent: Philips Intellectual Property & Standards

20070136643 - Digital television transmitter/receiver and method of processing data in digital television transmitter/receiver: A digital television (DTV) transmitter/receiver and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded enhanced data. A data formatter generates enhanced data packets... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20070136644 - Decoding device for decoding codeword: According to one embodiment, a decoding device decodes a (k+m) bit codeword in accordance with a check matrix. The codeword includes k-bit information symbols and an m-bit parity check code. The check matrix includes a unit matrix and a coefficient matrix. The most significant bit of each of a second... Agent: Pillsbury Winthrop Shaw Pittman, LLP

20070136645 - Error correction devices and correction methods: An error correction device is provided. When an error of a data group stored in a dynamic random access memory (DRAM) device is detected, a memory controller of the error correction device executes a burst read and write, burst write or burst read-modify-write (RMW) operations to the DRAM instead of... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070136647 - Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method: An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070136646 - Error correction device, error correction program and error correction method: An error correction device, an error correction program and an error correction method can reduce the processing time necessary for the process of correcting errors that involve erasure in a reception word by using a software and hardware properly and effectively. As an error-correcting circuit 3a for correcting errors that... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.

20070136649 - Apparatus and method for computing llr: Provided are an apparatus and method for efficiently computing a log likelihood ratio (LLR) using the maximum a posteriori (MAP) algorithm known as block combining. The method includes the steps of: calculating alpha values, beta values and gamma values of at least two time sections; calculating transition probabilities of respective... Agent: Blakely Sokoloff Taylor & Zafman

20070136648 - Iterative decoding receiver reducing complexity of partial sphere decoding in spatial multiplexing system and method thereof: The present invention relates to an iterative decoding receiver for reducing complexity of a partial sphere decoding operation in a spatial multiplexing system, and a method thereof. In the present invention, an iterative detection and decoding (IDD) method using a cost function-based iterative partial sphere decoding method and a soft... Agent: Mayer, Brown, Rowe & Maw LLP

20070130487 - Processing of an interruption to a communication connection between a domestic appliance and a controller in a local network: A method and a device determine an interruption state of a communication connection between a domestic appliance and a controller. The communication connection is between the domestic appliance, optionally connected in a local area network to further domestic appliances, to a bus line configuration, including a bus line controller, by... Agent: Lerner Greenberg Stemer LLP

20070130488 - Semiconductor device and data storage apparatus: A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to... Agent: Rader Fishman & Grauer PLLC

20070130489 - Systems and methods for lbist testing using isolatable scan chains: Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits, where boundary scan chains in functional blocks of the circuits can be selectively coupled/decoupled to isolate the functional blocks during LBIST testing. In one embodiment, processor cores of a multiprocessor chip are isolated and LBIST testing is performed... Agent: Law Offices Of Mark L. Berrier

20070130490 - Information protection using properties of a printed electronic circuit: Apparatus and methods for manufacturing and reading the apparatus is disclosed. The apparatus includes: a storage medium (610) comprising a first material; and a printed electronic circuit (104) coupled to the storage medium, the printed electronic circuit comprising a first portion (206) that includes a plurality of printed electronic circuit... Agent: Motorola, Inc.

20070130491 - Error detection of digital logic circuits using hierarchical neural networks: An artificial neural network for detecting and identifying errors in digital circuits is provided. Data from digital circuits are received and organized into current data set patterns by a supervisory control and data acquisition system. The supervisory control and data acquisition system transmits the current data set patterns to an... Agent: Duke W. Yee Yee & Associates, P.C.

20070130492 - Testable design methodology for clock domain crossing: A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals traversing from one clock domain to another clock domain across a synchronization circuit. The register is programmed with a latency value that corresponds... Agent: Garlick Harrison & Markison

20070130493 - Feedback and frame synchronization between media encoders and decoders: Feedback and frame synchronization between media encoders and decoders is described. More particularly, the encoder can encode frames that are based on source content to be sent to the decoder. The encoder can determine whether the frame should be cached by the encoder and the decoder. If the frame is... Agent: Lee & Hayes PLLC

20070130494 - Serial turbo trellis coded modulation using a serially concatenated coder: Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070130495 - Apparatus and method of multi-cyclic redundancy checking for section detection and reliability information acquisition in a dvb-h system: A method and apparatus of multi-Cyclic Redundancy Checking (CRC) are provided for section detection and reliability information acquisition in a Digital Video Broadcasting-Handheld (DVB-H) system. A Packet Identifier (PID) filtering process is performed for a packet received through a radio network. A transport stream packet including section data is detected.... Agent: The Farrell Law Firm, P.C.

20070130496 - Apparatus, method and computer program product for reading information stored in storage medium, and storage medium for storing information based on charge amount: A reproducing apparatus includes a storage unit including a plurality of memory elements each capable of holding an electric charge, each memory element indicating a 2-bit code which is related to each other so that the Hamming distance between adjacent codes is unity in four ranges determined by a charge... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070130497 - Adaptive decoder for decoding an asynchronous data stream: A data decoder for decoding an asynchronous incoming data stream includes a bit engine receiving information describing the incoming data stream and generating a decoded data stream. In one embodiment, the bit engine includes a best-fit bit analysis block performing a pattern match operation for each data bit of the... Agent: Patent Law Group LLP