Error detection/correction and fault detection/recovery inventions 05/07

20070124624 - Impulse noise mitigation: In a signal transmission medium such as an ac power line, impulse noise in the line may be dealt with by detecting impulse noise in the transmission medium, determining whether the impulse noise is periodic or complex, and, at least approximately, correlating the time at which periodic impulse noise occurs... Agent: Matthew E. Burr Lake Austin Marina

20070124626 - Method and apparatus for transmitting data in wireless network: A data transmission method and apparatus encodes data to be transmitted over a wireless network on a unit basis, and provides the transmission data with information for allowing the transmission data to recover from an error being added thereto, transmits the transmission data to the wireless network, calculates a transfer... Agent: Sughrue Mion, PLLC

20070124625 - Predicting degradation of a communication channel below a threshold based on data transmission errors: Applicants have discovered that error detection techniques, such as Forward Error Correction techniques, may be used to predict the degradation below a certain threshold of an ability to accurately convey information on a communication channel, for example, to predict a failure of the communication channel. In response, transmission and/or reception... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.

20070124627 - Communication processing device, home electric device, and home network system: A transmission rate negotiation between multi-rate home electric device 100 and communication processing device 200 is completed by sending and receiving a line connection request containing supported transmission rate specifying information specifying plural settable transmission rates, and a device interface information finalization notice containing selected transmission rate information specifying the... Agent: Wenderoth, Lind & Ponack L.L.P.

20070124629 - Embedded testing circuit for testing a dual port memory: Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port (A) and a second port (B), said embedded testing circuit comprising an embedded address generation circuit for generating an internal address consisting of an internal row selection address (RSAint) and... Agent: Maginot, Moore & Beck Bank One Tower

20070124628 - Methods of memory bitmap verification for finished product: Improved methods for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. A first method provides that EMMI is used to identify the physical location of a failing memory bit. A second... Agent: Lsi Logic Corporation

20070124630 - Semiconductor device having adaptive power function: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.... Agent: Harness, Dickey & Pierce, P.L.C

20070124631 - Bit field selection instruction: A digital signal processor having a generalized bit field extraction instruction which can be used to perform a bit field selection operation, a rotate left operation, a rotate right operation, a shift left operation, a logical shift right operation, an arithmetic shift right operation, and so forth.... Agent: Richard Calderwood Stexar Corp.

20070124632 - Touch sensing apparatus: A touch sensing apparatus is provided. The apparatus includes a sensor (13), a flip-flop (16), and a microcontroller unit (17). The sensor is connected to one of input of the flip-flop for receiving electricity signals from an object that touches the sensor. The MCU respectively supplies two AC signals at... Agent: North America Intellectual Property Corporation

20070124633 - Scan driver and organic light emitting display device: An organic light emitting display device includes a scan driver for supplying a first scan signal to a first scan line during a first period and a second period, a second scan signal to a second scan line during the second period, and a light emitting control signal to a... Agent: Christie, Parker & Hale, LLP

20070124635 - Integration circuit and test method of the same: An object of the present invention is to realize an at-speed test on a latch-to-latch path (a cross domain path) between different clock domains. In order to achieve the object, the present invention provides an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates... Agent: International Business Machines Corporation Dept. 18g

20070124636 - Phase synchronization for wide area integrated circuits: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of... Agent: Deniro/rambus

20070124634 - Test circuit, method and apparatus for supporting circuit design, and computer product: A first FF outputs a first signal. A second FF captures the first signal and outputs a second signal. Each of the first and the second FF has a clock terminal to capture a clock signal. A third FF captures the first signal in parallel with the second FF. The... Agent: Staas & Halsey LLP

20070124637 - Method and an integrated circuit for performing a test: A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated... Agent: International Business Machines Corporation

20070124638 - Test apparatus and test method: The present test apparatus avoids proximity restriction violation of an edge and surely generates a test signal. There is provided a test apparatus that tests a device under test. The test apparatus includes a test pattern generating section that generates a test pattern to test the device under test every... Agent: Osha Liang L.L.P.

20070124640 - Automatic request apparatus and method for multihop system broadband wireless access communication network: Provided are an Automatic ReQuest (ARQ) apparatus and method for a multihop system in a broadband wireless access communication system. When the number of ACK MAPs in ARQ feedback information element of ARQ feedback message transmitted from a destination or Multi-Hop Base Transceiver Station (MH-BTS) is not zero, and it... Agent: Dilworth & Barrese, LLP

20070124639 - Retransmission control method and transmitter in wireless communication system: In a wireless communication system, in which a frame comprising data and control information necessary for reception processing of the data is transmitted from a transmitter, and in which, when a reception failure is notified by a receiver, the frame that failed to be received is retransmitted, the control information... Agent: Katten Muchin Rosenman LLP

20070124642 - Automatic request apparatus and method for multihop system in broadband wireless access communication network: Provided are an ARQ apparatus and method for a multihop system in a broadband wireless access communication system. The ARQ method of a relay includes determining if the relay successfully receives specific data from a source and transmitting the specific data to a destination; receiving feedback data from the destination... Agent: Dilworth & Barrese, LLP

20070124641 - Method of improving network layer performance for a wireless station: A method for queuing data frames for improving network layer performance in wireless stations is provided. The method includes loading data frames to be transmitted from a transmitting wireless station into a hardware transmission queue; transmitting the data frames in the hardware transmission queue one data frame at a time;... Agent: North America Intellectual Property Corporation

20070124644 - Iterative metric updating when decoding ldpc (low density parity check) coded signals and ldpc coded modulation signals: Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been... Agent: Garlick Harrison & Markison

20070124643 - Method, encoder and communication device for encoding parallel concatenated data: A method of encoding data in a code block comprising an information bit sequence in a communication device of a communication system comprising the steps of distributing the bits of the information bit sequence of a first coding branch having a length k into a first plurality of n subsets... Agent: Stevens, Davis, Miller & Mosher, LLP

20070124645 - Data transmission method: Encrypted auxiliary information data DYAE/DCAE including no inhibited codes is generated based on auxiliary information data DYA/DCA including no inhibited codes, in an auxiliary data packet having an auxiliary data flag ADF formed of a first combination of a plurality of inhibited codes, the auxiliary data flag ADF is replaced... Agent: William S Frommer Frommer Lawrence Haug

20070124646 - Recording medium, recording method and apparatus, reproducing method and apparatus, data transmitting method, and data decrypting method: A recording medium having an area in which data that has been encoded with a first error correction code is recorded, wherein data that can be decoded with a second error correction code that is different from the first error correction code is recorded to the area along with the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070124648 - Data protection method: One embodiment disclosed is method for protecting data stored on at least one storage unit against uncorrectable media errors. The method includes associating a given redundancy set of at least one redundancy information sector (R) with a given data set of at least two data information sectors (D). The information... Agent: Ido Tuchman

20070124647 - Method and system for a non-volatile memory with multiple bits error correction and detection for improving production yield: A method and system for a non-volatile memory (NVM) with multiple bits error correction and detection for improving production yield are provided. Forward error correction (FEC) operations and cyclic redundancy check (CRC) operations may be utilized in an NVM array integrated in a chip to correct errors in memory elements... Agent: Mcandrews Held & Malloy, Ltd

20070124650 - Disk controller: A disk controller includes a determining unit for determining whether check codes added to data read from a disk drive are first type check codes or second type check codes, and a check code conversion unit. The check code conversion unit includes conversion unit for converting, if the check codes... Agent: Staas & Halsey LLP

20070124649 - Signal processing apparatus, signal processing method and storage system: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection... Agent: Cantor Colburn, LLP

20070124652 - Method and device for multi phase error-correction: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened... Agent: Mark Friedman Ltd. C/o Bill Polkinghorn

20070124651 - Method for lost packet reconstruction and device for carrying out said method: The invention concerns a method for securing a data packet stream involving the following steps: arranging the packets to be sent in a matrix of D rows and L columns; to each row and each column of the matrix, applying an error correction function, the result of which is a... Agent: Joseph J. Laks, Vice President Thomson Licensing LLC

20070124653 - Method and system for detecting a security violation using an error correction code: A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with the data), deriving an error location polynomial (ELP)... Agent: Texas Instruments Incorporated

20070124655 - Apparatus and method for a collision-free parallel turbo decoder in a software-defined radio system: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding binary and duo-binary code. The reconfigurable MAP calculation circuit comprises M memory banks for storing N input data samples. Each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data. The N input data samples are divided... Agent: Docket Clerk

20070124654 - Apparatus and method for decoding a received message with a priori information: An apparatus and method for receiving a message stream on a channel. A message is received on the channel. Information regarding the bits of a successfully decoded message is added to a message attributes list if the message is successfully decoded. An attempt is made to decode a subsequent message... Agent: Motorola Inc

20070124657 - Decoding device, decoding method, and receiving apparatus: A decoding apparatus includes a first decoder and a second decoder performing iterative decoding on each of a plurality of code blocks, each as a decoding unit, contained in a transport block, and a stop/end determination section determining whether or not to stop iterative decoding based on an output result... Agent: Young & Thompson

20070124656 - Generic maximum aposteriori probability decoder for use in software-defined radio systems: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed... Agent: Docket Clerk

20070124658 - Acs apparatus and method for viterbi decoder: The circuit (10) performs a butterfly calculation for a Viterbi trellis by using two path metrics and a branch metric to generate two new path metrics. The new metrics are produced by adders (12) and (14) whose inputs are controlled by selectors (16-22). The outputs of the selectors (16-22) are... Agent: Wolf Greenfield & Sacks, P.C.

20070124659 - Method and system for data replication: A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n−1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data,... Agent: Osha Liang L.L.P./sun

20070124660 - Error correcting processing device and error correcting processing method: According to one embodiment, modulation processing to convert digital information sequences into a form that meets a request from a recording/reproducing system is performed on a digital information sequence and a dummy bit is added to the sequence, and furthermore, an error correcting parity bit sequence is added to the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070118778 - Method and/or apparatus to detect and handle defects in a memory: An apparatus comprising a memory circuit, a test circuit, an interface circuit and a defect handler circuit. The memory circuit may be configured to store and retrieve data in response to (i) a data signal, (ii) a test data signal, (iii) an address signal, (iv) a first control signal and... Agent: Christopher P. Maiorana, P.C.

20070118779 - Intelligent test system and related method for testing an electronic product: An intelligent test system includes a control device for generating control data, and a test device for testing an electronic product. The testing device includes a processor for transmitting a test signal to the electronic product according to the control data generated by the control device, and for controlling the... Agent: North America Intellectual Property Corporation

20070118780 - Hierarchical access of test access ports in embedded core integrated circuits: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one... Agent: Texas Instruments Incorporated

20070118781 - Organic electroluminescent display device: An organic electroluminescent display device employing a demultiplexer to reduce the number of output lines of a data driver. The display device uses the demultiplexer to store a data voltage in a data line, and supplies the stored data voltage to a pixel when a scan signal is applied, thereby... Agent: Christie, Parker & Hale, LLP

20070118782 - Removable and replaceable tap domain selection circuitry: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore... Agent: Texas Instruments Incorporated

20070118783 - Runtime reconfiguration of reconfigurable circuits: A reconfigurable circuit having primary function blocks with runtime built-in self-test (BIST) circuitry, one or more redundant function blocks and runtime reconfiguration logic is described herein.... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20070118784 - Self test circuit for a semiconductor intergrated circuit: A semiconductor integrated circuit that self-tests the skew margin of the clock and data signals in an LVDS. A clock signal CKB1 is held in flip-flop circuit 105 synchronously with checking clock signal A1. Checking pattern signal PAT_A is held in flip-flop circuit 104 synchronously with checking clock signal A2.... Agent: Texas Instruments Incorporated

20070118785 - Multi symbol bit detection for sdpsk signals: This invention discloses a method of accurately detecting the current bit in a SDPSK modulated signal at the receiver. The proposed method calculates the current bit from the past-detected bits and the past symbols. Each past symbol estimates the current bit. Each of these estimates is summed up to provide... Agent: Ashok Tankha, Lipton, Weinberger & Husick

20070118786 - Method and apparatus for receiving data in a communication system: A method and apparatus is provided for receiving data in a receiver of a communication system. In the receiver, a first calculator calculates a Log Likelihood Ratio (LLR) value of data transmitted from a transmitter, a decoder performs iterative decoding on the transmitted data using the LLR value calculated by... Agent: Dilworth & Barrese, LLP

20070118787 - Method and apparatus for forward error correction in a content distribution system: Method, apparatus, and computer readable medium for forward error correction (FEC) in a content distribution system is described. One aspect of the invention relates to encoding frames of content. In one example, each frame is set partitioned into un-coded bits and bits to be encoded. For each frame, parity bits... Agent: General Instrument Corporation Dba The Connected Home Solutions Business Of Motorola, Inc.

20070118788 - Digital demodulating apparatus, controlling method of the apparatus, computer program product for the apparatus, recording medium recording thereon the product, and digital receiver: A digital demodulating apparatus comprises circuit elements constituting a tuner that performs channel select processing to an interleaved received signal, and a demodulator that demodulates the received signal; a deinterleaving section that deinterleaves the interleaved received signal; an error correcting section that corrects errors in the received signal deinterleaved by... Agent: Birch Stewart Kolasch & Birch

20070118789 - Decoding device in optical disc drive and related decoding method thereof: A decoding device is used to deal with an uncorrected data stored in a data storage device, the uncorrected data containing a inner-code parity (PI) direction error data and a outer-code parity (PO) direction error data, the decoding device including: an error correction unit receiving the uncorrected data and correcting... Agent: North America Intellectual Property Corporation

20070118790 - Apparatus and method for stopping iterative decoding in a mobile communication system: An apparatus and method are provided for stopping iterative decoding in a channel decoder of a mobile communication system. Constituent decoding of received signals is performed and decoded signals are output. Hard decision processes for the decoded signals are performed and hard-decided signals are output. The hard-decided signals are cyclic... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070118791 - Pipeline architecture for maximum a posteriori (map) decoders: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are... Agent: Volpe And Koenig, P.C. Dept. Icc

20070113118 - Worm providing storage system: A method for operating a storage system configured to provide a Write Once and Read Many (WORM) function includes receiving a first command at a storage subsystem from a host. At least a portion of the first command is stored on a WORM storage device coupled to the storage subsystem.... Agent: Townsend And Townsend And Crew, LLP

20070113119 - High-speed transceiver tester incorporating jitter injection: A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low-and high-frequency components. The phase-modulated signal is... Agent: Downs Rachlin Martin PLLC

20070113120 - System employing data verification operations of differing computational costs: A computer system having an optimized system for data integrity verification is disclosed. The computer system includes a processor and memory storage that is accessible by the processor. The memory storage includes stored data that is subject to data verification. The system also includes data verification software that is executable... Agent: Brinks Hofer Gilson & Lione

20070113122 - Information recording medium, information reproducing apparatus, information reproducing method and information recording method: An information recording medium includes a user information storage area which stores user information, a test write area which is extendable and for test write of information, a spare area which is extendable and capable of alternatively storing user information, and a recording position management information area including recordable range... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070113121 - Repair of semiconductor memory device via external command: A semiconductor integrated circuit memory device is repaired by receiving an externally-supplied signal containing failure information that identifies at least row or column of memory cells in the memory device that has a failure. The externally-supplied signal contains failure information derived from error correction or other failure logs. The failure... Agent: Edell, Shapiro & Finnan, LLC

20070113127 - Circuit design system and circuit design program: A circuit design system has: a storage unit in which a netlist is stored; a fault-candidate extracting module configured to extract equivalent fault class Gi from the netlist; a judgment module configured to select a target node out of a plurality of nodes Ni1 to Niji included in the equivalent... Agent: Young & Thompson

20070113123 - Method and system for network-on-chip and other integrated circuit architectures: A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an... Agent: Mcdermott Will & Emery LLP

20070113124 - Method of testing integrated circuit and apparatus therefor: In a method of testing integrated circuit (IC), a personal computer host and related software and hardware are used to constitute a system for conducting and controlling IC test. The method includes the steps of: (a) starting the test and using the computer host to drive a loading-unloading device to... Agent: Dykema Gossett, PLLC

20070113125 - System and method for testing a serial port: An exemplary system for testing a serial port includes a serial port (106), a female cable connector (108) connected to the serial port, and an optical-coupled chip (110) connected to the female cable connector. The serial port, the female cable connector and the optical-coupled chip collectively form a circular loop.... Agent: North America Intellectual Property Corporation

20070113126 - Testing and recovery in a multilayer device: Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within... Agent: Carr & Ferrell LLP

20070113130 - Low power testing of very large circuits: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at... Agent: Texas Instruments Incorporated

20070113128 - Method and apparatus for synthesis of multimode x-tolerant compressor: Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.... Agent: Synopsys, Inc. C/o Haynes Beffel & Wolfeld LLP

20070113129 - Method and apparatus for testing logic circuit designs: Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor... Agent: Nec Laboratories America, Inc.

20070113131 - Semiconductor integrated circuit, and designing method and testing method thereof: A semiconductor integrated circuit comprises a combinational circuit section having a combinational circuit, a scan path circuit for inputting and outputting a value from and to the combinational circuit section in accordance with a scan enable signal and in synchronization with a clock signal, and a clock control section for... Agent: Mcdermott Will & Emery LLP

20070113132 - Method and device for verifying timing in a semiconductor integrated circuit: A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a coefficient of variation for each cell based on conditions of the manufacturing process of a semiconductor integrated circuit. The timing verification device receives a... Agent: Staas & Halsey LLP

20070113133 - System and method for testing a serial port: The present invention provides a method for testing a serial port. The method includes the steps of: creating a transmission loop by connecting pins of the serial port; defining testing parameters, and reference values corresponding to the testing parameters; importing a test file that comprises test data; transmitting the test... Agent: North America Intellectual Property Corporation

20070113136 - Detection rate calculation method of test pattern, recording medium, and detection rate calculation apparatus of test pattern: To provide a detection rate calculation method of a test pattern for calculating how much a test pattern can detect short-out generated between the adjacent lines in an integrated circuit. A layout creating program 12 creates layout data 25 from circuit data 21, and creates the information of the adjacent... Agent: Nixon & Vanderhye, PC

20070113135 - Modular compaction of test responses: Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain implementations, the compactors are able to detect errors commonly observed from real defects,... Agent: Klarquist Sparkman, LLP

20070113134 - Test data reporting and analyzing using data array and related data analysis: Reporting and/or analyzing test data from a plurality of tests of an array structure using a data array is disclosed. One method includes obtaining the test data, and reporting the test data in a data array, which includes at least two portions representing different tests. Data stored in the data... Agent: Hoffman, Warnick & D'alessandro LLC

20070113137 - Error correction in binary-encoded dna using linear feedback shift registers: An encoding method for binary data storage in DNA that makes possible the correction of common errors that occur in strands of DNA. A linear feedback shift register generates a long sequence of bits used for the correction of DNA-specific errors.... Agent: Ho Seung Ryu

20070113138 - Apparatus and method for transmitting and receiving packet data using harq in a mobile communication system: A system and method is provided for transmitting packet data in a base station of a wireless communication system using a Hybrid Automatic Repeat Request (HARQ) scheme. The method includes determining a HARQ scheme for use, from among a plurality of HARQ schemes including a Synchronous HARQ (SHARQ) scheme and... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070113140 - Method and apparatus for efficiently retransmitting data in wireless network environment: A method and apparatus for efficiently retransmitting data in a wireless network environment are provided. The method includes transmitting a block comprising one or more data frames to a terminal, receiving an acknowledgement of receipt of the block from the terminal, and retransmitting a block comprising data frames that have... Agent: Sughrue Mion, PLLC

20070113139 - Method for setting environment of mobile communication terminal using multimedia message: Provided is a method for setting the environment of a mobile communication terminal providing a Multimedia Messaging Service (MMS). The method includes displaying a received multimedia message, extracting contents from the received multimedia message to construct a theme, setting the environment of the mobile communication terminal by mapping the contents... Agent: Dilworth & Barrese, LLP

20070113141 - Vsb reception system with enhanced signal detection for processing supplemental data: A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20070113142 - Method and system for providing low density parity check (ldpc) encoding: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences... Agent: The Directv Group Inc

20070113143 - Iterative decoder with stopping criterion generated from error location polynomial: A decoder for error correction an encoded message, such as one encoded by a turbo encoder, with reduced iterations due to an improved stopping criterion. The decoder includes an error correction loop that iteratively processes a message that is encoded prior to transmittal over a communication channel. The error correction... Agent: Stmicroelectronics, Inc.

20070113144 - Decoding apparatus and decoding method: A decoding apparatus is disclosed that is capable of reducing the calculation amount and memory capacity and preventing deterioration of characteristics at high decoding rates. In this decoding apparatus, a transition probability calculation section (201) calculates the transition probability from systematic bit Y1, parity bit Y2 and a priori value... Agent: Stevens, Davis, Miller & Mosher, LLP

20070113145 - Turbo stream processing device and method: A turbo stream processing device and method. A turbo stream processing device includes a turbo stream detector to receive a dual transmission stream in which a turbo stream and a normal stream are multiplexed, and to detect the turbo stream; an outer encoder to encode the turbo stream; an outer... Agent: Stein, Mcewen & Bui, LLP

20070113147 - Apparatus and method for transmitting/receiving a signal in a communication system using a low density parity check code: An apparatus and method are provided for transmitting a signal in a communication system using a low density parity check (LDPC) code. An LDPC codeword is generated by encoding an information word at a coding rate. A puncturing pattern is generated when a hybrid automatic repeat request (HARQ) scheme to... Agent: The Farrell Law Firm, P.C.

20070113148 - Decoding apparatus and method in a communication system using low density parity check codes: A decoding method in a communication system using a Low Density Parity Check (LDPC) code. The method includes determining whether an LDPC codeword to be decoded is a general LDPC codeword to which a puncturing scheme is not applied or a punctured LDPC codeword to which the puncturing scheme is... Agent: Dilworth & Barrese, LLP

20070113146 - System and method for low-density parity check (ldpc) code design: Disclosed is a density evolution algorithm based on a refined definition of node and edge densities for different parts of the code. In particular, density functions ƒV(1)(i) and ƒV(2)(i) of the output edges of the variable nodes with degree i within different codeword regions w1 and we, respectively, are defined... Agent: Nec Laboratories America, Inc.

20070113149 - Power savings technique for iterative decoding: An apparatus and method for reducing an average power consumed by an iterative decoder. A power savings loop coupled to the iterative decoder includes an averager, a comparator and an integrator. The averager receives an iteration count from the iterative decoder and determines an average iteration count of the iterative... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070113150 - Apparatus and method for memory asynchronous atomic read-correct-write operation: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each... Agent: Lemaire Patent Law Firm, P.l.l.c.

20070113151 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070113152 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070113153 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070113154 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070113155 - Semiconductor storage device equipped with ecc function: A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the ECC circuit when a data width of... Agent: Young & Thompson

20070113156 - Information processing method and apparatus, recording medium, and program: An information processing method includes generating a state transition diagram based on state transition information; displaying the state transition diagram; manipulating the displayed state transition diagram; updating the state transition information in accordance with how the state transition diagram has been manipulated; and storing a position of a state designated... Agent: Lerner, David, Littenberg, Krumholz & Mentlik

20070113157 - Data set level mirroring to accomplish a volume merge/migrate in a digital storage system: Users of Mainframe computers running under IBM's MVS operating systems have a need to merge migrate data from multiple smaller DASD devices (disk volumes) to larger DASD devices, and/or to migrate data in order to combine data set extents. A method is disclosed for migrating data where a volume merge... Agent: Stoel Rives LLP

20070113158 - High speed cam lookup using stored encoded key: The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged,... Agent: Qualcomm Incorporated

20070113159 - Golay-code generation: A Golay-code generator configured for generating Golay complementary code pairs comprises a sequence of delay elements configured for providing a predetermined set of fixed delays to at least a first input signal and a sequence of adaptable seed vector insertion elements configured for multiplying at least a second input signal... Agent: Steven J. Shattil

20070113160 - Convolutional decoding: In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes. The convolutional codes may also be block convolutional codes. The lazy... Agent: Fish & Richardson PC

20070113161 - Cascaded radix architecture for high-speed viterbi decoder: A Viterbi decoder includes a branch metric unit for generating branch metrics between two states at two different time periods, a traceback unit, a traceback memory and an add-compare-select circuit. The add-compare-select circuit includes a plurality of cascaded add-compare-select sub-circuits, each add-compare-select sub-circuit calculating a path metric responsive to a... Agent: Texas Instruments Incorporated

20070113162 - Error code for wireless remote control device and method: A method and apparatus to provide error coding for remote control communications.... Agent: Blakely Sokoloff Taylor & Zafman

20070113163 - Belief propagation decoder cancelling the exchange of unreliable messages: The present invention relates a method and a decoder for decoding codewords, the decoding being performed as message passing on a graph representation of the code, e.g. on low density parity-check (LDPC) code, wherein for each non-zero entry in a parity check matrix, the message matrix elements of a first... Agent: Stevens, Davis, Miller & Mosher, LLP

20070106922 - Error rate control apparatus: A radio communication apparatus transmitting a data signal and a control signal to another radio communication apparatus where a controller controls transmission power of the control signal separately from transmission power of the data signal based on a feedback signal from the other radio communication apparatus. A method for controlling... Agent: Myers Wolin, LLC

20070106923 - Integrated circuit and method for testing memory on the integrated circuit: An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform... Agent: Nixon & Vanderhye, PC

20070106924 - Time monitoring of packet retransmissions during soft handover: The present invention relates to a method for scheduling data retransmissions, a method for use in a data retransmission scheme and a method for updating a soft buffer of a base station in a mobile communication system during a soft-handover. The present invention relates to a base station executing the... Agent: Stevens, Davis, Miller & Mosher, LLP

20070106925 - Method and system using checksums to repair data: A method for reconstructing corrupted data, which includes determining a number of non-parity disks (n), selecting a first combination of n-1 non-parity disks, obtaining a first set of physical blocks from the first combination of n-1 non-parity disks, obtaining a parity block associated with the first set of physical blocks,... Agent: Osha Liang L.L.P./sun

20070106926 - Viterbi decoding method and apparatus for high speed data transmissions: Disclosed are a Viterbi decoding method and apparatus for high speed data transmissions. Branch metric is used with data inputted from a Viterbi decoder used in a communication system, and, when current state metric is used for addition, comparison, and selection, the selection operation is performed after simultaneous addition and... Agent: Sughrue Mion, PLLC

20070101178 - Automatic remote monitoring and diagnostics system and communication method for communicating between a programmable logic controller and a central unit: A Monitoring and Diagnostics System is provided, which includes a monitoring unit and a monitored unit remotely located from the monitoring unit. The System also includes communication means between the monitoring unit and the monitored unit. The monitored unit includes data acquisition means for providing fault data of the monitored... Agent: Patrick W. Rasche (22402)

20070101180 - Method and a system or handling a change in status for a resource managed by a utility data center: Embodiments of the present invention pertain to methods and systems for handling a change in status for a resource managed by a utility data center. In one embodiment, an event that describes the change of status for the resource managed by the utility data center is received. The categorization of... Agent: Hewlett Packard Company

20070101179 - Method for fault handling in a co-operative workflow environment: Embodiments herein provide a fault-handling scheme based on forward recovery for cooperative workflow environments. The fault handling scheme relies on the correct placement of transaction scopes and their associated fault and compensation handlers for maintaining correct application semantics, a fault propagation scheme for forwarding faults to a workflow component that... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070101181 - System design and manufacture: A method of system design and manufacture includes entering system details in a first user interface program 100, including in particular availability data. A transfer file 110 defining a spreadsheet including cells representing the system is created and transferred to a spreadsheet 120. The spreadsheet calculates both the availability and... Agent: Hewlett Packard Company

20070101184 - Apparatus and method for detecting over-programming condition in multistate memory device: A system embodiment comprises a nonvolatile memory device, a memory, and a controller. The nonvolatile memory device includes a plurality of nonvolatile memory cells. Each nonvolatile memory cell is adapted to store at least two bits. The memory is adapted to store a program when the system powers up. The... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070101182 - Data storage system, data storage control device, and write error diagnosis method for disks thereof: A storage system has a plurality of disk storage devices and a controller for controlling the plurality of disk storage devices, and diagnosis of a write miss to a disk of the disk storage device. The controller for controlling the plurality of disk storage devices attaches an ID to write... Agent: Staas & Halsey LLP

20070101183 - System and method for managing time-limited long-running operations in a data storage system: A system and method for managing a time-limited long-running process that acts upon disks of a disk array is based upon a general rule of acting upon each disk in an order based upon the length of time from when it was last acted-upon. Disks having the greatest last acted-upon... Agent: Cesari And Mckenna, LLP

20070101186 - Computer platform cache data remote backup processing method and system: A computer platform cache data remote backup processing method and system is proposed, which is designed for providing a main computer platform with a cache data remote backup capability through a backup computer platform; which is characterized by the provision of an interlinking mechanism between the main and backup computer... Agent: Edwards & Angell, LLP

20070101188 - Method for establishing stable storage mechanism: A method for establishing a stable storage mechanism applicable to a computer device with a RAID array and a RAID control unit is proposed. Operating conditions of the disks are constantly monitored, and if a disk is suspected to fail in the near future, a warning message is outputted to... Agent: Edwards & Angell, LLP

20070101185 - Multi-room network guide with scheduling device indicators: Multi-room network guide with scheduling device indicators. The networked multi-room system is made up of at least one primary device and one or more remote devices. The remote devices are able to view the network guide saved on the primary device and schedule programs to be recorded. When viewing the... Agent: Scientific-atlanta, Inc. Intellectual Property Department

20070101187 - Raid system, raid controller and rebuilt/copy back processing method thereof: A RAID system access a physical disk and perform Rebuild/Copy back processing according to a host I/O request, so as to implement high-speed Rebuild/Copy back processing without interfering with the processing of a normal I/O. When one disk device fails, out of a plurality of disk devices constituting a RAID... Agent: Staas & Halsey LLP

20070101189 - Storage apparatus, and control method and program: A rewrite verify processing unit rewrites read data on a sector requiring the number of times of retry equal to or more than a predetermined number of times during a process of reading a medium, and then perform a verify read. A rewrite verify managing unit records the sector processed... Agent: Greer, Burns & Crain

20070101190 - Systems, methods, and media for sharing input device movement information in an instant messaging system: Systems, methods and media for sharing input device movement information between users of an instant messaging system on a network by facilitating transmission and display to one user input device movement information from another user are disclosed. Embodiments may include receiving tracking information by a first client computer system where... Agent: Ibm Corporation (jss) C/o Schubert Osterrieder & Nickelson PLLC

20070101191 - Memory dump method, computer system, and memory dump program: A computer system of the present invention includes cells each of which includes a CPU and a memory, and partitions each of which is configured by combining any number of the cells. A service processor and a control element which controls reading and writing data for memory dumping are provided... Agent: Dickstein Shapiro LLP

20070101192 - Method and system for rollback-free failure recovery of multi-step procedures: Disclosed is a rollback-free method for performing multi-step procedures in the presence of possible failure. As the procedure proceeds from its initial state through transitions to its final state, its constituent transitions are monitored for failure. If a failure is detected, then the procedure is “sidetracked” into a recovery coordination... Agent: Perkins Coie LLP/msft

20070101193 - Diagnostic and managing distributed processor system: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal... Agent: Knobbe Martens Olson & Bear LLP

20070101194 - Method for cache correction using functional tests translated to fuse repair: A method of correcting defects in a storage array of a microprocessor, such as a cache memory, by operating the microprocessor to carry out a functional test procedure which utilizes cache memory, collecting fault data in a trace array during the functional test procedure, identifying a location of the defect... Agent: Ibm Corporation (jvm)

20070101195 - Method for testing network devices using breakpointing: A method for testing a network device having modules for receiving and sending data packets in a network includes generating in the network device at least one internal data structure associated with a data packet received by the network device from the network. A predefined action on the network device... Agent: Hewlett Packard Company

20070101196 - Functional testing and verification of software application: The present disclosure provides methods for testing a software application using the natural input flow of the application. In one respect, a method includes observing the software application under test to determine a current, active input site of the application. The method generates a stimulus for the current, active input... Agent: Fulbright & Jaworski L.L.P.

20070101198 - Semiconductor integrated circuit device, and debugging system and method for the semiconductor integrated circuit device: To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a... Agent: Young & Thompson

20070101197 - System and method for representing system capabilities as software packages in a software package management system: A system, method, and computer program product for representing at least one system capability as a software package in a software package management system. The method includes creating at least one system capability package representing at least one system capability. The at least one system capability package is installed on... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070101199 - Disk array device and failure response verification method thereof: This disk array device having at least one volume that reads and writes data based on an access request transmitted from a client device via a server device, includes: a failure generation unit for generating a simulated failure in one's own device; an access request transmission unit for transmitting the... Agent: Stanley P. Fisher Reed Smith LLP

20070101200 - Methods and systems for eliminating test system reboots between functional tests of host adapter boards: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be... Agent: Pete Scott, Senior Corporate Counsel Lsi Logic Corporation

20070101201 - Method for processing dump data packets in low earth orbital satellite: Provided is a method for processing dump data packets in a low earth orbital (LEO) satellite. The method includes the steps of: a) extracting table identification (ID) information from a header of high-resolution camera (HRC) dump data transmitted from the LEO satellite; b) searching a HRC dump table from a... Agent: Blakely Sokoloff Taylor & Zafman

20070101202 - Clustering process for software server failure prediction: Embodiments of the present invention allow the prevention and/or mitigation of damage caused by server failure by predicting future failures based on historic failures. Statistical data for server parameters may be collected for a period of time immediately preceding a historic server failure. The data may be clustered to identify... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1

20070101203 - Method and apparatus for selecting a primary resource in a redundant subsystem: Embodiments of the invention provide a method and apparatus for selecting a primary resource in a redundant subsystem. In one method embodiment, the present invention receives a list of available resources for a redundant subsystem. Additionally, the available resources are tested and results of the testing are generated. Then, the... Agent: Hewlett Packard Company

20070101204 - Method and system for providing customer service information: A method and system for providing customer service information provide a central database containing software modules for tasks and services and configurations for the modules. Information is received specifying a procedure to be carried out. Software modules relating to tasks forming part of the procedure are invoked, and the information... Agent: Hewlett Packard Company

20070101205 - Intelligent watchdog circuit: A simple, but intelligent watchdog circuit uses an up/down counter for its delay element. A watchdog event will occur if the counter is allowed to over flow or under flow its boundaries (in either direction). The system objective is to keep the counter within its boundaries by controlling the direction... Agent: Dillon & Yudell LLP

20070101206 - Timeouts on accessing a shared resource: A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared... Agent: Hewlett Packard Company

20070101207 - Pci express interface testing apparatus: A PCI Express interface testing apparatus for testing characteristics of signal transmissions of a PCI Express interface includes a printed circuit board, a plurality of sending signal connectors, and a plurality of receiving signals connectors. Both the sending signal connectors and the receiving signal connectors are electrically connected to the... Agent: Morris Manning Martin LLP

20070101208 - System and method for reporting errors: An error reporting mechanism, displayed in a user interface, allows a user to proactively and efficiently communicate error reports to a system administrator. The error reporting mechanism, when selected by the user, causes the user interface to display a text input box for the user to enter descriptive information about... Agent: Kenyon & Kenyon LLP

20070101209 - Method of error correction for a series of marks on an optical disc: A series of marks on an optical disc are sampled to yield a series of data pulses. The marks are at least substantially angularly equidistant to one another on the optical disc. A function is performed on the series of data pulses to yield an error-corrected series of data pulses.... Agent: Hewlett Packard Company

20070101210 - Intelligent table-driven interleaving: The present invention comprises an interleaver that uses a reduced interleaving table to generate interleaved output data blocks from input data blocks. By iteratively applying the reduced interleaving table to bits in the input data blocks, the interleaver generates output data blocks equivalent to those that would have been generated... Agent: Coats & Bennett, PLLC

20070101211 - Defect management method and disk drive using the same: A method and device for management of defects in a recording medium such as a DVD disc are disclosed. The present invention utilizes defect processing table to reduce the seek times of a pick-up head in obtaining replacement ECC blocks for defect ECC blocks in a user data area of... Agent: Madson & Austin Gateway Tower West

20070101212 - Reading method and apparatus for an information recording medium and spare area allocation thereof: An information recording medium reading method is disclosed. The information recording medium has a user data area for recording data and at least one spare area for recording replacements for defects of the user data area. The method includes steps of sequentially reading the user data area; upon a registered... Agent: Madson & Austin Gateway Tower West

20070101213 - Modeling error correction capability with estimation of defect parameters: A method, system and program product accurately model the error characteristics of a communications system, such as a tape storage system. Input parameters are entered which describe defect rates and sizes, Codeword Data Structure bytes, and any interleaving factor. Bit defects from simulated defect sources are generated, defined by the... Agent: Law Office Of Dan Shifrin, PC - Ibm

20070101215 - Automated device testing using intertwined stimulus-generation and response validation specifications for managing dut's that generate out-of-order responses: An intertwined test specification (ITTS) is used for controlling Automated Test Equipment (ATE) to apply a sequence of stimulus signals to a device under test (DUT) during a stimulus run and to validate returned response signals during a validation run. The ITTS has response validation scripts intertwined with stimulus invoking... Agent: Macpherson Kwok Chen & Heid LLP

20070101216 - Method to locate logic errors and defects in digital circuits: When, in the course of an integrated circuit's functional test an assertion fires at clock k, the operational clock is stopped, the sequence is reapplied to capture inputs to the assertion circuit that fired, signals within the assertion circuit are computed, and the error is backtraced. Once one or more... Agent: Henry Brendzel

20070101214 - Self-testing apparatus with controllable environmental stress screening (ess): Systems and methods associated with a self-testing module are described. The module may self control an environmental stress screen (ESS) apparatus and a self-test. One exemplary system includes a substitution test apparatus configured to hold a unit under test (UUT) configured with a self-test logic. The substitution test apparatus facilitates... Agent: Hewlett Packard Company

20070101219 - Semiconductor testing apparatus and method of calibrating the same: A calibration method and a semiconductor testing apparatus, including N drivers, N being a natural number no less than two, at least one transmission path coupled to at least one of the N drivers, at least one calibration board coupled to the at least one transmission path, N comparators, and... Agent: Lee & Morse, P.C.

20070101217 - Serial data input/output method and apparatus: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively... Agent: Texas Instruments Incorporated

20070101218 - Shift register system and method for driving a shift register system: An exemplary shift register system (200) includes a counter (270), a shift register (210), a level shifter (220), and a plurality of switches (231-234). The counter includes a signal receiving pin connecting to a first external circuit, a pulse output pin, and a number of signal output pins. The shift... Agent: Wei Te Chung Foxconn International, Inc.

20070101220 - Systems and methods for accessing input/output devices: Systems and methods are provided for a hardware access tool to access a computer input/output (I/O) device coupled to a standard I/O bus on a host computer system. Upon receiving a standard I/O bus command, the hardware access tool translates the bus command on-the-fly for operation on a selected I/O... Agent: Carr & Ferrell LLP

20070101221 - Method, apparatus and computer program product for implementing scan-chain-specific control signals as part of a scan chain: A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070101222 - Shift registers free of timing race boundary scan registers with two-phase clock control: A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. The two-phase clock generator locally generates... Agent: Jonathan O. Owens Haverstock & Owens LLP

20070101224 - Circuit for generating data strobe signal in ddr memory device, and method therefor: The present invention discloses a circuit for generating a data strobe signal in a DDR memory device and a method therefor which can precisely distinguish preamble and postamble periods of the data strobe signal by generating pulses for generating the data strobe signal only in a data strobe signal input... Agent: Marshall, Gerstein & Borun LLP

20070101223 - Electronic test apparatus and method for testing at least one circuit unit: An electronic test apparatus for testing at least one circuit unit comprises a clock signal generator for generating a clock signal, a driver device comprising a plurality of driver subunits each generating a phase-shifted driver signal in response to said clock signal, a processing device for processing the phase-shifted driver... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070101225 - Circuit and method of testing semiconductor memory devices: A circuit for testing a semiconductor memory device includes a data comparator and a signal aligner. The data comparator compares a first output data and a second output data provided from an output buffer circuit. The data comparator determines whether logical states of the first output data and the second... Agent: Mills & Onello LLP

20070101226 - Method of test pattern generation in ic design simulation system: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070101227 - Digital measuring system and method for integrated circuit chip operating parameters: This invention relates to digitally measuring operating parameters, for example, temperature, within a semiconductor chip and making those measurements internally available to hardware, firmware, and software.... Agent: F. Chau & Associates, LLC

20070101228 - Burst transmission: A terrestrial digital video broadcasting (DVB-T) network is used to transmit IP datagrams to receiving devices using multiprotocol encapsulation (MPE). MPE datagram sections and forward error correction (FEC) datagram sections are transmitted in separate time-sliced bursts using transport stream packets with different packet identifiers (PIDs).... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070101229 - Ldpc concatenation rules for 802.11n systems: Improved LDPC code structure and concatenation rules for IEEE 802.11n systems, providing two code sets per rate, one longer codeword and one shorter codeword. The longer codeword length is determined by the system parameters, while the shorter codeword length is ⅓ of the longer codeword length. A LDPC concatenation rule... Agent: Kenneth L. Sherman, Esq. Myers Dawes Andras & Sherman, LLP

20070101230 - Vsb reception system with enhanced signal detection for processing supplemental data: A VSB reception system includes a sequence generator for decoding a symbol corresponding to the supplemental data and generating a predefined sequence included in the supplemental data at VSB transmission system. The reception system also includes a modified legacy VSB receiver for processing the data received from the VSB transmission... Agent: Lee, Hong, Degerman, Kang & Schmadeka

20070101232 - Apparatus and method for improving turbo code performance in a communication system: An apparatus and method for improving turbo code performance in a communication system are provided. In the apparatus, a bit inserter inserts a predetermined number of bits into a transmission information bit stream, if the effective coding rate of a transmission packet is a predetermined coding rate. A turbo encoder... Agent: Dilworth & Barrese, LLP

20070101231 - Multi-standard turbo interleaver using tables: An interleaver for a turbo encoder and decoder comprising a first table populated with a first set of parameters to allow intra-row permutation of data within an array in accordance with a first wireless communication standard when operation in the first wireless communication standard is required and a second table... Agent: Freescale Semiconductor, Inc. Law Department

20070101235 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070101234 - Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters: A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number... Agent: Townsend And Townsend And Crew, LLP

20070101233 - System, method and computer program product for implementing rate 3/4 low density parity check code: A method, system, apparatus and computer program product for correcting errors in a signal transmission using a rate 3/4 low density parity check (LDPC) code. At least a portion of a received data message is encoded by using a parity check matrix of the LDPC code. The encoded data message... Agent: Hughes Network Systems, LLC C/o Bell, Boyd & Lloyd, LLC

20070101238 - Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh: A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each... Agent: Lemaire Patent Law Firm, P.l.l.c.

20070101239 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070101240 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070101237 - Memory card and memory controller: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area... Agent: Miles & Stockbridge PC

20070101236 - Method and system for performing function-specific memory checks within a vehicle-based control system: Integrity of data stored in a memory space associated with a vehicle-based control system (such as a traction enhancement system) is verified through the use of sub-module checksums. A checksum for one or more subsystem modules is initially calculated based upon a checksum routine and the values of data residing... Agent: General Motors Corporation Legal Staff

20070101241 - 64b/66b coding apparatus and method: A system and method for transmitting digital data over a transmission medium includes receiving digital values representing a plurality of N-bit characters to be output over the transmission medium, each N-bit character being either a data character or a control character. A determination is made as to which of the... Agent: Foley And Lardner LLP Suite 500

20070101242 - Reconfigurable communications infrastructure for asic networks: Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across... Agent: O'keefe, Egan & Peterman, L.L.P.

20070101243 - Method for puncturing a low density parity check code: A method for puncturing a Low Density Parity Check (LDPC). The method includes a) setting a codeword length and the total number of bit nodes to be punctured; b) selecting a check node (or check nodes) with highest priority excluding check nodes completely checked in a current round; c) selecting... Agent: The Farrell Law Firm

20070101244 - Apparatus, system, and method for converting between serial data and encoded holographic data: An apparatus, system, and method are disclosed for converting between serial data and encoded holographic data. The apparatus for converting between serial data and encoded holographic data is provided with a logic unit containing a plurality of modules configured to functionally execute the necessary steps of reading data signals from... Agent: Kunzler & Associates

20070101245 - Method for reducing the computational complexity of viterbi decoder: A method for reducing the computational complexity of a Viterbi decoder, which is suitable for all code rates of a convolutional code applied by the Viterbi decoder. The method dramatically reduces the branch metric computation to thus reduce the complexity of implementing the Viterbi decoder, without affecting the capability of... Agent: Bacon & Thomas, PLLC

20070101246 - Apparatus and method for coding/decoding block low density parity check code with variable block length: Disclosed is a device and method for coding a block low density parity check (LDPC) code having a variable length. The a device and method include receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second... Agent: The Farrell Law Firm