Error detection/correction and fault detection/recovery inventions 02/07

20070043967 - Automatic reconnect and reacquisition in a computer investigation system: An examining machine automatically reconnecting to a target machine and resuming acquisition of data stored in a device coupled to the target machine. The examining machine establishes connection with the target machine and initiates data acquisition of the device coupled to the target machine. Periodically during the data acquisition, the... Agent: Christie, Parker & Hale, LLP

20070043968 - Disk array rebuild disruption resumption handling method and system: A disk array rebuild disruption resumption handling method and system is proposed, which is designed for use with a disk array unit for providing the disk array unit a rebuild disruption resumption handling function, and which is characterized by the capability of continually recording a set of identification data about... Agent: Birch Stewart Kolasch & Birch

20070043969 - Isolating and storing configuration data for disaster recovery for operating systems providing physical storage recovery: Methods for performing a backup and/or restore operation of data from a computer for operating systems providing physical storage recovery methods. To perform a backup operation, a backup storage device and a configuration storage device are communicatively coupled to a computer. One or more data files is saved to backup... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070043970 - Approach for managing interrupt load distribution: A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of... Agent: Hickman Palermo Truong & Becker, LLP And Sun Microsystems, Inc.

20070043971 - Error identifying apparatus: An apparatus, including a plurality of units, each has at least one function which is executed by a software; an error detecting section which detects an error of the apparatus; a selector section which selects at least one of arbitrary unit of the units, when the error is detected by... Agent: Cantor Colburn, LLP

20070043972 - Systems and methods for split mode operation of fault-tolerant computer systems: Methods and systems are provided by which a computer system, and in particular, a lockstep fault-tolerant computer system, may be split into a plurality of independently operational subsystems. Each subsystem may be examined, managed or upgraded by an administrator while the overall computer system continues to service end-users. Finally, the... Agent: Kirkpatrick & Lockhart Nicholson Graham LLP

20070043973 - Isolating and storing configuration data for disaster recovery for operating systems providing physical storage recovery: Methods for performing a backup and/or restore operation of data from a computer for operating systems providing physical storage recovery methods. To perform a restore operation, a backup storage device and a configuration storage device are communicatively coupled to a computer. Physical storage recovery data can be stored on the... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070043974 - Techniques for performing memory diagnostics: Techniques are provided for performing memory diagnostics. A portion of physical memory is locked using functionality included in an operating system. At least one memory diagnostic test is executed on the portion producing a result. It is determined, in accordance with the result, whether a memory problem exists for the... Agent: Microsoft Corporation Attn: Patent Group Docketing Department

20070043975 - Methods and apparatus for recovering from fatal errors in a system: Fatal errors are uncorrectable errors in hardware, which cause entire applications to be restarted and at worst can cause machine reboots. A method of recovering from a fatal error in a system having a plurality of components, in which the system includes a processor for executing a plurality of processes,... Agent: Hewlett Packard Company

20070043976 - Device for continuous calibration of a gas mass flow measurement device: A gas test system (300) is disclosed comprised of a flow loop (302), a blower system (304), a temperature control system (306), a reference meter system (308), and a unit under test (UUT) system (310). The UUT system connects a unit under test (UUT) to the flow loop. The blower... Agent: The Ollila Law Group LLC

20070043978 - Encrypted debug interface: In one embodiment, a system comprises application-specific functionality, debug functionality, and a debug interface communicatively coupled to the debug functionality to communicatively couple the system to a debug device. The debug functionality encrypts data transmitted by the system over the debug interface.... Agent: Honeywell International Inc.

20070043979 - Monitoring of a program execution by the processor of an electronic circuit: A method for monitoring the execution of a program by a processor of an electronic circuit comprises operations of collecting monitoring data within the circuit and of transmitting the monitoring data to a device for debugging the program. The monitoring data are transmitted via a connection external to the circuit,... Agent: Seed Intellectual Property Law Group PLLC

20070043977 - [program encryption method]: Disclosed is a program encryption method, which sets a key in an application program, and the application program is designed by a designer who uses an embedded Linux system as a platform, and the key is writeable but not readable by the application program, but a Linux kernel of the... Agent: Moxa Technologies Co., Ltd

20070043980 - Test scenario generation program, test scenario generation apparatus, and test scenario generation method: A test scenario generation program makes a computer execute a test scenario generation method that generates a test scenario for use in verification of an application involving screen change. The test scenario generation program makes the computer execute: a design information acquisition step S11 that acquires design information of the... Agent: Staas & Halsey LLP

20070043981 - Methods and devices for detecting and isolating serial bus faults: A method for detecting and isolating serial bus faults. Whether any bus fault has occurred on a serial bus coupled to a device through an isolator is detected. When a bus fault occurs on the serial bus, the isolator is controlled to isolate the device from the serial bus. Whether... Agent: Quintero Law Office, PC

20070043982 - Interleaver, deinterleaver, interleaving method, and deinterleaving method for ofdm data: An interleaver and interleaving method each includes two stages, and is useful in coded orthogonal frequency division multiplexed (COFDM) wireless local area networks. A first stage performs a first block permutation and a second stage performs bit order permutation to effectuate a second group permutation. A corresponding de-interleaver does just... Agent: Dov Rosenfeld

20070043984 - Nonvolatile semiconductor memory device and signal processing system: The nonvolatile semiconductor memory device includes: a first memory block having a first program level and a first read circuit; a second memory block having a second program level different from the first program level and a second read circuit of a scheme different from the first read circuit, the... Agent: Mcdermott Will & Emery LLP

20070043983 - Sample screening method for system soft error rate evaluation: A sample screening method for system soft error rate evaluation. Memory cells of a memory device are written and read according to a first test condition to locate hard errors. The memory cells of the memory device are read according to a second test condition to locate functional errors. The... Agent: Birch Stewart Kolasch & Birch

20070043987 - Configurable voltage regulator: A testing system comprises a configurable integrated circuit that has M predetermined configurations that are selected based upon an input signal. The configurable integrated circuit generates a selected one of M discrete values of an output characteristic of the configurable integrated circuit based on the selected one of the M... Agent: Harness, Dickey & Pierce P.L.C

20070043988 - Configurable voltage regulator: A production testing system for testing an integrated circuit comprises a control module that generates a setpoint and a setpoint range. A configurable integrated circuit receives the setpoint and the setpoint range, that has M predetermined configurations, and generates N successive output signals by sequentially selecting N ones of M... Agent: Harness, Dickey & Pierce P.L.C

20070043985 - Memory control method and memory controller: In order to provide a memory control method and a memory controller, which can prevent an extra access even when a transfer frequency is uncertain, a memory access control method according to the invention is a method of controlling continuous transfers from a master connected to a system bus to... Agent: Rabin & Berdo, PC

20070043986 - Method for testing an electronic circuit comprising a test mode secured by the use of a signature, and associated electronic circuit: An electronic circuit comprises a plurality of configurable cells configured according to a chaining command signal. These configurable cells are configured either in a chained state in which the configurable cells are functionally connected in a chain to form a shift register, if the chaining command signal is in a... Agent: Bryan A. Santarelli Graybeal Jackson Haley LLP

20070043989 - Method for specifying failure position in scan chain: It is judged whether or not a scan chin has a failure, an arbitrary data string is inputted to the malfunction scan chain judged that a failure is present by a capture action through a combination circuit, the data string is outputted from a scan-out terminal of the malfunction scan... Agent: Mcdermott Will & Emery LLP

20070043991 - Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable... Agent: Fish & NeaveIPGroup

20070043990 - Providing precise timing control within a standardized test instrumentation chassis: Precise timing control within a standardized chassis such as PXI is obtained by providing several control signals over PXI_LOCAL. A Least Common Multiple (LCM) signal enables all clocks to have coincident clock edges occurring at every LCM edge. A start sequence allows all PXI expansion cards in the test system... Agent: Morrison & Foerster, LLP

20070043992 - Pattern implementation technique: A pattern implementation technique in which a pattern is defined as a software artifact that comprises a pattern signature representing one or more parameters of the pattern and a pattern implementation model representing one or more methods for expanding the pattern in a selected software context by assigning one or... Agent: Walter W. Duft

20070043993 - System and method for protection of data contained in an integrated circuit: A method and a circuit for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, and generating an error signal... Agent: Graybeal, Jackson, Haley LLP

20070043994 - Obtaining test data for a device: Obtaining test data for a device under test includes obtaining a first part of the test data by testing the device at first points of a range of parameters using progressive sampling, and obtaining a second part of the test data by testing the device at second points of the... Agent: Fish & Richardson P.C.

20070043995 - Semiconductor integrated circuit: By mounting, on a semiconductor integrated circuit, a clock stability waiting circuit 4 for deciding whether a clock signal generated by a high speed clock generating circuit 2 is stable or not, a scan pass control circuit 7 capable of switching a scan pass structure based on a signal output... Agent: Mcdermott Will & Emery LLP

20070043996 - Error correction coding and decoding apparatuses: A data allocator allocates (N×kV×kH)-byte source data distributively in N (kV bytes×kH bytes) two-dimensional arrays and sends the data to a V coder and an H coder. The V coder codes each column of the two-dimensional arrays according to an (nV, kV) code V, and the H coder codes each... Agent: Townsend And Townsend And Crew, LLP

20070043999 - Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus: The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order... Agent: Sughrue Mion, PLLC

20070044002 - Offload system, method, and computer program product for performing cyclical redundancy check (crc)-related calculations: An offload system, method, and computer program product are provided for utilizing a hardware network interface for identifying data and calculating at least a portion of a cyclical redundancy check (CRC) value for the data.... Agent: Zilka-kotab, PC

20070043997 - Reduced complexity error correction encoding techniques: An error correction encoder inserts redundant parity information into a data stream to improve system reliability. The encoder can generate the redundant parity information using a composite code. Dummy bits are inserted into the data stream in locations reserved for parity information generated by subsequent encoding. The error correction code... Agent: Steven J. Cahill

20070044001 - Single stage implementation of min*, max*, min and/or max to perform state metric calculation in siso decoder: Single stage implementation of min*, max*, min and/or max to perform state metric calculation in soft-in soft-out (SISO) decoder. This allows for calculation of state metrics in an extremely efficient, fast manner. When performing min or max calculations, comparisons are made using 2 element combinations of the available inputs. Subsequently,... Agent: Garlick Harrison & Markison

20070043998 - Systems and methods for a turbo low-density parity-check decoder: A method for forming a plurality of parity check matrices for a plurality of data rates for use in a Low-Density Parity-Check (LDPC) decoder, comprises establishing a first companion exponent matrix corresponding to a first parity check matrix for a first data rate, and partitioning the first parity check matrix... Agent: Baker & Mckenzie LLP Patent Department

20070044000 - Variable modulation with ldpc (low density parity check) coding: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an... Agent: Garlick Harrison & Markison

20070044004 - Cache memory device, semiconductor integrated circuit, and cache control method: A memory cache device in which a storage area used for a memory data protection function is effectively used at the time of not using the memory data protection function. A mode selection signal makes ECC code sections for storing an ECC code function as a storage area for storing... Agent: Arent Fox PLLC

20070044003 - Method and apparatus of detecting and correcting soft error: Briefly, a method and apparatus of detecting and correcting soft error in a way of a ways group of a cache bank The detection of the soft error may be done by comparing between two replicas of the ways groups. The correction may be done by copying data from one... Agent: Pearl Cohen Zedek Latzer, LLP

20070044005 - Iterative forward error correction: A method of preparing data for transmission. The method includes providing a block of data, generating a plurality of first dimension code words including first dimension forward error correction FEC elements, the elements of each code word may be used interchangeably to reconstruct a data portion of the block corresponding... Agent: Wolf, Block, Schorr & Solis-cohen LLP

20070044006 - Decoding techniques for correcting errors using soft information: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the... Agent: Steven J. Cahill

20070044007 - Method and apparatus for providing error correction capability to longitudinal position data: A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits for each of the... Agent: Dillion & Yudell, LLP

20070044008 - Acs circuit and viterbi decoder with the circuit: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder... Agent: Birch Stewart Kolasch & Birch

20070038880 - Network diagnostic systems and methods for accessing storage devices: A network diagnostic system may include one or more network diagnostic components. A network diagnostic component may include one or more storage devices and may be configured to perform one or more network diagnostic functions. The network diagnostic component and/or at least one other network diagnostic component may access the... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070038881 - Network diagnostic systems and methods for accessing storage devices: A network diagnostic system may include one or more network diagnostic components. A network diagnostic component may include one or more storage devices and may be configured to perform one or more network diagnostic functions. The network diagnostic component and/or at least one other network diagnostic component may access the... Agent: Workman Nydegger (f/k/a Workman Nydegger & Seeley)

20070038882 - Remote access control method and system for peripheral device connected to monitor, and recording medium storing computer program for executing the method: Provided are a remote access control method and system and a recording medium therefor. The method is performed on at least one peripheral device connected to a plurality of monitors in a network, the method including if a change event occurs in the at least one peripheral device, the monitor... Agent: Sughrue Mion, PLLC

20070038885 - Method for operating an arrangement of a plurality of computers in the event of a computer failure: A method is established for operating an arrangement of a plurality of computers that are configured to execute software units. Continuous monitoring of the plurality of computers and intervening with any failed computers is performed via a monitoring computer. The software units are assigned a weighting in accordance with their... Agent: Edell, Shapiro & Finnan, LLC

20070038883 - Mounting system for medical sensors: A mounting system for medical sensors is provided including an interface (2) for the electric contacting of a sensor (1). System components (3, 4, 5, 6, 7, 8) for processing the sensor signals are provided as well as an electromagnetic transmission unit (9) with an antenna (12). The system components... Agent: Mcglew & Tuttle, PC

20070038884 - System and method of remote storage of data using client software: Data, located on a client computer, is stored on a storage device in a computer located in a remote location. Backup software for the client computer loads into memory of the client computer. The backup scheduler and launcher software loads into memory, monitors an actual time at the client computer,... Agent: Pillsbury Winthrop Shaw Pittman LLP

20070038886 - Radio resource management: The present invention relates to radio resource management in a wireless communication system. Specifically, the present invention relates to a method and apparatus for obtaining downlink power information for a multi-sector base transceiver site in which power can be shared between the sectors. Such information can be used in radio... Agent: Motorola, Inc.

20070038887 - Remote disaster recovery and data migration using virtual appliance migration: A technique efficiently creates and serves a backup data set on a backup filer located at a remote site from a primary filer by essentially moving an entire operating environment of a primary data set to the backup filer. The primary filer is organized into one or more virtual filers... Agent: Cesari And Mckenna, LLP

20070038888 - Data protection management on a clustered server: A data protection management system for protecting content controlled by a clustered server is presented. The data protection management system includes a data protection server and a data storage pool. The data storage pool is coupled to and controlled by the data protection server for storing a replicated copy of... Agent: Christensen, O'connor, Johnson, Kindness, PLLC

20070038889 - Methods and systems to access process control log information associated with process control systems: Methods, apparatus, and articles of manufacture to access process control log information associated with process control systems involve obtaining the process control log information from a database based on a plurality of logging time periods and at least one data query. The process control log information is then categorized based... Agent: Hanley, Flight & Zimmerman, LLC

20070038890 - Configurable system and methods for writing and executing test components: An automated and flexible architecture is provided that enables a plurality of component tests to be executed in various testing orders while imposing a test framework to mitigate adverse effects or results on previously developed tests. In one aspect, a computerized test system is provided. The system includes a test... Agent: Amin. Turocy & Calvin, LLP

20070038891 - Hardware checkpointing system: A method and a system for recovering a computing system's hardware state. In one embodiment the method includes simulating a removal of a hardware device from a bus of the computing system, simulating the replacement of the hardware device onto the bus and executing a configuration program for the computing... Agent: Kirkpatrick & Lockhart Nicholson Graham LLP

20070038893 - Creating, designing, managing, scheduling, developing and producing products: Systems and methods to create, design, manage, schedule, develop and produce products are disclosed. A method may include displaying information about a product during creation, design, development and/or production. The displaying may be achieved by providing a three axis representation of a product including in which a first axis is... Agent: SocalIPLaw Group LLP

20070038892 - Pattern sequence and state transition triggers: A pattern sequence and state transition trigger generator provides a trigger when a specified transition from one pattern/state to another pattern/state occurs in a set of input signals. Decoders detect each specified pattern/state from the set of input signals to produce a prior value and a current value representing the... Agent: Thomas F. Lenihan Tektronix, Inc.

20070038896 - Call-stack pattern matching for problem resolution within software: A method of diagnosing a fault condition within software can include, responsive to a fault condition within a computing system belonging to an organization, automatically sending call-stack information for the fault condition to a first server within the organization. Within the first server, the call-stack information for the fault condition... Agent: Cuenot & Forsythe, L.L.C.

20070038895 - Configuring an application monitor utilizing discovered structural information for an application under test: A method, system and apparatus for configuring an application monitor utilizing discovered structural information for an application under test. A system for configuring an application monitor can include an application monitor disposed in a host computing platform. Also, the system can include an application inspector programmed to obtain snapshots of... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg

20070038898 - Method and apparatus for testing software: A state table includes a plurality of possible states of a computer system and the corresponding actions which produce transitions between source and target states. A set of test programs is stored, each test program performing an action in the state table. A test selects an action corresponding to the... Agent: Ibm Corporation

20070038897 - Method and system for delivering a software product from a central computer to a target computer via a computer network: A method and a system for delivering a software product from a central computer to a target computer via a computer network are disclosed. In a first method step, a software product package of the software product is transmitted from the central computer to the target computer via the computer... Agent: Brinks Hofer Gilson & Lione

20070038894 - Test data verification with different granularity levels: Test data is generated by executing code in a software application. The test data may be verified using a verification module. The code is executed based on test conditions. The verification module accesses a verification reference to obtain verification rules and values. Each verification rule is associated with values that... Agent: Merchant & Gould (microsoft)

20070038899 - Method for managing faults in a computer system environment: Many computing system environments require continuous availability and high operational readiness. The ability to find, diagnose, and correct actual faults and potential faults in these systems is a high priority. By combining a continually updated database of computing system performance with the ability to analyze that information to detect faults... Agent: James L. Davison

20070038900 - System with executing nodes for executing schedules: In a system (1) with storing means (2) for storing schedules (200, 210, 220, 230) and comprising nodes (3-6) for executing the schedules (200, 210, 220, 230), first and second nodes (3, 4) are primary and secondary nodes and comprise checking means (302, 402) for checking the storing means (2)... Agent: Sughrue Mion, PLLC

20070038901 - Nonvolatile memory system: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in... Agent: Miles & Stockbridge PC

20070038902 - Method and device for interleaving and method and device for de-interleaving: The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately... Agent: Brinks Hofer Gilson & Lione

20070038903 - Method and device for interleaving and method and device for de-interleaving: The writing address supply part 210 supplies writing addresses for writing the bits forming bit sequences corresponding to the header H contained in a frame to be transmitted or stored and bit sequences corresponding to the data D, into the operating memory 220. The reading address supply part 230 alternately... Agent: Brinks Hofer Gilson & Lione

20070038906 - Column/row redundancy architecture using latches programmed from a look up table: A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch each time an address transition is detected in... Agent: Dickstein Shapiro LLP

20070038904 - Information storage medium, information recording/playback apparatus, and method of recording and playing back information: A rewritable information storage medium includes a user area for storing user data, a defect management area for storing defect management information relating to a defective area in the user area, and a spare area serving as a replacement area for storing the user data that was unable to be... Agent: Knobbe Martens Olson & Bear LLP

20070038905 - Information storage medium, information recording/playback apparatus, and method of recording and playing back information: A rewritable information storage medium includes a user area for storing user data, a spare area serving as a replacement area for storing user data that was unable to be stored in the defective area, and a plurality of defect management areas. The same defect management information is stored in... Agent: Knobbe Martens Olson & Bear LLP

20070038907 - Testing system and method for memory modules having a memory hub architecture: A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memory signals to and... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20070038908 - Design data structure for semiconductor integrated circuit and apparatus and method for designing the same: Design data including circuit data on a test point and information about a test mode, which has been attached to the test point, is inputted to an apparatus for designing a semiconductor integrated circuit. A design data code analysis unit in a data input unit performs the code analysis of... Agent: Mcdermott Will & Emery LLP

20070038909 - Scan driver, display device having the same and method of driving a display device: A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having... Agent: Cantor Colburn, LLP

20070038910 - Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method: A semiconductor integrated circuit design method is a method for designing a semiconductor integrated circuit having a main circuit as well as the spare cell including a scan flip-flop. In the method, a net list is received, which indicates a connection relationship among circuits and their positions in a semiconductor... Agent: Mcginn Intellectual Property Law Group, PLLC

20070038911 - Direct logic diagnostics with signature-based fault dictionaries: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than... Agent: Klarquist Sparkman, LLP

20070038912 - Error correction encoding/decoding apparatus and error correction encoding/decoding method: An error correction coding apparatus which improves the throughput of the whole system, while minimizing the increase of the circuit size and the amount of processing operation of the whole apparatus. In this apparatus, a data divider 132 divides transmission data into a plurality of blocks to generate n divided... Agent: Stevens, Davis, Miller & Mosher, LLP

20070038915 - Adaptive archival format: Data are stored on a random-access storage medium. A user set of data is received. The user set of data is mapped to multiple frames. For each frame, error-correction bytes are generated over the data mapped to that frame. In addition, the data mapped to that frame are written to... Agent: Townsend And Townsend And Crew, LLP

20070038918 - Data backup method and memory device: In first and second areas 10 and 20 in an EEPROM 30, data storing areas 11 and 21 and checksum areas 12 and 22 are respectively provided. The highest bit of checksum data stored in each of the checksum areas 12 and 22 is used as the bit based on... Agent: Smith, Gambrell & Russell

20070038914 - Method and apparatus for block and rate independent decoding of ldpc codes: Methods and apparatus are provided for block and rate independent decoding of LDPC codes. The disclosed LDPC decoders support multiple code block lengths and code rates, as well as a variable parity check matrix. The disclosed LDPC decoders decode LDPC codes that are based on a parity check matrix having... Agent: Ryan, Mason & Lewis, LLP

20070038913 - Method and apparatus for the reliability of host data stored on fibre channel attached storage subsystems: A method for improving the reliability of host data stored on Fibre Channel attached storage subsystems by performing end-to-end data integrity checks. When a read or write operation is initiated, an initial checksum for data in the read/write operation is generated and associated with the data, wherein the association exists... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070038916 - Method of coding data: A method of coding data for transmission in a communication medium or channel. A codeword is generated from a mother code parity check matrix and a macro matrix. The mother code parity check matrix includes sub-matrices that are m-by-m square matrices with cyclic structure, and the macro matrix includes elements... Agent: Hogan & Hartson L.L.P.

20070038917 - Serial data communication - can memory error detection methods: A method is provided for formatting a message, with a first plurality of bits forming a data component, and a second plurality of bits forming a reserved component, for transmission in a vehicle. The method comprises the steps of calculating an initial checksum from the data component, calculating a revised... Agent: General Motors Corporation Legal Staff

20070038919 - Semiconductor memory device: A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such... Agent: Miles & Stockbridge PC

20070038920 - Information recording-reproducing apparatus and method of recording and reproducing information: An information recording-reproducing apparatus includes a recording-reproducing unit configured to record information given by encoding the data in predetermined data blocks with an error correction code, the data blocks being generated by multiplexing information indicating the positions of the defect management areas, on the information storage medium and to decode... Agent: Knobbe Martens Olson & Bear LLP

20070038922 - Method and apparatus for efficiently decoding concatenated burst in a wibro system: A method and apparatus for decoding a concatenated burst in a WiBro system are provided. A concatenated decoder fragments a received burst into fragment blocks, decodes at least one of the fragment blocks, and determines whether the decoded fragment block satisfies a circular state. A concatenated decoding controller determines burst... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070038921 - Method and system for forward error correction: Systems and methods wherein a two-dimensional array or the like is employable in data transmission and/or reception, and wherein characteristic values are computable with respect to data to be transmitted. The characteristic values are transmitted along with the data and perhaps used by a data recipient, and could include, for... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070033430 - Data storage distribution and retrieval: A device and method for storing data is disclosed. A user record is divided up into a plurality of input packets (block 202). The plurality of input packets is encoded into a plurality of output packets (block 204). The output packets are distributed to one or more storage devices (block... Agent: Hayes, Soloway P.C.

20070033433 - Dynamic write cache size adjustment in raid controller with capacitor backup energy source: A high data availability write-caching storage controller has a volatile memory with a write cache for caching write cache data, a non-volatile memory, a capacitor pack for supplying power for backing up the write cache to the non-volatile memory in response to a loss of main power, and a CPU... Agent: Huffman Law Group, P.C.

20070033431 - Storage controller super capacitor adaptive life monitor: A storage controller has a capacitor pack for storing energy to supply during a main power loss, a temperature sensor that senses the capacitor pack temperature, and a CPU, which repeatedly: receives the temperature during an interval over which the capacitor pack is operated, determines a lifetime over which the... Agent: Huffman Law Group, P.C.

20070033432 - Storage controller super capacitor dynamic voltage throttling: A storage controller has a capacitor pack for storing energy to supply power during a main power loss, a temperature sensor that senses the capacitor pack temperature, and a CPU, which detects that the temperature of the capacitor pack has risen above a predetermined threshold while operating at a first... Agent: Huffman Law Group, P.C.

20070033434 - Fault-tolerant processing path change management: Change management of data processing paths by tentatively trying proposed alternative data processing path(s) without first giving up the existing processing path. If the alternative data processing path(s) does not give a more satisfactory result that the existing processing path, the existing processing path may be returned to. On the... Agent: Workman Nydegger/microsoft

20070033435 - Method and sytem for redundancy management of distributed and recoverable digital control system: A method and system for redundancy management is provided for a distributed and recoverable digital control system. The method uses unique redundancy management techniques to achieve recovery and restoration of redundant elements to full operation in an asynchronous environment. The system includes a first computing unit comprising a pair of... Agent: Honeywell International Inc.

20070033436 - System and method for journal recovery for multinode environments: A system and method are disclosed for providing journal recovery in a multi-node environment which comprises determining whether a block was updated by a first node; determining whether the block is associated with a lock held by a second node; and writing the block to a final location if the... Agent: Van Pelt, Yi & James LLP

20070033437 - Data processing system: In a data processing system having a primary site and a secondary site, storage systems are connected to each other via a communication line, data update history is recorded in a storage device as a journal in the primary site, and the journal is transferred to the secondary site via... Agent: Townsend And Townsend And Crew, LLP

20070033438 - Method and system for controlling powers of a plurality of servers: A method and system of controlling powers of a plurality of servers with a power control command mechanism. The system for controlling powers of a plurality of servers compatible with an intelligent platform management interface comprises a console unit, a command mechanism and a plurality of control modules. The console... Agent: Troxell Law Office PLLC

20070033439 - Look-across system: A system and method configured to look across programs, and more specifically, to a look-across program application used to update large and complex amounts of information. The information updated may be FMEA (failure modes and effects analysis) reports. Multiple FMEA reports are updated efficiently according to common attributes between products/processes... Agent: Mcdonald Hopkins Co., Lpa

20070033440 - Parameterized unit tests: Separation of parameterized unit tests from specific test cases supports many benefits including automated test case generation. Symbolic execution assigns symbolic input variables to parameters of a parameterized unit test. Path constraints of an implementation under test (IUT) are identified during symbolic execution. A constraint solver automatically generates test cases... Agent: Klarquist Sparkman LLP

20070033441 - System for and method of multi-location test execution: Methods, systems and computer program products for performing multi-location execution of tests between or among multi-sided test components in a wireless environment are described. Multiple flows are initiated substantially simultaneously and concurrently executed. A graphical representation of a multi-flow test is created that permits synchronization of the flows among agents... Agent: Agilent Technologies Inc.

20070033444 - Method and apparatus of providing devices with history information on image forming jobs: A method and apparatus for providing devices with job history information on image forming jobs are provided, in which job history information corresponding to image forming jobs of the devices are generated. The job history information is transmitted to any device selected from the devices.... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.

20070033442 - Mock object generation by symbolic execution: A system for testing programs using a digital processor and programs in computer memory. A mock behavior generator identifies an interface indicated for mock behavior. The interface is identified as an input parameter of a parameterized unit test. The mock behavior generator creates a symbolic object with stubs to receive... Agent: Klarquist Sparkman LLP

20070033443 - Unit test generalization: A computer system provides a test program and one or more unit tests, such as a traditional unit test and or a parameterized unit test. The system also includes a constraint solver, a theorem prover, an implementation under test, a symbolic executor, a generalizor, and generated test cases. The generalizor... Agent: Klarquist Sparkman LLP

20070033447 - Heartbeat apparatus via remote mirroring link on multi-site and method of using same: The present invention is directed to a heartbeat apparatus via a remote mirroring link for a multi-site and a method for using the heartbeat apparatus. Information is registered in a configuration table, wherein the configuration table stores host ID information and volume ID information. The configuration table is configured, access... Agent: Reed Smith LLP

20070033445 - Method, apparatus, and program product for autonomic patch risk assessment: An automatic risk assessment system is provided that determines a risk for the patch based on collected activity metrics, file weights, a list of files affected by the patch, and other factors. An application monitor collects metrics from the application to determine the level of activity of the application or... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20070033446 - Monitoring apparatus: An apparatus for monitoring a digital television decoder connected to a network comprising a monitor engine and a monitor server wherein the monitor engine is operable to receive and/or retrieve raw event data from a digital television decoder connected to a network, generate significant event data in dependence on the... Agent: Gifford, Krass, Groh, Sprinkle & Citkowski, P.c

20070033448 - Method and apparatus for using dual bit decisions to measure bit errors and event occurences: An apparatus and method for measuring errors and event occurrences in a multi-valued data stream by using a dual decision bit error rate tester is disclosed. The Bit error rate tester (BERT) includes a plurality of decision circuits operative to provide a respective bit decision output signal in response to... Agent: PeninsulaIPGroup

20070033450 - Column redundancy system for an integrated circuit memory: A memory is organized with many memory subspaces (db<i>) each including their own read-out circuit (SA<i>). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory controller is provided for interacting with the memory... Agent: Jenkens & Gilchrist, PC

20070033449 - Flash memory device and method of repairing defects and trimming voltages: A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified in response... Agent: Marger Johnson & Mccollom, P.C.

20070033452 - Method and circuit arrangement for detecting errors in a data record: The method comprises providing a part-data record to be changed from a data record stored in a memory device, providing a change data record changing the part-data record to be changed and providing a check word associated with the data record. The check word is changed by a change transformation... Agent: Dickstein Shapiro LLP

20070033451 - Method for writing data blocks on a block addressable storage medium using defect management: The present invention relates to a method for writing data blocks on a block addressable storage medium, preferably an optical storage medium, using defect management, comprising the steps: processing data to data blocks adapted to the storage medium by a host device; sending each data block from the host device... Agent: Glenn Patent Group

20070033457 - Circuit board and method for manufacturing the same: A circuit board and a method of manufacturing the same are disclosed. Embodiments of the circuit board may include a dielectric substrate, a first via structure comprising a first via-hole, which is defined through the dielectric substrate, and a plurality of first vias that are formed on an inner wall... Agent: Marger Johnson & Mccollom, P.C.

20070033458 - Diagnostic method and apparatus for non-destructively observing latch data: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20070033456 - Integrated circuit test system and associated methods: An integrated circuit chip test system comprises a reference chip adapted to generate original test data, and a test target chip adapted to receive and process the original test data to produce processed test data. The test target chip returns the processed test data to the reference chip, and the... Agent: Volentine Francos, & Whitt PLLC

20070033455 - Load testing of a telecommunication network: A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with the load test being divided into several test phases and on the graphical user interface functionalities being... Agent: Tektronix, Inc. M/s 50-law

20070033454 - Method and apparatus for securing communications ports in an electronic device: An apparatus comprises at least one port for coupling signals to the apparatus, a mode selector for setting the apparatus to a normal mode or a debug mode, and a port control for controlling access to secure information in the apparatus through the port in accordance with the selected mode.... Agent: Pietragallo, Bosick & Gordon LLP

20070033453 - Test of ram address decoder for resistive open defects: A new test pattern which consists of performing “very small jumps” and “very big jumps” within the matrix. The “very small jumps” are controlled by the row decoder, and have the effect of sensitizing the resistive open defects which lead to slow-to-fall behavior in the word line. A “very small... Agent: Philips Intellectual Property & Standards

20070033463 - Integrated circuit comprising a test mode secured by detection of the state of a control signal: An electronic circuit comprises configurable cells driven by command signals to adopt either a standard mode of operation in which they are integrated into a logic circuit, or a test mode in which they provide information on this logic circuit. The circuit includes a spy circuit capable of detecting an... Agent: Graybeal Jackson Haley LLP

20070033461 - Method and system for encryption-based design obfuscation for an integrated circuit: Encryption-based design obfuscation for an integrated circuit includes creating multiple functional circuit paths for an integrated circuit design and selecting among the multiple functional circuit paths during scan testing. Encrypting selection data corresponding to an intended function of the integrated circuit design avoids revealing the intended function as a result... Agent: Sawyer Law Group LLP

20070033459 - Method for enabling scan of defective ram prior to repair: A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal... Agent: Lynn L. Augspurger IBM Corporation, Iplaw

20070033460 - System and method for scan testing: A scan system comprises a scan engine adapted to receive a scan request from a host system for performing a scan test on a system-under-test. The scan engine comprises dedicated logic where a state of the dedicated logic is adapted to control processing of the scan request on the system-under-test.... Agent: Hewlett Packard Company

20070033462 - Test circuit and test method: A test method sets a write value to a scan flip-flop for setting a value to a memory to be tested. It then performs a series of shift operation in scan paths until setting of a read value is completed. During the shift operation, a value for refresh operation is... Agent: Young & Thompson

20070033465 - Apparatus and method for a single wire interface between a intergated circuit and jtag test and emulation apparatus: A single conducting path provides communication between a JTAG unit and a JTAG TAP controller. The data is communicated between the two units using time-division multiplexing. Three time slots are allocated to data-in, to data-out and to JTAG control signals. Two of the time-division multiplexing slots exchange data by having... Agent: Texas Instruments Incorporated

20070033464 - Efficient clocking scheme for ultra high-speed systems: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the... Agent: Michael G. Fletcher Fletcher Yoder

20070033466 - Method and apparatus for handling of clock information in serial link ports: A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a... Agent: Anne Vachon Dougherty

20070033467 - Method and device for protecting a memory against attacks by error injection: A method secures a memory in which individually read-accessible binary words are saved. The method includes defining a memory zone covering a plurality of words, calculating a cumulative signature according to all of the words in the memory zone, and storing the cumulative signature as an expected signature of the... Agent: Seed Intellectual Property Law Group PLLC

20070033470 - Emulation cache access for tag view reads: A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state.... Agent: Texas Instruments Incorporated

20070033471 - Hardware configuration of pbist: This invention is a method of constructing an integrated circuit with built-in self test. The built-in self test includes a built-in self test unit a read only memory storing test algorithms and test data. The built-in self test unit of a particular integrated circuit includes a subset of all test... Agent: Texas Instruments Incorporated

20070033469 - Rom-based memory testing: This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration... Agent: Texas Instruments Incorporated

20070033468 - System, apparatus and method of improving logical built-in self test (lbist) ac fault isolations: A system, apparatus and method of isolating a plurality of limiting logical cones in a chip during a logical built-in self test (LBIST) are provided. An LBIST is performed on the chip in order to locate a first latch that fails the test. Particularly, latches on the chip are arranged... Agent: Ibm Corporation (ve) C/o Volel Emile

20070033472 - Vlct programmation/read protocol: An integrated circuit with built-in self test enables internal data registers to be written to or read from via an external tester. In a command phase the programmable built-in self test unit receives a command, an address and a data transfer count. The address specifies the initial data register address.... Agent: Texas Instruments Incorporated

20070033473 - Lsi inspection module, control method for lsi inspection module, communication method between lsi inspection module and inspection apparatus, and lsi inspection method: In an LSI inspection module, an I/O interface compatible with the I/O interface of an LSI as an inspection target is provided and testing data is stored in a memory for test data. During inspection, an LSI inspection apparatus controls the interface control circuit of the inspection module by setting... Agent: Mcdermott Will & Emery LLP

20070033474 - Production test technique for rf circuits using embedded test sensors: A single test stimulus and a simple test configuration with embedded envelope detectors are used to estimate all the specification values of interest for an RF circuit under test in an integrated circuit chip. Envelope detectors are deployed as sensors inside the circuit under test. Where more than one circuit... Agent: Merchant & Gould PC

20070033475 - Digital broadcasting transmission capable of improving receiving and equalizing performance and signal processing method thereof: A digital broadcast transmitting system and a signal processing method thereof that improves the receiving performance of the system. A digital broadcast transmitter includes a randomizer to receive and randomize a transport stream into a specified position of which stuff bytes are inserted, a replacement sequence generator to generate known... Agent: Stein, Mcewen & Bui, LLP

20070033476 - Method and system for decoding signals, corresponding receiver and computer program product: A system for the transmission of signals comprises a transmitter configured for transmitting signals xt, encoded with a mapping, with different and separable configurations in the real part and the imaginary part of the signal. These may be, for example, signals xt encoded according to a Gray mapping, signals xt... Agent: Graybeal Jackson Haley LLP

20070033477 - Packet based retransmission system for dmb service and apparatus therefor: Disclosed is a packet based retransmission apparatus for a digital multimedia broadcasting (DMB) terminal supporting DMB service. The apparatus and system includes a DMB receiver for receiving DMB data transmitted through a broadcasting transmission medium; and a DMB transport mode release unit for releasing a DMB transport mode in the... Agent: Dilworth & Barrese, LLP

20070033479 - Apparatus, method and computer program for correction of multiple bit errors: The present invention relates to an apparatus and method for monitoring and correcting data errors in a computer system, in particular transient data errors in computer systems having very limited tolerance for deteriorations in performance. The method comprises the steps of: writing a set of data to a plurality of... Agent: Albihns Stockholm Ab

20070033486 - Channel interleaving/deinterleaving apparatus in a communication system using low density parity check code and control method thereof: A channel interleaving method and apparatus in a communication system using a low density parity check (LDPC) code. Upon receipt of information data bits, an encoder encodes the information data bits into an LDPC codeword using a predetermined coding scheme. A channel interleaver interleaves the LDPC codeword according to a... Agent: Dilworth & Barrese, LLP

20070033482 - Decoder device and decoding method and program: A device and a method that improve decoding characteristics of an LDPC decoder to which SPA where the equation for the computation of messages is approximated and the number of messages are reduced is applied. A received LDPC code is decoded by repeating the passing of messages between a plurality... Agent: Foley And Lardner LLP Suite 500

20070033481 - Decoding device and decoding method and program: To provide an LDPC decoder, to which SPA is applied, and a method wherein decoding characteristics are improved by reducing the ratio of a message from a check node within messages sent to the same check node. In a decoding device that decodes a received LDPC code by repeating the... Agent: Foley And Lardner LLP Suite 500

20070033480 - Efficient construction of ldpc (low density parity check) codes with corresponding parity check matrix having csi (cyclic shifted identity) sub-matrices: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero... Agent: Garlick Harrison & Markison

20070033485 - Low-complexity hybrid ldpc code encoder: Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G... Agent: Keshab K. Parhi

20070033483 - Method of generating quasi-cyclic low density parity check codes and an apparatus thereof: Disclosed is a method and apparatus for completely recovering received data with high reliability using LDPC codes without short-sized cycles in a digital communication system using an error-correcting code. The method includes performing exponent conversion of a predetermined number of exponent matrixes stored in advance in a memory so as... Agent: Dilworth & Barrese, LLP

20070033478 - System and method for blind transport format detection with cyclic redundancy check: A method for BTFD decoding of signals having at least a message block of k-bit from a length candidate set S={s1, s2, . . . si}, wherein the k message bits are encoded by a CRC encoder and processed by an (n, l, m) convolutional encoder to generate encoded data... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070033484 - System and method for designing rs-based ldpc code decoder: A memory address generation method and circuit architecture for time-multiplexed RS-based LDPC code decoder is presented. The method is developed for non quasi-cyclic RS-based LDPC code decoder implementation. A circuit for the memory address generation method achieves low area. High throughput time-multiplexed RS-based LDPC code decoder design models and circuit... Agent: Keshab K. Parhi

20070033488 - Persistent error detection in digital memory: A method for detecting a persistent error in a digital memory is provided. Error location information for errors detected in the digital memory is received. A group of the errors that are associated with a same error position is identified from the error location information. A number of the errors... Agent: Hewlett Packard Company

20070033491 - Repair techniques for memory with multiple redundancy: In one aspect, the present invention features techniques for generating a repair solution for a memory having a set of IOs including a plurality of main IOs and a plurality of redundant IOs. For example, techniques are provided for selecting a mapping between input/output ports of the memory and a... Agent: Hewlett-packard Company Intellectual Property Administration

20070033487 - Semiconductor memory device and method of operating the same: A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at... Agent: Edell, Shapiro & Finnan, LLC

20070033489 - Semiconductor memory device and method of operating the same: A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as... Agent: Edell, Shapiro & Finnan, LLC

20070033490 - Semiconductor memory module with error correction: A semiconductor memory module comprises a control chip for driving ECC memory chips and further memory chips. The memory chips are arranged in two rows on a top side and a bottom side of the module circuit board. The ECC memory chips are arranged centrally on the module circuit board... Agent: Edell, Shapiro & Finnan, LLC

20070033492 - Method and device for monitoring an electronic circuit: A method and apparatus for monitoring an electronic control system such that provision is made for the complete data of at least one memory to be read sequentially into an ECC unit, which can be filled very rapidly from the memory, and automatically checked there, with no need to transfer... Agent: Kenyon & Kenyon LLP

20070033493 - Using fractional sectors for mapping defects in disk drives: Herein described is at least a method and system for processing a read or write operation when one or more defects are mapped using one or more fractional sectors. The method comprises using one or more fractional sectors to map defects and to store data symbols. Furthermore, a first algorithm... Agent: Mcandrews Held & Malloy, Ltd

20070033495 - Code-word list algorithm: A communications system for reducing bit errors in a received data sequence provides a method for generating candidate code-word sequences for evaluation by a CRC decoder. The system may determine a most-likely received sequence using the probable code-word list of candidate sequences. The number of candidate sequences may be reduced... Agent: Motorola Inc

20070033494 - Method, device, and system for forward channel error recovery in video sequence transmission over packet-based network: Accelerated video decoding makes use of FEC-repaired media packets that become available through FEC decoding later than their intended decoding time, so to re-establish the integrity of the prediction chain between predicted pictures. The decoder state may be stored at the time of reception of an erroneous packet or at... Agent: Ware Fressola Van Der Sluys & Adolphson, LLP

20070033496 - System and method for adjusting ber/per to increase network stream-based transmission rates: A transmitting method obtains a data packet of a data-type to be transmitted via a computer network to a receiving system; appends a retry flag to the data packet, the retry flag based on the data-type, the retry flag indicating whether the receiving system may attempt a retransmission; and transmits... Agent: Thelen Reid Brown Raysman & Steiner LLP

20070033498 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033499 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033500 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033501 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033502 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033503 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033504 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033505 - Data processing method and apparatus, recording medium, reproducing method and apparatus using the same method: A burst error-correcting capability is largely improved. At least the even-number row and at least the odd-number row of the data block which is a set of data sectors are separated. An outer parity is created for each column and an inner parity is created for each row. Then, the... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070033497 - Efficient construction of ldpc (low density parity check) codes with corresponding parity check matrix having csi (cyclic shifted identity) sub-matrices: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero... Agent: Garlick Harrison & Markison

20070033507 - Efficient error code correction: In one embodiment of the invention, an error-correcting receiver includes an input buffer for storing received codewords, a first error correction syndrome circuit coupled to receive a first codeword and produce an output word, and a second error correction syndrome circuit coupled to receive a second codeword and produce an... Agent: Macpherson Kwok Chen & Heid LLP

20070033506 - Error detection detection device and error detection method: In an error detection method of the present invention, as shown in FIG. 1, target code strings which are inputted in a discontinuous arrangement are subjected to a syndrome operation, and simultaneously, the target code strings which are inputted in a discontinuous arranged are subjected to a first error detection... Agent: Wenderoth, Lind & Ponack L.L.P.

20070033508 - Interative stripewise trellis-based symbol detection method and device for multi-dimensional recording systems: When processing a two dimensional data area it is known to be advantageous to divide the two dimensional are into stripes and process each stripe using a stripe-wise detector. The stripe being processed shifts row per row downwards. Each stripe has as its output the bit-decisions of the top bit-row... Agent: Philips Intellectual Property & Standards

20070033509 - Method and apparatus for concatenated channel coding with variable code rate and coding gain in a data transmission system: A novel method and apparatus for efficiently coding and decoding data in a data transmission system is described. A concatenated coding scheme is presented that is easily implemented, and that provides acceptable coding performance characteristics for use in data transmission systems. The inventive concatenated channel coding technique is well suited... Agent: Berkeley Law & Technology Group

20070033510 - Turbo decoder employing simplified log-map decoding: A turbo decoder iteratively decodes a received, encoded signal with one or more constituent decoders employing a simplified log-maximum a posteriori (SMAP) decoding algorithm. The SMAP decoding algorithm calculates reliability information as a log likelihood ratio for a log-MAP algorithm using a reduced set of path metrics recursively updated based... Agent: Mendelsohn & Associates, P.C.

20070033511 - Methods and apparatus for processor system having fault tolerance: A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the input/output processor, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by... Agent: Raytheon Company C/o Daly, Crowley, Mofford & Durkee, LLP

20070033514 - Apparatus and method for detecting data error: A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with... Agent: Sughrue Mion, PLLC

20070033512 - Method and apparatus for detecting communication errors on a bus: A semiconductor memory comprising multi-mode reporting signals, a state register, and parity detectors is disclosed. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enables reporting of communication faults without adding additional signals to the semiconductor memory by being configured... Agent: Trask Britt, P.C./ Micron Technology

20070033513 - Radio communication system, transmitter and decoding apparatus employed in radio communication system: Radio-communication-system includes transmitting-station and receiving-station. The transmitting-station includes first-encoding-unit configured to generate plural parity-information by using the different-data, second-encoding-unit configured to encode each of the plural parity-information and each of the different-data to produce plural encoded-data, modulation-unit configured to modulate carriers by the plural encoded-data to generate plural modulated-signals, and... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070028134 - Communication device and method of transmitting data: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication... Agent: Dickstein Shapiro LLP

20070028133 - Download method for file by bit torrent protocol: The present invention relates to the improvement of the Bit Torrent protocol, which is one of the P2P protocols. A seeder flag is added to the active peer table. First a super seeder having the original is activated, and the super seeder is stopped when the total value of the... Agent: Oliff & Berridge, PLC

20070028135 - Method and apparatus for dynamic performance evaluation of data storage systems: Improved approaches for evaluating performance of data storage systems used with computers are disclosed. The performance evaluation of the data storage systems utilizes dynamic performance evaluation by use of data throughput as a diagnostic. The data storage systems include, for example, either disk drives or RAIDs. In one embodiment, the... Agent: Beyer Weaver & Thomas, LLP

20070028138 - Combined local and network storage interface: A method, system and computer program product for a generic data storage interface for local and remote networked storage is provided. It comprises providing a data storage interface accessible by an operating system, transmitting data from an application running on the operating system to the data storage interface and selectively... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070028137 - Computer data storage unit reinstallation data protection method and system: A computer data storage unit reinstallation data protection method and system is proposed, which is designed for use with a computer platform for providing a reinstallation data protection function to a data storage unit that is to be installed onto the computer platform, which is characterized by the categorization of... Agent: Pearl Cohen Zedek, LLP Pearl Cohen Zedek Latzer, LLP

20070028140 - Information processing method and information processing device: According to one embodiment, an information processing method comprising reading information of a data frame from an external to store the information in a memory, the data frame being defined to include an error detecting parity code, checking by use of the error detecting parity code whether or not there... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070028136 - Parity update footprints kept on disk: Parity Update Footprints (PUFPs) are kept on the disk drives themselves (rather than in nonvolatile RAM) so that the PUFPs will move along with the RAID arrays and data they protect. This permits effective detection of and recovery from many unexpected-power-loss events, and certain other types of failures, even in... Agent: Oppedahl & Olson LLP

20070028139 - Resource allocation throttling in remote data mirroring system: A computer network remote data mirroring system writes update data both to a local data device and to a local, chronologically sequenced journal storage area, or writelog device. A graphical user interface enables a user to create and configure throttles, which are user-defined tests and actions evaluated by the primary... Agent: Van Pelt, Yi & James LLP And Emc Corporation

20070028141 - Interrupt-responsive non-volatile memory system and method: An interrupt-responsive non-volatile memory respond to an interrupt by aborting execution by a memory controller of a memory routine in a non-volatile memory, sets, a flag and executes an interrupt service routine; and upon completion of the interrupt service routine, in response to the flag, recovers the execution of the... Agent: Iandiorio & Teska Intellectual Property Law Attorneys

20070028142 - Application delay analysis: A graphic user interface facilitates the hierarchical analysis of timing parameters related to network-based applications. At the top level of the hierarchy, the user is presented a summary of the delays incurred while running an application, or while simulating the running of an application, organized by delay categories, including processing... Agent: Robert M. Mcdermott, Esq.

20070028143 - Integrated systems testing: A hard disk drive system comprises N hard disk drive means for performing hard disk drive functions and is connected in a daisy chain, wherein N is greater than one. The system includes integrated system test (IST) means for testing and that is integrated with a first one of the... Agent: Harness, Dickey & Pierce P.L.C

20070028144 - Systems and methods for checkpointing: The invention relates to checkpointing a disk and/or memory. In one aspect, a first computing device receives a write request that includes a data payload. The first computing device then transmits a copy of the received write request to a second computing device and writes the data payload to a... Agent: Kirkpatrick & Lockhart Nicholson Graham LLP

20070028145 - Raid-6 multiple-input, multiple-output finite-field sum-of-products accelerator: A standalone hardware engine is used on an advanced function storage adaptor to improve the performance of a Reed-Solomon-based RAID-6 implementation. The engine can perform the following operations; generate P and Q parity for a full stripe write, generate updated P and Q parity for a partial stripe write, generate... Agent: Oppedahl & Olson LLP

20070028146 - Semiconductor memory device system, and method for operating a semiconductor memory device system: A method for operating a semiconductor memory device system, and a semiconductor memory device system are disclosed. In one embodiment, the system includes a memory device and a control means connected with the memory device via a bus system, wherein a single signal line or a single signal line pair... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070028147 - Method and apparatus for outage measurement: An Outage Measurement System (OMS) monitors and measures outage data at a network processing device. The outage data can be stored in the device and transferred to a Network Management System (NMS) or other correlation tool for deriving outage information. The OMS automates the outage measurement process and is more... Agent: Marger Johnson & Mccollom, P.C.

20070028148 - Device and method for malfunction monitoring and control: A monitoring device and method are provided to monitor a separate device for malfunctions and to control and restore the malfunctioning monitored device to a normal functioning state. A malfunction state includes the monitored device being powered off or in a standby power state. The monitoring device includes control logic... Agent: Ati Technologies, Inc. C/o Vedder Price Kaufman & Kammholz, P.C.

20070028150 - Error correcting memory access means and method: As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, it will be necessary to create memory devices for which the testing of the device must be minimized in order to minimize costs. Current memory manufacturing... Agent: Goodwin Procter LLP Patent Administrator

20070028149 - System, method, and computer program product for reducing error causing conditions in an information handling system: A system includes a first information handling system (“IHS”) for collecting information associated with conditions that cause errors in a second IHS. The first IHS is also for, in response to the information, forming a list of error-causing conditions. Moreover, the first IHS is for outputting the list to the... Agent: Haynes And Boone, LLP

20070028151 - Supervisory operating system for running multiple child operating systems simultaneously and optimizing resource usage: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity... Agent: Schmeiser, Olsen & Watts

20070028152 - System and method of processing received line traffic for pci express that provides line-speed processing, and provides substantial gate-count savings: A branch of CRC resources is configured to process back-to-back TLPs in a PCIe architecture. A state machine receives back-to-back TLPs and generates carrier signals, which it then routes to the branch of CRC resources. These signals are used to align the back-to-back TLPs such that a LCRC for each... Agent: Intellectual Property Law Group LLP

20070028153 - Information recording method, information recording system, drive control unit, and semiconductor integrated circuit: An information recording method for recording information on a recording medium having a volume space by a system including a drive control unit and a system control unit includes the steps of: the system control unit notifying the drive control unit of position information indicating a position of a spare... Agent: Snell & Wilmer L.L.P.

20070028154 - Valid-transmission verifying circuit and a semiconductor device including the same: A valid-transmission verifying circuit and a semiconductor device including the same are provided. The valid-transmission verifying circuit provides data to an output circuit in correspondence with reference data, the valid-transmission verifying circuit comprising: a data receiving terminal receiving the reference data; a valid-transmission verifier including a reference load unit configured... Agent: F. Chau & Associates, LLC

20070028155 - Flash memory device having single page buffer structure and related programming method: A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense... Agent: Volentine Francos, & Whitt PLLC

20070028156 - Method for detecting and correcting operating data errors: A method and apparatus for detecting errors within an incorrect media access control address and for preventing an Ethernet device from using the incorrect media access control address while it is fully operating. The method and apparatus can also correct some types of errors within the media access control address... Agent: Wall Marjama & Bilinski

20070028157 - Self-resetting, self-correcting latches: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate... Agent: Ibm Corporation (jvm)