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Error detection/correction and fault detection/recovery January USPTO class patent listing 01/07Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/25/2007 > 53 patent applications in 33 patent subcategories. USPTO class patent listing
20070022314 - Architecture and method for configuring a simplified cluster over a network with fencing and quorum: A host-clustered networked storage environment includes a “quorum program.” The quorum program is invoked when a change in cluster membership occurs, or when the cluster members are not receiving reliable information about the continued viability of the cluster, or for a variety of other reasons. When the quorum program is... Agent: Cesari And Mckenna, LLP
20070022315 - Detecting and reporting changes on networked computers: A method and system detects changes to the computers on a computer network, and reports these changes in a simple and useful format. Two compatible components are used, including a Local Agent that runs locally on each computer, and a Digester that is run centrally by a system administrator. Changes... Agent: Law Offices Of Ronald M Anderson
20070022313 - Notifications in a telecommunications network: In a telecommunications network in which a threshold crossing alert (TCA) notification is generated when a threshold set for a variable related to an object of a network element (NE) of the network is crossed, there is provided a method of identifying the object, comprising: creating an entry for the... Agent: Kirschstein, Ottinger, Israel & Schiffmiller, P.C.
20070022316 - Use of non-volatile memory to perform rollback function: A mechanism and method for maintaining a consistent state in a non-volatile random access memory system without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults, power loss, or other computer system failure without a loss of data or processing continuity. In a typical... Agent: Knobbe Martens Olson & Bear LLP
20070022317 - Method, system, and program for transmitting input/output requests from a first controller to a second controller: Provided are a method, system, and program monitoring paths between a first controller and second controller. A determination is made as to whether one path has been unavailable for a predetermined time period in response to detecting that the path is unavailable. Indication is made that the path is in... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20070022318 - Method and system for environmentally adaptive fault tolerant computing: A method and system for adapting fault tolerant computing. The method includes the steps of measuring an environmental condition representative of an environment. An on-board processing system's sensitivity to the measured environmental condition is measured. It is determined whether to reconfigure a fault tolerance of the on-board processing system based... Agent: Honeywell International Inc.
20070022319 - Maintaining and using information on updates to a data group after a logical copy is made of the data group: Provided are a method, system and program for maintaining and using information on updates to a data group after a logical copy is made of the data group. A first logical copy of a data group in a storage at a first point-in-time is established. The first logical copy maintains... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20070022320 - Support automation: An embodiment of a framework for servicing a client computer has a coordination engine and a data retrieval service for receiving a diagnostic data set from a client computer, an analysis service for analyzing said diagnostic data set and for generating a recommendation using the results of said analyzing. Functional... Agent: Hewlett Packard Company
20070022321 - Exception analysis methods and systems: Exception analysis methods for embedded systems. System exceptions from an embedded system with an operating system are received. Each system exception comprises first error code portion and second error code portion. The system exceptions are classified into error categories according to the first error code portion. The categories are based... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20070022322 - Fast data breakpoint emulation: A technique to implement software debugging capability using breakpoints includes creating breakpoints, storing them in a watchlist, and paging out a virtual address (VA) to physical address (PA) page entry in a translation look-aside buffer (TLB). When software under test is run at full speed, memory is accessed via the... Agent: Woodcock Washburn LLP (microsoft Corporation)
20070022324 - Multi-platform test automation enhancement: Embodiments of the present invention address deficiencies of the art in respect to host platform configuration for software testing and provide a novel and non-obvious method, system and computer program product for multi-platform test automation. In an embodiment of the invention, a multi-platform test automation data processing system can include... Agent: Ibm Corporation
20070022323 - Product framework for manufacturing testing environment: A software framework for centralizing the management of test plans, test configurations, test sources, debug information for testing electrical devices in a manufacturing testing environment is presented. A three-tier software architecture is defined that allows one-time effort and segregation of tasks related to integration of hardware devices, development of multiple... Agent: Agilent Technologies Inc.
20070022325 - Program, apparatus and method for verifying program: A program, an apparatus and a method verify a program that efficiently verifies a concurrent/parallel program, allowing interactively debugging the current/parallel program. The program causes a computer to execute a detection step that detects the function that has been altered and the function that uses a shared variable influenced by... Agent: Staas & Halsey LLP
20070022326 - Visual inspection of automatically-mounted component in circuit board assembly processes: A component is mounted onto a circuit board and is visually inspected after the circuit board is subjected to heat to determine whether the component has undergone a notable change in appearance. The component is preselected to have indicative characteristics after being subjected to heat. While the component is subjected... Agent: Lenovo (us)IPLaw
20070022327 - Computer-readable recording medium recording system performance monitoring program, and system performance monitoring method and apparatus: A computer-readable recording medium recording a system performance monitoring program for monitoring performance at desired timing and under desired conditions. A monitoring unit collects and stores status information indicating the operating statuses of servers in a status information memory. When other status information is necessary for evaluating performance, the monitoring... Agent: Patrick G. Burns Greer, Burns & Crain, Ltd.
20070022328 - Firmware update for consumer electronic device: To update firmware on a consumer device intelligently, two or more application images are stored as firmware on the consumer device. If the primary application image is corrupt, the back-up application image is executed on the consumer device. The back-up application image can be updated based on the primary application... Agent: Fenwick & West LLP
20070022329 - Shape matching method for indexing and retrieving multimedia data: The invention relates to a method for indexing and retrieving multimedia data. In particular the invention provides a method of comparing at least two sets of multimedia data using shape information in order to provides a dissimilarity measure between the sets. The invention finds use in retrieving images or parts... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20070022330 - Redundant column read in a memory array: A nonvolatile memory device requires no additional dummy bytes between receipt of a read instruction and a scanning out of data from a first target memory location requiring incorporation of redundant memory bits. A set of most significant redundant memory bits corresponding to a range of regular memory locations may... Agent: Schneck & Schneck
20070022331 - Single-ended ethernet management system and method: A single-ended Ethernet management system and method are provided. The system enables a user to provision and monitor an Ethernet interface, as well as to detect and isolate faults, from a single end. The method may be executed on the system to provide Ethernet services from a first end to... Agent: Haynes And Boone, LLP
20070022332 - Background block erase check for flash memories: Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.... Agent: Leffert Jay & Polglaze, P.A.
20070022335 - Methods and apparatus for interfacing between test system and memory: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least... Agent: Harness, Dickey & Pierce, P.L.C
20070022334 - Semiconductor device, test board for testing the same, and test system and method for testing the same: Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and... Agent: Mills & Onello LLP
20070022333 - Testing of interconnects associated with memory cards: Various systems and method for testing data interconnects are provided. In one method, a test data value is transmitted from an interconnect test tool to a memory card included in a memory card bank through a first set of interconnects. A received data value received by the memory card is... Agent: Hewlett Packard Company
20070022336 - Digital storage element with enable signal gating: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional... Agent: Texas Instruments Incorporated
20070022337 - Method and apparatus to verify non-deterministic results in an efficient random manner: The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a device under test. Such random accesses may more closely resemble actual accesses to the registers of a device during... Agent: Ibm Corporation, Intellectual Property Law Dept 917, Bldg. 006-1
20070022339 - Digital design component with scan clock generation: A master and a slave stage of a flip-flop are each separately clocked with non-overlapping clock signals during scan mode to eliminate a data input scan mode multiplexer. Separate, non-overlapping clocking permits the elimination of hold violations in scan mode for scan mode flip flop chains, permitting the elimination of... Agent: Texas Instruments Incorporated
20070022340 - Method and apparatus for determining stuck-at fault locations in cell chains using scan chains: Methods and apparatus are provided for testing digital circuits. In one implementation, a scan chain test structure is provided that includes a cell chain, a first scan chain, and a second scan chain. The first scan chain is operable to test digital circuitry within a first portion of the cell... Agent: Sawyer Law Group LLP
20070022341 - Method and system for protecting processors from unauthorized debug access: A method for securing a scan test architecture by performing an authentication operation to authorize use of a protected scan chain.... Agent: Wagner, Murabito & Hao, LLP
20070022338 - Sequential scan technique for testing integrated circuits with reduced power, time and/or cost: Each portion of an integrated circuit is tested using Automatic test pattern generation (ATPG) technique to detect intra-portion faults. Inter-portion faults are detected by first forming a scan chain containing (a) the memory elements in the fan-out of the inputs to each of said plurality of portions, (b) the memory... Agent: Texas Instruments Incorporated
20070022342 - Parallel test mode for multi-core processors: An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a... Agent: Blakely Sokoloff Taylor & Zafman
20070022343 - Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same: A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on... Agent: Banner & Witcoff, Ltd., Attorneys For Reserve Attorneys For Client No. 000449, 001701
20070022344 - Digital storage element architecture comprising dual scan clocks and gated scan output: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional... Agent: Texas Instruments Incorporated
20070022345 - Pseudo-random test generator in an integrated circuit: An integrated circuit with a multiplexer system and a control circuit is described. The multiplexer system has an output terminal connected to an output pin of the integrated circuit and input terminals connected to internal nodes of the integrated circuit. In a normal mode the control circuit generates the control... Agent: Aka Chan LLP
20070022346 - Test apparatus and test method: A test apparatus for testing a device under test 15 is provided. The test apparatus includes a driver 122 for applying a test signal to the device under test, a comparator 128 for comparing a result signal outputted by the device under test 15 corresponding to the applied test signal... Agent: Osha Liang L.L.P.
20070022348 - Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system: Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core... Agent: Blakely Sokoloff Taylor & Zafman
20070022347 - Systems, methods and computer programs for calibrating an automated circuit test system: In one embodiment, an automated circuit test system is calibrated by electrically coupling a first calibration unit between a plurality of drivers and comparators of the test system, and then executing an AC timing calibration procedure to determine a timing delay for each of a first set of relationships. A... Agent: Agilent Technologies Inc.
20070022349 - Test apparatus with tester channel availability identification: Automated semiconductor device tester apparatus includes a plurality of tester channels for devices under test. The apparatus includes an automated switching module, for switching an unused operative tester channel in the place of any tester channel found to be malfunctioning. The apparatus provides continued test operation irrespective of tester channel... Agent: Paul D. Greeley, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.
20070022350 - Built-in waveform edge deskew using digital-locked loops and coincidence detectors in an automated test equipment system: Although various embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without... Agent: Agilent Technologies Inc.
20070022351 - Method and apparatus that provide for configuration of hardware resources specified in a test template: In one embodiment, the execution of instructions causes a machine to: 1) display an automated test equipment (ATE) test template selection tool; 2) upon user selection of a test template from the ATE test template selection tool, display default parameters of the selected test template; and 3) provide user access... Agent: Agilent Technologies Inc.
20070022352 - Code design and implementation improvements for low density parity check codes for wireless routers using 802.11n protocol: Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM... Agent: The Directv Group Inc
20070022353 - Utilizing variable-length inputs in an inter-sequence permutation turbo code system: The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means... Agent: Volentine Francos, & Whitt PLLC
20070022357 - Apparatus selectively adopting different determining criteria in erasure marking procedure when performing decoding process, and method thereof: A method and a related apparatus that decode an input signal to generate an output signal. The method includes determining burst noise locations corresponding to the input signal and generating a first indication signal accordingly, decoding the input signal to generate an inner-code decoded signal, selectively adopting one of a... Agent: North America Intellectual Property Corporation
20070022356 - Input control device and input control method: An input control apparatus capable of suppressing characteristic deterioration, reducing the circuit scale of a turbo decoder and effectively using memory of the turbo decoder. In this apparatus, control section (110) acquires information on a coding rate and coding block length of a received signal, determines the number of bits... Agent: Stevens, Davis, Miller & Mosher, LLP
20070022354 - Method for encoding low-density parity check code: An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20070022355 - Method, an encoder and communication device for individually encoding code block segments: A method of encoding data in a code block comprising an information bit sequence in a communication device of a communication system comprising the step of separating the information bit sequence into a plurality of subsets of information bits. Each subset forming a code block segment Further, the method comprises... Agent: Stevens, Davis, Miller & Mosher, LLP
20070022358 - Methods and apparatuses for generating error correction codes: Methods and apparatuses for generating error correction codes of a data block are disclosed. One proposed method includes: storing a plurality of calculating data corresponding to the error correction codes in a buffer; generating operating results according to the calculating data from the buffer and corresponding data of the data... Agent: North America Intellectual Property Corporation
20070022359 - Data storage device and data processing method: The exclusive OR (XOR) of user data (sector) 0, user data (sector) 1 and user data (sector) 2 is taken to have the virtual user data, thereby giving rise to a correlation of the sectors 0 to 2, and its virtual user data is appended with C2 having a greater... Agent: Harrington & Smith, L.L.P.
20070022360 - Method and apparatus to lower operating voltages for memory arrays using error correcting codes: A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes on the data... Agent: Marger Johnson & Mccollom, P.C.
20070022361 - Method and system for optimizing forward error correction of multimedia streaming over wireless networks: The loss of packets in a communication system can be minimized in an optimal manner by adapting a set of error correction (EC) parameters in response to a calculated probability of packet loss. The calculated probability is obtained from derived algorithms that are applied to a set of communication parameters.... Agent: Gallagher & Lathrop, A Professional Corporation
20070022362 - Rate-compatible low density parity check coding for hybrid arq: A new rate compatible coding approach is disclosed herein which takes advantage of the structure of irregular repeat accumulate (IRA) type codes, a special class of low density parity check codes.... Agent: Nec Laboratories America, Inc.
20070022363 - Redundant 3-wire communication system and method: A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data... Agent: Carey, Rodriguez, Greenberg & Paul, LLP Steven M. Greenberg
20070022364 - Data management architecture: A performance optimized RAID Level 3 storage access controller with a unique XOR engine placement at the host/network side of the cache. The invention utilizes multiple data communications channels and a centralized cache memory in conjunction with this unique XOR placement to maximize performance and fault tolerance between a host... Agent: Blakely Sokoloff Taylor & Zafman
20070022365 - Out-of-band change detection: An automated method for facilitating management of a data processing environment is disclosed. In various embodiments, the method may include facilitating creation of a first memorialization, in digital form, of one or more changes detected on a data processing device of the data processing environment. In various embodiments, the method... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 190001/18/2007 > 22 patent applications in 18 patent subcategories. USPTO class patent listing
20070016822 - Policy-based, cluster-application-defined quorum with generic support interface for cluster managers in a shared storage environment: A system, method and computer program product for use in a server cluster having plural server nodes implementing a server tier in a client-server computing architecture in order to determine which of two or more partitioned server subgroups has a quorum. A determination is made of relative priorities of the... Agent: Walter W. Duft
20070016823 - Duplicated double checking production rule set for fault-tolerant electronics: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing... Agent: Wall Marjama & Bilinski
20070016824 - Methods and apparatus for global systems management: Techniques for globally managing systems are provided. One or more measurable effects of at least one hypothetical action to achieve a management goal are determined at a first system manager. The one or more measurable effects are sent from the first system manager to a second system manager. At the... Agent: Ryan, Mason & Lewis, LLP
20070016825 - Resource allocation aware queuing of requests for media resources: Resource allocation aware processing of requests for media resources is disclosed. A queue is defined. A media resource is allocated to the queue. A media resource request is associated with the queue.... Agent: Van Pelt, Yi & James LLP
20070016826 - Configurable memory architecture with built-in testing mechanism: A configurable memory architecture includes a built-in testing mechanism integrated in said memory to support very efficient built-in self-test in Random Access Memories (RAMs) with greatly reduced overhead, in terms of area and speed. Memories can fail at high speed due to glitches (unwanted pulses which can at times behave... Agent: Jenkens & Gilchrist, PC
20070016827 - Systems and methods for providing remotely accessible in-system emulation and/or debugging: An information handling system providing remotely accessible in-system debugging functionality is provided. The information handling system may include a first logic device and a remote access card distinct from the first logic device. The remote access card may include a network interface port, a processor, and a second logic device.... Agent: Baker Botts, LLP
20070016830 - Method and system for tracking software components: A method system for tracking the state of an entity (e.g., an object) on behalf of a client (e.g., an application program). The states of an entity include up and down. The tracking system of the present invention receives a request from a client to track the state of an... Agent: Woodcock Washburn LLP (microsoft Corporation)
20070016828 - Push-to-talk communications in computing environments: Described is a communication mechanism that provides push-to-talk functionality for mobile and desktop computing environments. Mobile and desktop computers are configured as client computers in a client/server architecture. Some of the client computers are configured to handle multiple push-to-talk sessions simultaneously. If multiple streams from different sessions are active at... Agent: Lee & Hayes PLLC
20070016829 - Test case generator: A test system for software includes a test case generator, which produces test cases, and a test framework, which executes the test cases. The test case generator represents test cases as actions to be performed. Actions for inclusion in a test case are selected by a rule-based inference engine applying... Agent: Wolf Greenfield (microsoft Corporation) C/o Wolf, Greenfield & Sacks, P.C.
20070016831 - Identification of root cause for a transaction response time problem in a distributed environment: Method and apparatus for identifying a cause for a response time problem for a transaction in a distributed computing system that includes a central server and a plurality of subsystems. Data is stored at each subsystem relating to sub-transactions of transactions performed by the subsystems. When a problem is discovered... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20070016832 - System, device and method of verifying that a code is executed by a processor: Some demonstrative embodiments of the invention include a method, device and/or system of verifying that a secure code is executed by a processor. The device may include, for example, a memory to store a secure code; a processor intended to execute a gating code, wherein the gating code, when executed... Agent: Pearl Cohen Zedek, LLP Pearl Cohen Zedek Latzer, LLP
20070016833 - Method for performing built-in and at-speed test in system-on-chip: A method for performing a built-in and at-speed test in a system-on-chip includes receiving a statistic timing analysis report of the system-on-chip, determining a plurality of critical paths for an at-speed test in the system-on-chip according to the statistic timing analysis report, analyzing signals at observe control points and capture... Agent: North America Intellectual Property Corporation
20070016834 - Reducing power dissipation during sequential scan tests: A scan cell which provides two data outputs, one of use in scan mode and another in functional mode. The functional mode output is connected to functional portions, and transitions on the functional mode output are avoided by using an isolation circuit. As a result, the inputs in functional portions... Agent: Texas Instruments Incorporated
20070016835 - Method and apparatus for parameter adjustment, testing, and configuration: A method and apparatus for parameter monitoring, adjustment, testing, and/or configuration of devices have been disclosed.... Agent: Heimlich Law
20070016836 - Test pattern compression for an integrated circuit test environment: A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the... Agent: Klarquist Sparkman, LLP
20070016837 - Computer-implemented method for correcting transmission errors using linear programming: A computer-implemented method for correcting transmission errors. According to the method, a transmitted vector corrupted by error can be recovered solving a linear program. The method has applications in the transmission of Internet media, Internet telephony, and speech transmission. In addition, error correction is embedded as a key building block... Agent: Alessandro Steinfl, Esq. C/o Ladas & Parry
20070016838 - Adaptive hybrid arq systems with bcjr decoding: A method and an apparatus of constructing hybrid Automatic Repeat reQuest (ARQ) systems using specific properties of the BCJR error correcting algorithm. Since the convergence to an actual codeword is not always guaranteed with the BCJR, the method and apparatus implements a system, in which two different types of Negative... Agent: Christensen, O'connor, Johnson, Kindness, PLLC
20070016839 - Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method: An apparatus for error-correcting an input signal to generate an output signal. The apparatus includes an unreliable-location determining module for determining unreliable-locations of the input signal and generating an indication signal accordingly, a first error-correcting module for error-correcting the input signal to generate a first candidate signal, a second error-correcting... Agent: North America Intellectual Property Corporation
20070016840 - Method for checking the safety and reliability of software-based electronic system: A method for checking the safety and reliability of software-based electronic systems, using a reliability function for checking the functions of the system that are called for, based on the hardware components of the system required for this. In this connection it is provided that a reliability function is determined... Agent: Kenyon & Kenyon LLP
20070016841 - Variable code rate and signal constellation turbo trellis coded modulation codec: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively... Agent: Garlick Harrison & Markison
20070016842 - Method and apparatus for configuring a cyclic redundancy check (crc) generation circuit to perform crc on a data stream: A method and apparatus for configuring a cyclic redundancy check (CRC) generation circuit to perform CRC on a data stream are disclosed. The method includes storing a generator polynomial associated with a CRC equation in a register, where the generator polynomial has a length capable of varying such that the... Agent: Baker Botts L.L.P. Patent Department
20070016843 - Ecc for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.... Agent: Graybeal Jackson Haley LLP01/11/2007 > 22 patent applications in 18 patent subcategories. USPTO class patent listing
20070011485 - Application-based specialization for computing nodes within a distributed processing system: A distributed processing system is described that employs “application-based” specialization. In particular, the distributed processing system is constructed as a collection of computing nodes in which each computing node performs a particular processing role within the operation of the overall distributed processing system. Each of the computing nodes includes an... Agent: Shumaker & Sieffert, P. A.
20070011484 - Testing a data-processing system with telecommunications endpoints: A method and apparatus are disclosed that provide a technique for testing a data-processing system that enables communications between two or more telecommunications endpoints. An example of such a data-processing system is a Session-Initiation Protocol (SIP) proxy server. In particular, a test-execution system, in accordance with the illustrative embodiment of... Agent: Demont & Breyer, LLC
20070011486 - Apparatus and method for cooperative guest firmware: A method and apparatus for cooperative guest firmware are described. In one embodiment, the method includes the launch of a virtual machine (VM) including a guest operating system (OS) and guest firmware. Prior to launching the VM, a data structure is generated in memory and is associated with the guest... Agent: Blakely Sokoloff Taylor & Zafman
20070011487 - Method and infrastructure for recognition of the resources of a defective hardware unit: A system and method of recognizing resources of a computer comprising a system serial number and a broken hardware unit comprising a non-volatile memory unit and enablement definition data relating to functions of the broken hardware unit, wherein the method comprises starting the computer; entering a serial number in a... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC
20070011488 - Storage system, adapter apparatus, information processing apparatus and method for controlling the information processing apparatus: An information processing apparatus that enables easy identification of the cause of failure. The information processing apparatus has a transfer unit for transferring data between first equipment and second equipment. The information processing apparatus further includes an collection unit for collecting data that passes between the first equipment and the... Agent: Antonelli, Terry, Stout & Kraus, LLP
20070011489 - Command processing method for raid: A command processing method for an RAID is performed when a usable memory of a system is smaller than a size of a command. The command processing method for the RAID includes the following steps of: dividing the command into a plurality of segmented commands, transmitting the segmented commands to... Agent: Birch Stewart Kolasch & Birch
20070011490 - Information processing apparatus, and method of controlling operation of the same: According to one embodiment, An information processing apparatus includes: a managing section that manages a plurality of correspondences between each of a plurality of combinations of a plurality of recording devices and each of a plurality of data backup procedures; a detecting section that detects a connection of any of... Agent: Pillsbury Winthrop Shaw Pittman, LLP
20070011491 - Method for platform independent management of devices using option roms: A method for platform independent management of devices using option ROMs. Under one embodiment of the method, manageability data is stored in an option ROM of a peripheral device of a computer platform. The manageability data includes a descriptor that provides an identity, data type, access method and potentially other... Agent: Blakely Sokoloff Taylor & Zafman
20070011492 - Generation of trace data: An apparatus and method for processing data is disclosed. The apparatus comprises a data processing circuit operable over a sequence of processing cycles to perform data processing operations in response to program instructions and a tracing circuit configurable to perform a selected one of a number of tracing activities in... Agent: Nixon & Vanderhye, PC
20070011493 - Method for renovating the computer operating system: The present invention provides a method for restoring a computer operation system comprising at least steps of: a) backing up information related to start up of the computer in an HPA of a hard disk; b) providing a self-checking module in the HPA of the hard disk, and additionally configuring... Agent: Dickstein Shapiro LLP
20070011494 - System and method for building software package for embedded system: A method and system for building an embedded software package for a target system including creating a cross-compiling stub in the target system, wherein the stub accesses a compiling tool at a remote location, starting a software package building process at the target system, and intercepting a compiling command coming... Agent: Anne Vachon Dougherty
20070011495 - Cluster availability management: A first logical partition in a first processing complex of a server cluster is operated in an active mode and a second logical partition in the processing complex is operated in a standby mode. Upon detection of a failure in a second processing complex of the server cluster. the standby... Agent: Konrad Raynes & Victor, LLP. Attn: Ibm37
20070011496 - Method and system for design and analysis of fastened joints: A computer system for analyzing fasteners and fastened joints includes a display and a processor. The processor may be configured to provide a first interface and a second interface to the display, and receive, via the first or second interface, a set of parameters associated with a component to be... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20070011497 - System and method for economizing trace operations: A system and method of creating trace information of an application. Trace data of the application is stored in a trace heap. Processing of stored trace data including a hard-coded string is deferred.... Agent: Senniger Powers (msft)
20070011498 - Method and system for using presence information in error notification: A method for using presence information in error notification includes detecting an error associated with operation of a software system and executing a workflow in response to detecting the error to determine error transmission information instructions. The method includes using presence information to identify one or more targets for receipt... Agent: Baker Botts L.L.P.
20070011499 - Methods for ensuring safe component removal: The invention includes a method for determining whether a node in a non-recursive network can be removed. The method includes the steps of executing a reachability algorithm for a resource of a system upon initialization of the system. The resource is accessible to the system upon the initialization. A safe... Agent: Kirkpatrick & Lockhart Nicholson Graham LLP
20070011500 - System and method for using hot plug configuration for pci error recovery: A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive... Agent: Dillon & Yudell LLP
20070011501 - Long term data protection system and method: A file to be written can be partitioned into one or more partitions. Each such input partition is identified with a hash code and a group ID. Replica(s) of an input partition can be created to ensure a certain number of identical partitions. When a file is accessed, each partition... Agent: Townsend And Townsend And Crew, LLP
20070011502 - Structured interleaving/de-interleaving scheme for product code encoders/decoders: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column... Agent: Mendelsohn & Associates, P.C.
20070011503 - Communication terminal: A communication terminal optimally switches between the use of multicast reception and unicast reception, in consideration of the mobile radio environment of each terminal. For example, received signal strength indicator information is acquired at a received signal strength indicator information acquisition time calculated using a content reception time. Either multicast... Agent: Cohen, Pontani, Lieberman & Pavane
20070011504 - Method for reporting reception result of packets in mobile communication system: Disclosed is a method for configuring a bitmap in a mobile communication system employing a block ACK scheme, which faithfully performs its intrinsic function of acknowledging a reception result, and yet can reduce transmission delay and the overall system load due to retransmission in the case where packet loss is... Agent: Dilworth & Barrese, LLP
20070011505 - Information recording medium, recording device and recording method for information recording medium, reproduction device and reproduction method for information recording medium, computer program for recording or reproduction, and data structure containi: An information recording medium (100) is provided with: a user data area (108) for recording therein record data; a plurality of temporary defect management areas (104, 105) for temporarily recording therein defect management information (120) which is a basis of defect management for a defect in the data area; and... Agent: Young & Thompson
20070011506 - Semiconductor integrated circuit verifying and inspecting method: A method of verifying a semiconductor integrated circuit according to the invention does not compare expected values based on a strobe every cycle but executes a verification on the basis of a signal transition (change) point. At the same time, the verifying method is intended for verifying a path in... Agent: Mcdermott Will & Emery LLP
20070011509 - Bitmap cluster analysis of defects in integrated circuits: A system and method for defect analysis are disclosed wherein a defect data set is input into the system. A radius value is selected by a user, which is the maximum number of bits that bit failures can be separated from one another to be considered a bit cluster. When... Agent: William C. Milks, Iii Russo & Hale LLP
20070011511 - Built-in self-test method and system: A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the... Agent: Seed Intellectual Property Law Group PLLC
20070011510 - Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories): A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register.... Agent: Dicke, Billig & Czaja, P.l.l.c.
20070011507 - System and method for remote system support: In some embodiments, the invention involves a system and method relating to out-of-band debugging of a platform. In at least one embodiment, the present invention enables a debugger to operate during any operational phase of the platform. Specifically, the debugger may operate during pre-boot, before memory initialization and through to... Agent: Blakely Sokoloff Taylor & Zafman
20070011508 - Time controllable sensing scheme for sense amplifier in memory ic test: A test method is described in which a signal from a tester enters a memory chip or memory module into a special test mode. The special test mode allows leakage defects connected to bit lines to be detected using bit line sense amplifiers. A first test command is issued by... Agent: Stephen B. Ackerman
20070011512 - Semiconductor memory device and control method for the semiconductor memory device: A memory cell array for memorizing data with any of 0th through fourth threshold voltages and a flag memory unit for memorizing a flag data showing a chronological sequence relationship between writing operations in which data in first and second pages are respectively written are provided. A controller shifts a... Agent: Mcdermott Will & Emery LLP
20070011513 - Selective activation of error mitigation based on bit level error count: Embodiments of apparatuses and methods for selective activation of error mitigation based on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality of state elements, an error counter, and activation logic. The error counter is to count the number of bit level errors in the... Agent: Blakely Sokoloff Taylor & Zafman
20070011514 - Data compression: A method and apparatus for compressing test vector data for use in testing a logic product, wherein original test vector data is generated in the form of two or more sequences of bits including “care” bits and “don't care” bits. The test vector data is then compressed by comparing corresponding... Agent: Philips Intellectual Property & Standards
20070011517 - Debug system for data tracking: Some embodiments provide configuration of an internal monitoring mechanism of a processing device to output first data associated with a predetermined operational state of the processing device, and loading of control code into the processing device. The control code may be executable by the processing device to output second data... Agent: Buckley, Maschoff, Talwalkar LLC
20070011520 - Element substrate, test method for element substrate, and manufacturing method for semiconductor device: A test circuit and a test method using a plurality of oscillation circuits for evaluation are provided in order to reduce the measuring time and simplify the test. One measuring terminal is shared by a plurality of oscillation circuits for evaluation that are formed over the same substrate as a... Agent: Fish & Richardson P.C.
20070011521 - Integrated scannable interface for testing memory: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal... Agent: Hogan & Hartson LLP
20070011518 - Method and apparatus for selectively accessing and configuring individual chips of a semi-conductor wafer: A method and apparatus according to the present invention enable wafer chips to be configured with a single power on and off sequence and further enable a chip parameter to be adjusted during a wafer test without utilizing that sequence. In particular, each wafer chip under test is assigned a... Agent: Edell, Shapiro & Finnan, LLC
20070011516 - Method and apparatus to launch write queue read data in a microprocessor recovery unit: A method of checkpointing a microprocessor by providing, in parallel, a current read value from a queue and a next read value from the queue, and then selectively passing one of the current read value and next read value to a capture latch based on an instruction completion signal. The... Agent: Ibm Corporation (jvm)
20070011519 - Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system: A failure analysis apparatus 10 is composed of an inspection information acquirer 11 for acquiring at least a pattern image P1 of a semiconductor device, a layout information acquirer 12 for acquiring a layout image P3, a failure analyzer 13 for analyzing a failure of the semiconductor device, and an... Agent: Drinker Biddle & Reath (dc)
20070011515 - System and method for evaluating an expression in a debugger: When an expression is first entered into a debugger, the expression may be automatically evaluated. Later, when the debugger detects an action that causes the value of the expression to become stale, the expression may be reevaluated with a setting to disable the automatic reevaluation of certain designated disabled expressions.... Agent: Woodcock Washburn LLP (microsoft Corporation)
20070011522 - System and methods for functional testing of embedded processor-based systems: Functional testing of an embedded system is performed by a test control system that implements a peripheral emulation module to interface with an externally accessible port of the embedded system. The test control system implements a test generation processor that operates to autonomously resolve abstracted component templates and embedded system... Agent: Gerald B Rosenberg New Tech Law
20070011527 - Generating responses to patterns stimulating an electronic circuit with timing exception paths: Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing... Agent: Klarquist Sparkman, LLP
20070011523 - Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chain: A method, apparatus and computer program product are provided implementing a scan chain diagnostics technique. The diagnostics technique includes employing fuses coupled to latches of the scan chain to load a known logic value into the latches at known locations of the scan chain, and then unloading values from the... Agent: Kevin P. Radigan, Esq. Heslin Rothenberg Farley & Mesiti, P.C.
20070011526 - Position independent testing of circuits: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided... Agent: Texas Instruments Incorporated
20070011524 - Scan test circuit and method of arranging the same: Replaced cell CELL1 is composed of clock buffer circuit CB1 and flip-flop circuit FF1 that latches data at a falling-down time of a clock signal. Clock buffer circuits CB1a-CB1d are cascade-connected to form a clock tree circuit. A scan circuit is composed of scan flip-flop circuits SFF1-SFF4. Replaced cell CELL1... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070011525 - Semiconductor integrated circuit and control method thereof: A semiconductor integrated circuit according to the present invention has a logical circuit network that implements predetermined processing, a plurality of scan chains that are penetrated through the logical circuit network and test the logical circuit network in a plurality of test modes, a plurality of shared terminals that share... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070011528 - Method and apparatus for testing an ultrasound system: A medical imaging system is provided that includes a plurality of circuit boards configured to be tested using boundary scan test vectors. A controller of the medical imaging system is configured to test the plurality of circuit boards. The controller is further configured to access test profiles to perform boundary... Agent: The Small Patent Law Group LLP
20070011529 - Semiconductor device and test method thereof: An LSI has bidirectional buffers connected to a boundary scan circuit. The boundary scan circuit 12 has asynchronous setting circuits for setting each bidirectional buffer to input mode or output mode. The bidirectional buffers are asynchronously and uniformly set to output mode to detect a logic error. If there is... Agent: Mcginn Intellectual Property Law Group, PLLC
20070011530 - Decompressor/prpg for applying pseudo-random and deterministic test patterns: A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under... Agent: Klarquist Sparkman, LLP
20070011531 - Methods and apparatus for managing clock skew between clock domain boundaries: Methods and apparatus provide for: a plurality of stages of combinational logic, each stage including a full latch circuit operable to transfer data into the given stage of combinational logic and a transparent latch circuit operable transfer output data from the given stage of combinational logic to a next of... Agent: Kaplan Gilman Gibson & Dernier L.L.P.
20070011532 - Semiconductor chip and semiconductor integrated circuit device: A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to... Agent: Mcginn Intellectual Property Law Group, PLLC
20070011533 - Method and apparatus for reducing number of transitions generated by linear feedback shift register: A method for reducing the number of transitions generated by an LFSR is introduced. The transition monitoring window monitors the number of transitions occurring as random patterns generated from an LFSR are applied to a scan chain, and, if the number of transitions exceeds a threshold value (“k-value”), all further... Agent: Gwips Peter T. Kwon
20070011534 - Self-synchronising bit error analyser and circuit: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by... Agent: International Business Machines Corporation Dept. 18g
20070011536 - Automated bist execution scheme for a link: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted,... Agent: Blakely Sokoloff Taylor & Zafman
20070011538 - Circuit and method for performing built-in self test and computer readable recording medium for storing program thereof: A circuit and a method for built-in self test (BIST) and a computer readable recording medium for storing program thereof are provided. The BIST circuit serves a system to self test a circuit-under-test in the system. The system further includes a unit circuit having a plurality of input terminal couple... Agent: Jianq Chyun Intellectual Property Office
20070011539 - Self test structure for interconnect and logic element testing in programmable devices: A self test structure for interconnect and logic element testing in programmable devices including a plurality of logic elements; an interconnect structure for connecting the logic elements; SRAM based configuration latches for configuring the interconnect structure; test configuration circuitry for configuring any desired set of logic elements, interconnect structure and... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, PC
20070011535 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a plurality of memories; a BIST circuit configured to test at least one of the memories; and a plurality of shift circuits connected to each of the memories, each of the shift circuits shifts one of first data bits obtained from at least one of... Agent: Dla Piper Rudnick Gray Cary Us, LLP
20070011537 - Systems and methods for self-diagnosing lbist: Systems and methods for performing logic built-in self-tests (LBISTs) in digital circuits. In one embodiment, a system has first and second target logic, each of which has LBIST circuitry incorporated therein. The system also includes comparison circuitry which is coupled to the first and second LBIST circuitry. The comparison circuitry... Agent: Law Offices Of Mark L. Berrier
20070011540 - Telecommunications network testing: On a test apparatus for a telecommunication network a plurality of quality rules are defined as a function of the results of counts of events for a plurality of test parameters. The events relating to the plurality of test parameters during the performance of a test are counted. A plurality... Agent: Tektronix, Inc.
20070011541 - Methods and systems for identifying intermittent errors in a distributed code development environment: A distributed code development environment includes baseline code that is logically divided into a plurality of labels, each including a plurality of transactions authored by respective developers. A computer-implemented method for identifying intermittent errors in the baseline and determining whether errors generated by a test of transactions are intermittent or... Agent: Young Law Firm, P.C.
20070011542 - Reduced-pin-count-testing architectures for applying test patterns: Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary nonlimiting embodiment, a circuit is disclosed... Agent: Klarquist Sparkman, LLP
20070011543 - Test pattern generation method: A high-quality test pattern for testing a delay fault is generated at a high speed. In order that a second test pattern provided at a test cycle that follows a test cycle should be generated, a fault value set up in a circuit is propagated to an observation point. At... Agent: Mcdermott Will & Emery LLP
20070011546 - Ic output signal path with switch, bus holder, and buffer: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).... Agent: Texas Instruments Incorporated
20070011544 - Reprogramming of tester resource assignments: A method including creating a mapping file and a package test program for testing an electronic package. The package comprises a device. The package test program comprises source code for a device test program for testing the device and source code from the mapping file. The device test program source... Agent: Agilent Technologies Inc.
20070011545 - System and method for testing a nas: A system for testing a NAS includes: a data storage device (3) connected with a NAS (6) for storing function test program and test data; a host computer (1) connected with the NAS being used to issue commands for the NAS to self-test itself via the function test program and... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp
20070011552 - Auxiliary data transmitted within a display's serialized data stream: Techniques to transmit auxiliary data are disclosed. One technique includes generating a control signal from a video data enable signal and an auxiliary data enable signal, and combining an auxiliary data signal and a video data signal into a composite data signal using the control signal. Techniques to receive the... Agent: Perkins Coie LLP
20070011548 - Centralized error signaling and logging: A device, method, and system are disclosed. In one embodiment, the device comprises one or more error receiving units, each operable to receive error requests from a given layer in a protocol and synchronize the received error requests to a common clock domain for all layers, and an arbiter unit... Agent: Blakely Sokoloff Taylor & Zafman
20070011547 - Method and apparatus for detecting and fixing faults in an inline-power capable ethernet system: Methods and apparatus are disclosed for detecting ground faults in an Ethernet system. An Ethernet switch is configured to provide inline power to a plurality of ports each having positive and negative rails. Current is injected into selected rails of a port and ground isolation is temporarily broken for the... Agent: Sierra Patent Group, Ltd.
20070011553 - Method and apparatus of memory management: A method and apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and a quality indicator value related to at... Agent: Pearl Cohen Zedek Latzer, LLP
20070011549 - Providing high availability in a pci-express™ link in the presence of lane faults: A method, device, and system are disclosed. In one embodiment, the method comprises discovering a failure on a PCI Express interconnect, determining whether a failure override bit has been set to override the standard PCI Express Polling.Compliance state for the failure on the PCI Express interconnect, and if the failure... Agent: Blakely Sokoloff Taylor & Zafman
20070011550 - Rank step-down for mimo scw design employing harq: Systems and methodologies are described that facilitate reducing rank (e.g., of a user device) as a number of transmissions there from increases. Such rank step-down can improve interference resistance and facilitate maintaining code rate despite transmission propagation. Additionally, rank step-down information can be encoded along with CQI information to generate... Agent: Qualcomm Incorporated
20070011551 - Signal, storage medium, method and device for encoding, method and device for decoding: The invention relates to a signal comprising a runlength limited (RLL) encoded binary d,k channel bitstream 3, wherein parameter d defines a minimum number and parameter k defines a maximum number of zeroes between any two ones of said bitstream 3 or vice versa, comprising a number of sections of... Agent: Philips Intellectual Property & Standards
20070011555 - Apparatus and method for transmitting/receiving broadcast data in a mobile communication system: A method and apparatus for transmitting a broadcast physical layer packet in a mobile communication system supporting multi-slot transmission and hybrid Automatic Repeat Request (H-ARQ) are provided. The method comprises initially transmitting the broadcast physical layer packet according to a fixed transmission format for at least one first slot interval... Agent: Roylance, Abrams, Berdo & Goodman, L.L.P.
20070011554 - Block acknowledgement request apparatus, systems, and methods: Embodiments of block acknowledgements request apparatus, systems, and methods are generally described herein. Other embodiments may be described and claimed. An originator operating in a frame-aggregating mode sends a multiple-frame data block to a receiver. The block may include a header for each frame. The header may have an indicator... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20070011557 - Inter-sequence permutation turbo code system and operation methods thereof: A high performance real-time turbo code system is proposed. The proposed system exploits cooperative coding architecture and a proper decoding scheduling to achieve low error rate within a constrained latency. Permutation schemes and hardware embodiments utilizing the cooperative coding are also shown. Various memory saving techniques are provided to reduce... Agent: Ladas & Parry
20070011556 - Media packet structure for real time trasnmission via packet switched networks: The present invention proposes a media packet structure comprising an insensitive part (ISP) comprising a block of media data (BMD) and a sensitive part (SP), said sensitive part being protected by a checksum (CS), said sensitive part comprising error correction codes (FEC) for correcting the block of media data (BMD)... Agent: Philips Intellectual Property & Standards
20070011559 - Dynamic minimum-memory interleaving: Minimum-memory-implementation is available with any depth and period in DSL interleaving/deinterleaving, always allowing the minimum amount of memory to be used in both transmitter and receiver without loss of performance or of basic triangular structure, even if the interleaver/deinterleaver parameters change dynamically. A novel cell-scheduling process ensures availability of the... Agent: Sylke Law Offices, LLC
20070011558 - Methods and apparatus to extract codes from a plurality of channels: Methods and apparatus to extract audio codes are disclosed. An example method includes receiving signals on a plurality of channels and ranking the signals based on at least one characteristic of the signals. A first channel from the plurality of channels is selected based upon the ranking of the signals.... Agent: Hanley, Flight & Zimmerman, LLC
20070011568 - hardware-efficient low density parity check code for digital communications: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclosed. The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc).... Agent: Texas Instruments Incorporated
20070011570 - Apparatus and method for transmitting/receiving data in a communication system using structured low density parity check code: Provided is an apparatus and method for transmitting/receiving data in a communication system using a structured Low Density Parity Check (LDPC) code. The transmitter performs structured LDPC coding on input information data using a structured LDPC code, parallel-converts a structured LDPC codeword generated by performing the structured LDPC coding, in... Agent: Dilworth & Barrese, LLP
20070011566 - Clash-free irregular-repeat-accumulate code: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix... Agent: Townsend And Townsend And Crew, LLP
20070011572 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070011571 - Iterative method of decoding a received signal: An iterative method and a device (20) for decoding received signals (21) transmitted in data frames via various channels (A, B). In order to be able to utilize the computing capacity of digital signal processors (DSPs) as efficiently as possible, it is proposed that, starting at a first channel (A;... Agent: Sughrue Mion, PLLC
20070011561 - Method and apparatus for data transfer: A data management layer of a layered protocol system and a method of transmitting data. The data management layer including: a cyclic redundancy check generator connected to a retry buffer through a multiplexer; a sequence number generator connected to the retry buffer through the multiplexer; means for generating a sequence... Agent: Schmeiser, Olsen & Watts
20070011565 - Method and apparatus for low-density parity check encoding: A method of improving the error correcting performance using low-density parity check (LDPC) encoding includes, making an LDPC matrix by arranging non-zero matrices in a series of blockwise columns not to overlap with one another, making at least one LDPC codeword block by generating parity information based on the LDPC... Agent: Stein, Mcewen & Bui, LLP
20070011560 - Method and system for performing fast checksum operations in a gprs communication system utilising tunnelling: Methods have been provided for accomplishing fast checksum operations for various nodes in a GPRS network. According to one embodiment of the invention a method is provided for performing tunnelling wherein, a first packet (J) is received having a stored first checksum value (HC J) covering at least portions of... Agent: Ericsson Inc.
20070011567 - Method for padding and puncturing low density parity check code: Disclosed is a method for puncturing a Low Density Parity Check (LDPC) code that is expressed by a factor graph having a check node and a variable node, connected to each other by an edge, and is decoded by a parity check matrix including a parity part having a single... Agent: Dilworth & Barrese, LLP
20070011562 - Mitigating silent data corruption in a buffered memory module architecture: Embodiments of the invention are generally directed to systems, apparatuses, and methods for mitigating silent data corruption in a fully-buffered memory module architecture. In an embodiment, a memory controller includes a memory channel bit-lane error detector having an M-bit CRC and N-bit CRC, wherein N is less than M. The... Agent: Blakely Sokoloff Taylor & Zafman
20070011564 - Multi-channel ldpc decoder architecture: A multi-channel decoder system has a decoder core, at least a portion of which comprises or is configurable as a LDPC decoder, a plurality of channels to and from the decoder core, and control logic for controlling application of the decoder core to data carried by one or more of... Agent: Howrey LLP
20070011563 - Shared redundancy in error correcting code: A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundancy symbols. Shared redundancy symbols are generated for the cooperative... Agent: Seagate Technology LLC C/o Westman Champlin & Kelly, P.A.
20070011569 - Variable-rate low-density parity check codes with constant blocklength: Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blocklength as the higher-rate LDPC matrix.... Agent: Gates & Cooper LLP Howard Hughes Center
20070011573 - Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining: A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receive a first codeword from the input buffer and process the first... Agent: Sawyer Law Group LLP
20070011575 - Autonomous method and apparatus for mitigating soft-errors in integrated circuit memory storage devices at run-time: Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device... Agent: Terry W. Kramer Kramer & Amado, P.C.
20070011576 - Data managing method and optical disc drive for handling an decoding error of a readback data retrieved from an optical disc: A data managing method and optical disc drive capable of handling decoding errors of readback data retrieved from an optical disc. The data managing method includes providing a buffering pointer and a decoding pointer; utilizing the buffering pointer to indicate an address utilized for storing an un-decoded readback data; controlling... Agent: North America Intellectual Property Corporation
20070011580 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks.... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070011574 - Memory device: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are... Agent: Edell, Shapiro & Finnan, LLC
20070011578 - Reducing false positives in configuration error detection for programmable devices: A device reduces false positive memory error detections by using a masking unit and sensitivity mask data to exclude unused portions of the memory from the error detection computations. A device includes an error detection unit to read data from the memory and verify data integrity. The sensitivity mask data... Agent: Townsend And Townsend And Crew LLP/ 015114
20070011579 - Storage system, management server, and method of managing application thereof: In a storage system having a plurality of disk array devices connected through a network to a host for running an application, and a management server for monitoring the disk array devices, the disk array device includes a physical disk error detecting unit for detecting an error in a physical... Agent: Townsend And Townsend And Crew, LLP
20070011577 - Trie-type memory device with a compression mechanism: The invention relates to a tri-type memory device comprising a compression mechanism. According to the invention, the memory stores binary patterns that are associated with respective references. Data chains are analyzed by successive section of K bits (K>1) in order to extract one of the references when there is a... Agent: Holland & Knight LLP
20070011582 - Error correction device of optical disk unit: An error correction device for an optical disk unit is an error correction device of the optical disk reproduction unit for reproducing recorded information from the optical disk recorded with a code row data added with an error code in the same direction as a sequence of recorded information in... Agent: C. Irvin Mcclelland Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.
20070011581 - Memory controller, nonvolatile memory device, nonvolatile memory system and data writing method: With nonvolatile memory device employing a nonvolatile memory such as multiple-valued NAND flash memory or the like in which each memory cell holds data in a plurality of pages, there is such a problem that, if an error occurred under writing data, data stored in other page in the same... Agent: Smith Patent Office
20070011584 - Data encoding method and system: The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a... Agent: The Law Offices Of Andrew D. Fortney, Ph.d., P.C.
20070011583 - Information storage medium on which drive data is recorded, and method of recording information on the information storage medium: An information storage medium includes a drive zone having a plurality of physical clusters or ECC blocks. When new drive data is recorded in the drive zone, the new drive data is recorded in a physical cluster or ECC block next to the physical cluster or ECC block containing the... Agent: Stein, Mcewen & Bui, LLP
20070011586 - Multi-threshold reliability decoding of low-density parity check codes: A method and apparatus are provided for error correction of a communication signal. A multiple threshold scheme for iteratively decoding a received codeword includes using a comparison of an updated bit reliability with a threshold to generate a reconstructed version of the received codeword. At each iteration the bit reliability... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.
20070011585 - Programmable error correcting device: A programmable error correcting device is disclosed. The programmable error correcting device includes a controller for receiving information about a length of a codeword, an error correcting capacity, whether of not a shortened codeword mode is supported and a total byte number of burst data and outputting a control signal;... Agent: Mayer, Brown, Rowe & Maw LLP
20070011587 - Redundant path communication methods and systems: The systems and methods described herein provide a redundant communication path. The systems and methods can provide a second source for the same data under many circumstances. These circumstances can include, for example, 1) when data incurs errors during transmission in the communication link network, 2) when a communication link... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20070011588 - Architecture and method for error detection and correction for data transmission in a network: Architecture and a method for error detection and error correction for data transmission in a network are provided. In the above architecture, the data for transmission is first encoded by a generating polynomial and the generated parity bits are placed behind the data bit to be transmitted together. A packet,... Agent: J C Patents, Inc.
20070011589 - Nak-to-ack error detection and recovery: According to one embodiment, a system is provided that allows a receiver to determine that an initial error message (such as a NAK message) was not correctly received by a transmitter, and to cause the transmitter to continue transmitting information corresponding to data that has not yet been successfully decoded... Agent: Qualcomm Incorporated
20070011590 - Methods and systems for generating error correction codes: Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns... Agent: North America Intellectual Property Corporation
20070011592 - Decoder architecture for reed solomon codes: A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration... Agent: Manelli Denison & Selter PLLC 7th Floor
20070011591 - Method for generating syndrome value and apparatus thereof: The present invention discloses a method for generating a syndrome value of an error correction codeword (ECC), and a related apparatus. The ECC includes a fixed section, an information section, and a parity section. The fixed section includes not only byte “00”. The method provides a fixed syndrome value according... Agent: North America Intellectual Property Corporation
20070011593 - Apparatus and method for receiving signal in a communication system: Provided is an apparatus and method for receiving a signal in communication system. The apparatus and method includes generating a particular log-likelihood ratio (LLR) value by demapping an input signal according to a particular demapping scheme among a plurality of demapping schemes; performing a control operation of buffering the particular... Agent: Dilworth & Barrese, LLP
20070011594 - Application of a meta-viterbi algorithm for communication systems without intersymbol interference: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed... Agent: Mcandrews Held & Malloy, Ltd
20070011595 - Communication decoder employing single trellis to support multiple code rates and/or multiple modulations: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used... Agent: Garlick Harrison & Markison
20070011597 - Method and apparatus for extracting specific data from bis data: Methods and apparatus for extracting a portion of data from a plurality of BIS data are disclosed. The portion of data can be extracted from the plurality of BIS data stored in a first storage unit when those BIS data are accessed by other components. Alternatively, the extraction of the... Agent: North America Intellectual Property Corporation
20070011596 - Parity check circuit to improve quality of memory device: A system and method for internal error checking a semiconductor memory device in a much more area and energy efficient manner. According to the method, a predefined data pattern is written to a plurality of memory cells in the memory device. A pause or waiting time interval is initiated after... Agent: Edell, Shapiro & Finnan, LLC
20070011600 - Decoding method and apparatus: According to a method and apparatus taught herein, a decoding circuit and method decode linear block codes based on determining joint probabilities for one or more related subsets of bits in received data blocks. The use of joint probabilities enables faster and more reliable determination of received bits, meaning that,... Agent: Coats & Bennett, PLLC
20070011598 - Error detection and correction for encoded data: Embodiments of the present invention provide techniques for detecting and correcting encoded data. In one embodiment, a system for detecting and correcting errors in a plurality of data bits comprises a static memory configured to store a plurality of data bits; a systematic encoder configured to convert the plurality of... Agent: Townsend And Townsend And Crew LLP
20070011599 - Method, apparatus, and computer program product for testing ability to recover from cache directory errors: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20070011601 - Ecc for single 4-bits symbol correction of 32 symbols words with 22 maximum row weight matrix: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.... Agent: Graybeal Jackson Haley LLP01/04/2007 > 22 patent applications in 18 patent subcategories. USPTO class patent listing
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