Error detection/correction and fault detection/recovery inventions 10/06

20060242451 - Memory checking device and method for checking a memory: A memory checking device for cells arranged in memory rows and columns, wherein, in a state of integrity, the memory has parity values for two memory rows or two columns that differ from each other with the same parity value calculation rule or with different parity value calculation rules or...

20060242450 - Methods and apparatuses for selectively rebuffering and decoding a portion of a data block read from an optical storage medium: An apparatus for selectively rebuffering at least a portion of a data block read from an optical storage medium. The apparatus comprises a storage device for buffering the data block, and a rebuffering control module for rebuffering a specific portion into the storage device according to a previous decoding result,...

20060242452 - External storage and data recovery method for external storage as well as program: The data is automatically recovered to a desired arbitrary point in an external storage without imposing a burden on the host computer. An application on a host computer instructs data recovery control processing of a disk control apparatus to set a recovery opportunity. It is possible to register arbitrary plural...

20060242454 - Scalable method of continuous monitoring the remotely accessible resources against the node failures for very large clusters: The notion of controlling, using and monitoring remote resources in a distributed data processing system through the use of proxy resource managers and agents is extended to provide failover capability so that resource coverage is preserved and maintained even in the event of either temporary or longer duration node failure....

20060242453 - System and method for managing hung cluster nodes: A method of enforcing active-active cluster input/output fencing through out-of-band management network for hung cluster nodes is disclosed. In accordance with one embodiment of the present disclosure, a method of resetting a cluster node in a shared storage system includes identifying the cluster node from a plurality of cluster nodes...

20060242456 - Method and system of copying memory from a source processor to a target processor by duplicating memory writes: A method and system of copying memory from a source processor to a target processor by duplicating memory writes. At least some of the exemplary embodiments may be a method comprising stopping execution of a user program on a target processor (the target processor coupled to a first memory), continuing...

20060242455 - Wireless voting method: A wireless voting method is disclosed. The method comprises generating an optical voting indication (140), and controlling a plurality of handsets (112), capable of electromagnetically transmitting a vote input (150) by a user, and a vote registering arrangement (130), capable of receiving and registering transmitted votes, to register votes for...

20060242457 - Method and apparatus for coordinating seamless channel switching in a mesh network: A mesh network including at least one channel master (CM) and a plurality of mesh points (MPs). The CM sends a channel change intention message to at least one of the MPs indicating the CM's intention to change from a first channel to a second channel. Upon reception of the...

20060242458 - Computer volatile memory power backup system: A system for backing up a computer in the event of a mains power failure, the system comprising: sensing means operative to sense a failure of mains power; means for receiving power over data communication cabling; a volatile memory; means for feeding power from the means for receiving power to...

20060242459 - Method, apparatus and program storage device for protecting data writes in a data storage device: A method, apparatus and program storage device for protecting data write operations against write failures in a data storage device is provided. The data storage device includes a storage medium, a write cache including a copy of data written to the storage medium, and a controller configured for testing data...

20060242460 - Software recovery method for flash media with defective formatting: A method and software program for recovering data from corrupted flash media. In one aspect, the method employs a low-level access scheme that enables data to be recovered when high-level interfaces, such as file systems, are damaged. The type of flash media is determined, and a corresponding access scheme is...

20060242461 - Method and system of copying a memory area between processor elements for lock-step execution: A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of...

20060242463 - Abnormal circuit operation detection system: An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each...

20060242462 - Power supply control in a server system: An information handling system comprising at least one power supply unit (PSU), at least one blade server module (BSM) and at least one module monitor board (MMB). The at least one PSU, at least one BSM and the at least one MMB may be removable from the information handling system....

20060242464 - Computer architecture and method of operation for multi-computer distributed processing and coordinated memory and asset handling: The present invention discloses a modified computer architecture (50, 71, 72) which enables an applications program (50) to be run simultaneously on a plurality of computers (M1, . . . Mn). Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied...

20060242465 - Encrypted jtag interface: In one embodiment, a system comprises JTAG functionality that implements at least a portion of a JTAG protocol. The JTAG functionality supports a test data in (TDI) line, a test data out (TDO) line, a test rest (TR) line, a test mode state (TMS) line, and a test clock (TCLK)...

20060242466 - Generating test cases for software with complex preconditions: Techniques and tools for generating test cases for methods or programs with input preconditions are described. For example, after finding feasible control flow paths for a tested method along with each path's associated input conditions, a new program is created which tests these conditions along with the precondition. By analyzing...

20060242467 - Method and apparatus of analyzing computer system interruptions: A method of analyzing a computer application interruption may analyze a cause of the computer application interruption, determine whether the cause of the computer application interruption was user disruptive or non-user-disruptive, determine whether the cause of the computer application interruption was operating system related or non-operating system related and determine...

20060242468 - Memory application tester having vertically-mounted motherboard: The present invention relates to a memory application tester for testing a semiconductor memory device comprising a plurality of motherboards having a memory socket. The motherboards are vertically mounted and effectively integrated so that a memory application tester may test more memory device simultaneously, and a limit in the trace...

20060242469 - Software-hardware welding system: A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think it knows what it is doing may try to control a hardware device, but may not know about a hardware issue, such as another feature or defect...

20060242470 - Trace reporting method and system: A system and method for recording, storing, transferring and viewing trace data from a processor with an embedded trace macrocell. The system provides for compression of repetitive trace records using an algorithm which identifies compressible trace record streams, creates a highly compressed processed trace record stream and stores the processed...

20060242471 - Monitoring error-handler vector in architected memory: A computer system provides a vector monitor for monitoring a first instance of an error-handling vector in architected memory. The monitoring can involve repeatedly comparing the first instance with a second instance of the vector so as to detect a mismatch, should it occur. If a mismatch is detected, the...

20060242472 - Received data compensating device: Provided is a compensating device for a received data can be used in a wide application by a single apparatus for various wiring configurations and transmission media. The compensating device provided between a receiver circuit in a physical layer and a processing device utilizing the received data and including a...

20060242473 - Phase optimization for data communication between plesiochronous time domains: A method and apparatus for optimizing data transfer between launch and capture domains driven by plesiochronous launch and capture clocks transmits a beacon of representational data from the launch domain to the capture domain and captures the beacon in the capture domain using the capture clock. The captured beacon is...

20060242474 - Programmable in-situ delay fault test clock generator: A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse...

20060242475 - Interleaver: An interleaver and scheme for interleaving in which highly correlated bits are maximally separated. The scheme involves interleaving a set of bits to be delivered to a modulation system that utilizes a quantity of N carrier frequencies. A first block of N consecutive bits is assigned to each of N...

20060242476 - Pre-emptive interleaver address generator for turbo decoders: An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself...

20060242477 - Folded interposer: A folded interposer used to achieve a high density semiconductor package is disclosed. The folded interposer is comprised of a thin, flexible material that can be folded around one or multiple semiconductor dice in a serpentine fashion. The semiconductor dice are then attached to a substrate through electrical contacts on...

20060242478 - Methods and systems for detecting symbol erasures: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying...

20060242479 - Method and apparatus for managing disc defects using updateable dma, and disc thereof: A disc defect management method and apparatus using a defect management area that can be updated, and a write once disc incorporating the method. A data area is disposed between a lead-in area and a lead-out area. The disc includes a defect management area (DMA) that is present in at...

20060242480 - Method of and apparatus for managing disc defects using temporary defect management information (tdfl) and temporary defect management information (tdds), and disc having the tdfl and tdds: A disc having an updatable defect management area used by an apparatus for managing defects on the disc, the disc including a user data area which includes user data, a spare area that is a substitute area for a defect existing in the user data area, and an area in...

20060242481 - Method of and apparatus for managing disc defects using temporary defect management information (tdfl) and temporary defect management information (tdds), and disc having the tdfl and tdds: A disc having an updatable defect management area used by an apparatus for managing defects on the disc, the disc including a user data area which includes user data, a spare area that is a substitute area for a defect existing in the user data area, and an area in...

20060242482 - Method of and apparatus for managing disc defects using temporary defect management information (tdfl) and temporary defect management information (tdds), and disc having the tdfl and tdds: A disc having an updatable defect management area used by an apparatus for managing defects on the disc, the disc including a user data area which includes user data, a spare area that is a substitute area for a defect existing in the user data area, and an area in...

20060242483 - Built-in self-testing of multilevel signal interfaces: Error detection mechanisms for signal interfaces, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms are provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or are coupled to the interfaces on a printed circuit board (PCB). BIST...

20060242486 - Error correction coding method for a high-density storage media: An error correction encoding method for a high-density storage medium is provided. This method arranges sequential input data so as to form a plurality of data blocks of a predefined matrix form, the plurality of data blocks being made sequentially, appends outer parity to each column of each data block...

20060242485 - Error detection, documentation, and correction in a flash memory device: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as...

20060242484 - Memory block quality identification in a memory device: If a memory block in a flash memory device is found to have a defect, a memory block quality indication is generated in response to the type of memory defect. This indication is stored in the memory device. In one embodiment, the quality indication is stored in a predetermined location...

20060242487 - Test buffer design and interface mechanism for differential receiver ac/dc boundary scan test: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test...

20060242488 - Flash memory device with reduced access time: A flash memory device with a reduced access time. The flash memory device executes an error detection and correction operation while encoding or decoding transmission and reception signals with a host apparatus. The flash memory device utilizes a simplified design algorithm and reduces an access time....

20060242495 - Memory device having terminals for transferring multiple types of data: Some embodiments of the invention include a memory device having a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information...

20060242492 - Method and apparatus for masking known fails during memory tests readouts: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that...

20060242490 - Method and apparatus for testing a memory device: The extension sector enable signal RS_SEL is a test target control signal for switching a test target between ordinary sectors and redundant sectors. During the test period of redundant sectors, if the defective redundant sector signal RSECF is at a HIGH level (that is, the selected redundant sector is a...

20060242491 - Method and system for applying patches to a computer program concurrently with its execution: The present invention relates to a method, a computer program product and a system of adding new static data variables and initialisation routines for these variables as part of a method of replacing a current version of a computer program with a replacement version of the program concurrently with the...

20060242493 - Network processor having cyclic redundancy check implemented in hardware: A network processor [200] performs Cyclic Redundancy Check (CRC) operations using specialized hardware circuits [308-308]. The network processor [200] includes a plurality of hardwired CRC polynomials that are used to implement the CRC operations. A CRC instruction selects which polynomial to use when performing the CRC operation....

20060242494 - Output data compression scheme using tri-state: A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state condition in response...

20060242496 - Printer controller having tamper resistant shadow memory: A printer controller is provided having an integrated circuit incorporating a processor and memory. The memory stores a set of data representing program code and/or an operating value for printer control. Each bit of the data is stored as a bit/inverse-bit pair in corresponding pairs of physically adjacent bit cells...

20060242489 - Stored data reverification management system and method: A system and method are provided for verifying data copies and reverifying the copies over the life span of media according to a verification policy. Characteristics of media and use of media are tracked to provide metrics which may be used to dynamically reevaluate and reassign verification policies to optimize...

20060242497 - Circuit and method for test and repair: A preferred exemplary embodiment of the current invention concerns memory testing and repair processes, wherein circuitry is provided to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a...

20060242500 - 1149.1tap linking modules: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4...

20060242501 - Communication interface for diagnostic circuits of an integrated circuit: An integrated circuit is provided with diagnostic circuitry, such as serial scan chains or debug bus access circuits, with which communication is established using an interface circuit coupled with a bi-directional serial link to an external diagnostic device. The bi-directional serial link carries both data and control signals....

20060242498 - Digital system and method for testing analogue and mixed-signal circuits or systems: A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied...

20060242503 - Integrated circuit test system: A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by...

20060242502 - Method and apparatus for broadcasting scan patterns in a random access scan based integrated circuit: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network...

20060242499 - Remote integrated circuit testing method and apparatus: A method and system for remotely testing an integrated circuit installed in an integrated circuit system is presented. The integrated circuit is equipped with test structures for testing functional blocks within the integrated circuit, and a test access mechanism configured to receive test vectors for controlling the test structures. Test...

20060242504 - Configurable automatic-test-equipment system: Methods and systems for measuring a device under test are described. A first test instrument is connected to a programmable logic device. The programmable logic device is configured to comply with interface specifications of the first test instrument. A second test instrument, having interface specifications that are different from the...

20060242507 - Achieving desired synchronization at sequential elements while testing integrated circuits using sequential scan techniques: A programmable delay circuit is provided in either data input path or a clock input path of a sequential element contained in a scan chain of an integrated circuit. The scan chain is used to test the integrated circuit using a sequential scan technique (e.g., Automatic test pattern generation (ATPG))....

20060242510 - Apparatus and method for programmable fuse repair to support dynamic relocate and improved cache testing: An apparatus and method for allowing for dynamic wordline repair in a clock running system in addition to allowing for programmable fuse support of combined Array Built-In Self-Test (ABIST) and Logic Built-In Self-Test (LBIST) testing. The method makes use of programmable fuses which contain Level Sensitive Scan Design (LSSD) latches...

20060242505 - Apparatus for performing stuck fault testings within an integrated circuit: An apparatus for performing stuck fault testings within an integrated circuit is disclosed. A delay chain structure includes a first select register, a second select register, a decoder and a chain of multiplexors. With a set of select signals, the first select register generates a set of true encoded select...

20060242506 - High-speed level sensitive scan design test scheme with pipelined test clocks: This invention describes a method of synchronizing test clocks in an LSSD system to achieve near simultaneous arrival of the clock signals at the inputs of all LSSD registers. The method relies on pipelining the latches to distribute the test clocks, where all pipeline latches are synchronized by the system...

20060242509 - Method and system for an on-chip ac self-test controller: An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at...

20060242508 - Simultaneous scan testing for identical modules: A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process scan input and produce a first scan output. The system 100 includes a second module 150 substantially...

20060242513 - Enhancements to data integrity verification mechanism: A method and apparatus is provided for maintaining data integrity. According to the method, a physical checksum calculation is performed on a block of data. After performing the physical checksum calculation, a logical check is performed on the data contained with the block of data. If the block of data...

20060242511 - High speed interconnect circuit test method and apparatus: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry and the boundary scan cells are required to implement the additional instructions. The...

20060242512 - Ip core design supporting user-added scan register option: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and...

20060242514 - Method and apparatus for generating expect data from a captured bit pattern, and memory device using same: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first...

20060242515 - Systematic scan reconfiguration: Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for...

20060242516 - Methods and systems for generating an accurate adaptive clock: A method for generating an accurate adaptive clock is disclosed. The method includes accessing data at a first clock rate, generating an adaptive clock that has an adaptive clock rate that is based on the arrival rate of said data, accessing data related to the first clock rate and the...

20060242517 - Monitoring a data processor to detect abnormal operation: Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or...

20060242518 - Method for verification of electronic circuit units, and an apparatus for carrying out the method: The invention relates to a method for verification of electronic circuit units (101) which are contained in a circuit apparatus (100) with the operating state of the electronic circuit unit (101) to be verified being read by means of the circuit apparatus (100), an identification key (102, HWID) being read...

20060242520 - Adapting scan-bist architectures for low power operation: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan...

20060242521 - Built-in self-test arrangement for integrated circuit memory devices: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the...

20060242519 - Multiple uses for bist test latches: A method, an apparatus, and a computer program are provided to utilize built-in self test (BIST) latches for multiple purposes. Conventionally, BIST latches are single purpose. Hence, separate latches are utilized for array built-in self test (ABIST) and logic built-in self test (LBIST) operations. By having the separate latches, though,...

20060242523 - Ic with protocol selection memory coupled to serial scan path: A digital bus monitor used to observe data on a bus (14, 16, 18) connecting multiple integrated circuits (10, 12) comprises a memory buffer (30), bypass register (34), test port (38) and output control circuits (42, 46) controlled by an event qualifying module (EQM) (32). In response to a matching...

20060242522 - Test vehicle data analysis: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested...

20060242524 - System and method for system-on-chip interconnect verification: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the...

20060242525 - Method and apparatus for functionally verifying a physical device under test: Method, apparatus, and computer readable medium for functionally verifying a physical device under test (DUT) is described. In one example, verification test data is generated for the physical DUT using a constraint-based random test generation process. For example, the architecture, structure, and/or content of the verification test data may be...

20060242528 - Error correction method for high density disc: An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte x m x o. The method comprises the steps of...

20060242527 - Microprocessor with trace module: A processor-based device includes a processor, a trace module, a plurality of data input/output pins, and an input/output interface circuit. The input/output interface circuit, when operating in a trace mode, externally outputs trace data signals from the trace module to an external device via at least one of the data...

20060242526 - Transmitting apparatus, receiving apparatus, transmission method, and reception method: A transmitting apparatus controls, for each transmit frame, at least one of a modulation method and an error correction method. The transmitting apparatus forms an information symbol and transmits the information symbol using multiple subcarriers. A modulation method information signal generator generates an information signal relating to a modulation method...

20060242529 - Medium access control-high speed: A medium access control-high speed (MAC-hs) comprises a hybrid automatic repeat request (H-ARQ) device configured to receive data blocks over a wideband-code division multiple access (W-CDMA) high speed-downlink shared channel (HS-DSCH). The H-ARQ device generates an acknowledgement (ACK) or negative acknowledgement (NACK) for each said data block received. Each received...

20060242530 - Method for constructing finite-length low density parity check codes: A technique for construction of finite-length low-density parity check (LDPC) codes is herein disclosed which advantageously provides a flexible tradeoff of low decoding thresholds and low error-floors....

20060242531 - Method for decoding tail-biting convolutional codes: A method for decoding tail-biting convolutional codes is disclosed. In the method, all beginning states of a trellis diagram are initialized. Forward Viterbi metrics are calculated for the trellis diagram. A trace-back process is performed from an ending state of the trellis diagram at a first time instance to a...

20060242536 - Decoding device and decoding method: The present invention provides a decoding device for decoding an LDPC (Low Density Parity Check) code. The decoding device include: a first operation unit for performing a check node operation for decoding the LDPC code, the operation including an operation of a nonlinear function and an operation of an inverse...

20060242535 - Detection of errors in the communication of data: The invention relates to a method and a system for detecting errors in the communication of data from a transmitter to at least one receiver. In the method, in a first step on the side of the transmitter a first check value is generated at least from user data to...

20060242534 - Low density parity check (ldpc) code: Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown....

20060242533 - Method for updating check-node of low-density parity-check (ldpc) codes decoder and device using the same: The invention provides a method for updating check-node of low-density parity-check (LDPC) codes decoder. The method comprises the following steps: First of all, sort all data that are input into the check-node of LDPC codes decoder to find a minimum absolute value and a second minimum absolute value. Secondly, compare...

20060242532 - Techniques to provide information validation and transfer: Techniques to issue a single application programming interface (API) to request both data copy and CRC validation operations. In some embodiments, a receiver of the API may observe which logic (e.g., software or hardware and/or combinations of software and hardware) is available to execute instructions for data copy and CRC...

20060242537 - Error detection in a logic device without performance impact: An apparatus and method to perform error detection in a logic device without performance impact. The apparatus includes an Error Detection Device (EDD) coupled to a memory module and a processor. The memory module connects to the processor. As information transfers from the memory module to the processor, the EDD...

20060242538 - Multi-bit nonvolatile ferroelectric memory device having fail cell repair circuit and repair method thereof: A multi-bit nonvolatile ferroelectric memory device comprises a plurality of memory cell arrays each including a plurality of multi-bit unit cells connected serially, and a correcting block adapted and configured to group the predetermined number of multi-bit unit cells in one memory group to store a data level signal corresponding...

20060242539 - Nonvolatile ferroelectric memory device including failed cell correcting circuit: A nonvolatile ferroelectric memory device including a failed cell correcting circuit which effectively processes randomly distributed cell data. The nonvolatile ferroelectric memory device checks horizontal parity of a main memory cell array and stores the parity in a horizontal parity check cell array, and checks vertical parity of a main...

20060242540 - System and method for handling write commands to prevent corrupted parity information in a storage array: An architecture and method for executing write commands in a storage array is disclosed. The data strips of the data stripes of the storage array each include a parity check bit. The parity strip of each stripe includes a plurality of parity check bits, each of which is uniquely associated...

20060242541 - High reliability memory module with a fault tolerant address and command bus: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a...

20060242542 - Correcting multiple block data loss in a storage array using a combination of a single diagonal parity group and multiple row parity groups: A method for correcting double failures in a storage array has the following steps. A storage array is organized as a plurality of concatenated sub-arrays, each sub-array including a set of data storage devices and a row parity storage device. Row parity is computed for each row of each sub-array....

20060242543 - Packet protection for header modification: Systems, methods, and devices are disclosed that provide packet protection for header modification. One method includes receiving a packet to a computing device. The method includes apply error checking techniques independently to different portions of the packet....

20060242544 - System(s), method(s), and apparatus for decoding exponential golomb codes: Presented herein are system(s), method(s), and apparatus for decoding exponential Golomb codes. In one embodiment, there is presented a system for decoding codes having lengths (L) and information bits. The system comprises a circuit and a multiplexer. The circuit provides the information bits of the codes. The multiplexer provides values...

20060242547 - Decoding method: A method for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits. Preferably, the stream of units of...

20060242546 - Decoding method and apparatus: A method and apparatus for decoding forward error correction (FEC) encoded data. A stream of units of FEC encoded bits are received, where the units are derived from a transmitted signal, where each unit represents a one-bit data value, and where each unit includes correctness bits that together reflect a...

20060242545 - Decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation: A decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation (EFM/ESM), which has an analog to digital converter (ADC), an adaptive equalizer and a Viterbi decoder. The ADC receives an analog signal with an EFM or ESM feature, and converts the analog signal into a digital signal with the EFM or...

20060242548 - Error correction method for high density disc: An error correction method for optical discs, and more particularly, an error correction method appropriate to high density discs is provided. The error correction method adds inner parity and outer parity to an error correction block of size n byte x m x o. The method comprises the steps of...

20060236149 - System and method for rebuilding a storage disk: A system and method for rebuilding a storage drive utilizes a rebuild management module within a RAID controller to conduct a substantially sequential rebuild operation on a rebuild disk. When the rebuild management module receives host I/O requests during a rebuild operation, these requests are facilitated using other disks. After...

20060236150 - Timer-based apparatus and method for fault-tolerant booting of a storage controller: A fault tolerant storage controller having a processor, redundant copies of a stored program, and a timer that automatically runs when the processor is reset is disclosed. Selection logic selects a first copy of the program to boot on the processor. If the timer expires before the first copy successfully...

20060236151 - Database automated disaster recovery: A method of automated disaster site recovery of a DB2 subsystem is presented. The method reads parameters contained in a user modifiable control dataset of recovery parameters for objects, systems, and applications to be recovered. The method also reads a DB2 system catalog containing recovery requirements. The method then creates...

20060236152 - Method and apparatus for template based parallel checkpointing: A method and apparatus for a template based parallel checkpoint save for a massively parallel super computer system using a parallel checksum algorithm such as rsync. In preferred embodiments, the checkpoint data for each node is compared to a template checkpoint file that resides in the storage and that was...

20060236154 - Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method: A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net...

20060236153 - Transmission of data with forward error correction information: A method of transmitting content data to one or more receiving devices (5a, 5b) over a first communication channel (7) and transmitting recovery information associated with the content data over a second communication channel (9). The recovery information may be transmitted as a response to a request from the receiving...

20060236155 - Remote control system and remote switch control method for blade servers: A remote control system and remote switch control method for blade servers aims to switch different server blades and monitors and controls the server blades through a remote control station. The remote control system is connected to a baseboard management controller on a back plane, to form direct communication. When...

20060236156 - Methods and apparatus for handling code coverage data: In one aspect, a method and apparatus for formatting code coverage data generated by performing one or more code coverage tests on a program module derived from computer code is provided, including organizing the code coverage data in a hierarchy having a plurality of tables, each of the plurality of...

20060236157 - Calibrating automatic test equipment: Calibrating automatic test equipment (ATE) includes determining an offset between a reference timing event and a channel event, where the channel event is associated with a communication channel of the ATE, and adjusting signal transmission over the communication channel based on the offset. Determining the offset may include obtaining a...

20060236159 - Data transmitter-receiver, bidirectional data transmitting system, and data transmitting-receiving method: A data obtaining portion 11 of a terminal 10 obtains positional directional information D(Tn) and a time information obtaining portion 12 obtains time information Tn. The terminal 10 stores D(Tn) and Tn in a memory portion 13 and a transmitting portion 15 transmits D(Tn) and Tn to a server 20....

20060236158 - Memory element for mitigating soft errors in logic: In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed data signals, the delayed data signals, the clock signal, and the data signal from a logic circuit are applied to a triple redundant memory element. The delay of the first delayed...

20060236161 - Apparatus and method for controlling disk array with redundancy: According to one embodiment, a read/write control unit controls read/write access to at least two disk drives that provide a disk array. Error counters are provided for the respective disk drives for counting respective numbers of errors if the errors occur when the disk drives are accessed. A failure estimation...

20060236160 - Mutli-layered information recording medium, reproduction apparatus, recording apparatus, reproduction method, and recording method: A multi-layered information recording medium comprising a plurality of recording layers, a user data area for recording user data, provided in at least two of the plurality of recording layers, and a defect list storing area for storing a defect list. When at least one defective area is detected in...

20060236164 - Automatic test entry termination in a memory device: A memory device has a control register comprising a test mode disable bit. The test mode is initially enabled. If the device does not receive an appropriate key or command as the next command received, the test mode is disabled. If the appropriate key is received, the test mode is...

20060236162 - Method and system for performing system-level correction of memory errors: One embodiment is a method of correcting errors in a memory subsystem in a computer system. The method comprises monitoring occurrence of correctable memory errors; responsive to the monitoring, determining whether a risk of occurrence of an uncorrectable memory error is less than a tolerable risk; and responsive to a...

20060236163 - Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area: A memory component and a method for the parallel testing of memory components are described herein. A fully functional memory area, which is classified herein as all good memory, and memory components including a restricted memory area, which are classified herein as partial good memory, are provided. Test data words...

20060236165 - Managing memory health: Systems, methodologies, media, and other embodiments associated with managing memory health are described. One exemplary system embodiment includes logic for detecting and correcting single bit memory errors. The example system may also include logic for selectively making unavailable a memory location associated with single bit memory errors....

20060236166 - Integrated circuit capable of error management: A method according to one embodiment may include receiving a write request to write data in a local storage device. The method of this embodiment may also include detecting a write error in the local storage device. The method of this embodiment may also include reserving a reserved area in...

20060236167 - Compilation of calibration information for plural testflows: In one embodiment, a selection of plural testflows is first obtained. Each testflow specifies how automated test equipment (ATE) should test at least one device. Calibration information is then identified for each of the testflows, and redundancies in the identified calibration information are eliminated to compile a set of non-redundant...

20060236169 - Method and circuit for parametric testing of integrated circuits with an exclusive-or logic tree: A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second...

20060236173 - Method and system for configuring registers in microcontrollers, and corresponding computer-program product: A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the...

20060236171 - Method for detecting and correcting errors of electronic apparatus: A method for detecting and correcting the error of an electronic apparatus is provided. An embedded controller whose power is independently supplied is used to detect and store the error code from the internal devices of the electronic apparatus. First, the error status of the electronic apparatus is detected to...

20060236170 - On-chip sampling circuit and method: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In...

20060236174 - Optimized jtag interface: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used...

20060236172 - Semiconductor device and method for testing the same: On a semiconductor wafer 10, semiconductor chip regions 12 including a semiconductor integrated circuit, a scribe line 14 formed adjacent to the semiconductor chip region 12, a test device 18 formed in the scribe line 14, electrically separated from the semiconductor circuit in the semiconductor chip region 12, for controlling...

20060236175 - Semiconductor integrated circuit device and i/o cell for the same: In a semiconductor integrated circuit device in which a plurality of I/O cells having level shift circuits are placed in an I/O region, two input/output cells respectively have four level shift circuits 11, 12a to 12c. A power supply cell, originally including only wiring for supply of a power supply...

20060236168 - System and method for dynamically optimizing performance and reliability of redundant processing systems: An improved system and method for dynamically optimizing the performance and reliability of redundant processing systems (e.g., for use in space applications) are disclosed. As one example, a Field Programmable Gate Array (FPGA) that includes a plurality of processors is disclosed. Based on mission specific modes or environmental conditions, the...

20060236179 - Delay test method for large-scale integrated circuits: The propagation delay of a combinatorial circuit in a large-scale integrated circuit is tested by carrying out two scan tests. Both scan tests generate the same input signal transitions to the combinatorial circuit. One scan test scans the outputs of the combinatorial circuit after the transitions propagate through the combinatorial...

20060236177 - Method for eliminating hold error in scan chain: A method for eliminating a hold error from a scan chain configured by connecting a plurality of data holding circuits with wiring. The method includes reordering the data holding circuits using the wiring as a delay element to eliminate hold errors from the scan chain. This method eliminates hold errors...

20060236178 - Ram testing apparatus and method: Since fault detection is not conducted for the address other than the noted address or the expected value other than the noted expected value in the RAM test, generation of a fault can be discriminated easily for the predetermined noted address or noted expected value when a fault is detected....

20060236176 - Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset...

20060236180 - Integrated circuit testing module including command driver: Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between an automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher clock frequency than the automated testing equipment...

20060236181 - Systems and methods for lbist testing using multiple functional subphases: Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where the LBIST circuitry is configured to propagate data through different portions of the functional logic of the circuits at different times. In one embodiment, a logic circuit incorporates LBIST components including a set of scan chains interposed between...

20060236182 - Scan-based self-test structure and method using weighted scan-enable signals: A scan-based self-test architecture and method using weighted scan enable signals is disclosed. The self-test architecture comprises: a linear feedback shift register; a phase shifter connected to outputs of the linear feedback shift register, and scan chains and the combinational part of the circuit under test; an AND gate; scan...

20060236183 - Method and apparatus for evaluating and optimizing a signaling system: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference....

20060236184 - Fault detecting method and layout method for semiconductor integrated circuit: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to...

20060236185 - Multiple function results using single pattern and method: A testing system for testing a manufactured semiconductor component includes a main processor and a pattern generator. The main processor is configured to run a main program. The pattern generator is configured to generate a plurality of functional test patterns, and each test pattern is assembled to test the manufactured...

20060236186 - Test output compaction with improved blocking of unknown values: A test output compaction arrangement and a method of generating control patterns for unknown blocking is herein disclosed. The specified bits in the control patterns, which when using linear feedback shift register (LFSR) reseeding determines control data volume and LFSR size, are preferably organized in a manner so as to...

20060236187 - Error messaging method in http based communication systems: The invention relates to error messaging in HTTP based communication systems. An intermediate device (20) interconnecting a wireless client terminal (10) and a web server (30) transforms error messages sent from the server before transmitting them to the client. Hereby, a first error status code from the server is transformed...

20060236188 - Rf transmission error detection and correction module: A radio frequency (RF) transmission correction module includes an RF transmission error detection module and a correction module. The error detection module includes an RF envelope detector, a signal conversion module, and an error detection module. The RF envelope detector is operably coupled to produce an envelope signal from a...

20060236189 - Distributed control apparatus: A distributed control system includes a plurality of PLCs which are connected together via active and backup transmission lines which are opposite in transmission direction. Each of the PLCs includes a diagnosis command sending program for sending a diagnosis command, via a diagnosis-command transmission line, which is one of the...

20060236190 - Power control of packet data transmission in cellular network: A transmitter for a packet radio network, including means for transmitting a signal including data packets to a receiver, means for receiving acknowledgement messages from the receiver, each acknowledgement message indicating whether or not a data packet was received successfully, and means for adjusting transmit power of the signal in...

20060236191 - Method and apparatus for generating block-based low-density parity check matrix and recording medium having recorded thereon code for implementing the method: A method of and an apparatus for generating a block-based low density parity check (LDPC) matrix, where calculation of an inverse matrix is not necessary and back-substitution is possible over the entire matrix area, and a recording medium having recorded thereon code for implementing the method. An area of the...

20060236192 - Adaptable channel compensation for reliable communication over fading communication links: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of...

20060236193 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. In the data stream, the second error correcting codes and the synchronization signals alternatively interleave the first error...

20060236194 - Decomposer for parallel turbo decoding, process and integrated circuit: A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional...

20060236199 - Apparatuses and methods for checking integrity of transmission data: A generator may include a monitoring unit, an engine unit and/or a register. The monitoring unit may selectively extract at least a portion of data to be transmitted to, or received from, an external communication device. The engine unit may generate an error check code using a polynomial expression or...

20060236196 - Combined command and data code: An apparatus includes a source for a command and an associated data. An error code generator generates an error code for the combined command and associated data, which is distributed among the command and the associated data. A transmitter then transmits the command and the associated data separately....

20060236195 - Efficient check node message transform approximation for ldpc decoder: In modern iterative coding systems such as LDPC decoder and turbo-convolutional decoder in which the invention may be used, the core computations can often be reduced to a sequence of additions and subtractions alternating between logarithm and linear domains A computationally efficient and robust approximation method for log and exp...

20060236201 - High reliability memory module with a fault tolerant address and command bus: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a...

20060236200 - Image processor: An image processor includes a JPEG 2000 codec. The JPEG 2000 codec generates a plurality of levels of encoded data, and a checksum circuit integrates the encoded data for each of the levels to determine a checksum. The determined checksum is written together with the encoded data into a header...

20060236202 - Method of detecting two-dimensional codes: A method is described of detecting two-dimensional codes, in particular matrix codes, which include a plurality light and dark data bits arranged two dimensionally, in particular in matrix form. In the method, the code is detected as a gray scale value image; the detected gray scale value image is split...

20060236198 - Storage system with automatic redundant code component failure detection, notification, and repair: A RAID system includes a non-volatile memory storing a first program and first and second copies of a second program, and a processor executing the first program. The first program detects the first copy of the second program is failed and repairs the failed first copy in the non-volatile memory...

20060236197 - Transmission method combining trellis coded modulation and low-density parity check code and architecture thereof: The present invention discloses a method combining Trellis Coded Modulation (TCM) and Low-Density Parity Check (LDPC) code and the architecture thereof, which incorporates TCM with LDPC code having better error-correction capability to promote transmission quality and to define TCM of different transmission rates. Further, TCM can utilize less number of...

20060236203 - Error recovery in rfid reader systems: RFID systems, devices, software and methods are adapted for receiving from an RFID tag at least waves that communicate at least a first version of its code. An output tag code is output that is the same as the first version, if a fidelity criterion is met regarding the first...

20060236207 - Error detection, documentation, and correction in a flash memory device: A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as...

20060236204 - Memory device with serial transmission interface and error correction mehtod for serial transmission interface: The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial...

20060236206 - Semiconductor memory device: In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a...

20060236205 - Storage control circuit, and method for address error check in the storage control circuit: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written...

20060236209 - Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit: A logic integrated circuit reconfigures a reconfigurable circuit to a circuit having the function of a fixed circuit at the time of a fault in the fixed circuit. The fixed circuits are divided into a plurality of functional circuit blocks, which are connected to programmable buses. Reconfigurable circuits corresponding to...

20060236208 - Soft error correction method, memory control apparatus and memory system: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable...

20060236210 - Iterative decoding of packet data: A receiver employs iterative decoding of packet data, where the packet data represents a data frame encoded with at least two logical dimensions. A logical dimension refers to a layer, or sub-layer, of a layered network architecture. Consequently, a first logical dimension of encoding might refer to error detection in...

20060236211 - Cyclic redundancy check modification for length detection of message with convolutional protection: In a method for a variable-length communications system including encoding a message and decoding a data bit stream, the message includes a plurality of message blocks. A message block of the message is encoded by generating a parity check bit stream, flipping the parity check bit stream, appending the flipped...

20060236212 - High speed hardware implementation of modified reed-solomon decoder: A decoder suitable for use in a digital communications system utilizing an RS(n′, k′) code modified from an RS(n, k) code receives n′-symbol vectors each including k′ message symbols and r′=n′-k′ parity symbols and decodes the n′-symbol vectors to correct errors therein, wherein n, k, n′, and k′ are integers,...

20060236213 - Control method for error detection & correction apparatus, error detection & correction apparatus, and control program for error detection & correction apparatus: The present invention provides a control method for an error detection & correction apparatus, comprising a plurality of data processing apparatuses which reside in a data communications path and partake in exchanging data by the unit of error correcting code, and a plurality of information exchange paths which are installed...

20060236214 - Method and apparatus for implementing decode operations in a data processor: An improved method and apparatus for performing operations (such as Viterbi decode) in digital processors using a reduced number of cycles. In one aspect, the invention comprises efficient methods for performing multiple “butterfly” add-compare-select (ACS) operations using an improved dual butterfly (DVBF) extension instruction added to the instruction set of...

20060230305 - Retry request overload protection: Retry request overload protection is described. A server system determines a client status based on retry requests received from the client. The client status may be used to determine whether to accept and/or process new retry requests received from the client and/or whether to transmit previously requested retry packets to...

20060230306 - Apparatus, system, and method for facilitating monitoring and responding to error events: An apparatus, system, and method are disclosed for facilitating monitoring and responding to error events. An apparatus may includes a set of counters associated with a processing system resource, each counter associated with an error event and having attributes defining a count value, counter thresholds directly related to time, and...

20060230307 - Methods and systems for conducting processor health-checks: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the...

20060230308 - Methods and systems for conducting processor health-checks: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the...

20060230309 - System for remote fault management in a wireless network: This invention relates generally to network management in large telecommunications networks. A system and method capable of providing signal consolidation, replication, and correlation at a fault processor in order to allow signal information to remain visible at the fault processor even when communications between the fault processor and subordinate processors...

20060230310 - Trellis ring network architecture: A network for a large number of processing elements utilizes a trellis ring architecture to provide an efficient and fault tolerant data routing system. The processing elements (which may be chip-based processors, circuit cards, unit level assemblies, or computing devices) are interconnected together in an endless ring structure. In addition...

20060230311 - System and method for undoing application actions using inverse actions with atomic rollback: An undo operation is executed by an application by performing the inverse actions of the do operation to which the undo operation relates. Previous designs simply swapped memory to execute an undo operation according to code that was entirely dissimilar to the code of the do operation. The dissimilarity of...

20060230312 - Methods and systems for performing remote diagnostics: Diagnostic methods and systems are described in which a client or consumer electronic device can be remotely controlled and operated for purposes which include performing diagnostics and/or implementing remedial measures designed to remedy identified problems associated with the consumer electronic device....

20060230314 - Automatic generation of solution deployment descriptors: A system for generating deployment descriptor files for automation of installation and integration of computing system solution components such as databases, application programs, communications protocols, and the like, to form an enterprise computing solution. Configurable behavioral models are associated with a system solution design, each of which is associated with...

20060230313 - Diagnostic and prognostic method and system: A method for diagnosing a system is provided. The method may include obtaining a plurality of input parameters from the system. The system may generate actual values of one or more output parameters based on the plurality of input parameters. The method may also include independently deriving values of the...

20060230315 - System for integrated data integrity verification and method thereof: In accordance with one technique, a first plurality of values associated with data transfers between a processor and a memory is received at the processor and at least a subset of the first plurality of values are accumulated in one or more accumulators. The one or more accumulators are accessed...

20060230316 - Method ensuring normal operation at early power-on self test stage: A method for ensuring normal operation at an Early Power-On Self Test stage of a computer device is proposed. The method is applied to the computer devices having a timing function. A largest execution time for at least an Early POST program is preset, and the actual execution time of...

20060230319 - Automated migration of software instructions: A system is disclosed for converting a source software script from one format into a target software script having another format. The process includes for converting both a script file for testing a software application as well as GUI files related to a user interface of the software application to...

20060230317 - System and method for benchmarking: According to one embodiment, a benchmarking system comprises a processor and a multi-threaded load generator. The multi-threaded load generator uses events for managing processing by the threads. The load generator utilizes a thread for spinning and using a CPU cycle counter to determine time for issuing loads to a system...

20060230320 - System and method for unit test generation: A method and system for generating test cases for a computer program including a plurality of test units. The method and system execute the computer program; monitor the execution of the computer program to obtain monitored information and generate one or more test cases utilizing the monitored information....

20060230318 - Test executive system with automatic expression logging and parameter logging: A test executive sequence may be created by including a plurality of test executive steps in the test executive sequence in response to user input to a sequence editor. At least a subset of the test executive steps in the test executive sequence may be configured to call user-supplied code...

20060230321 - User interface panel for hung applications: Methods and systems for providing information to a user when an application is in a hung state are provided. When an application is in a hung state, a dialogue box informing the user of options for responding to the hung application is displayed. An application window may also be replaced...

20060230322 - Content processing device: An HDD recording unit records a received content in an HDD unit based on copyright protection information. If restriction information permits compression, the content recorded in the HDD unit can be read and compressed. In this case, the original content recorded in the HDD unit is not deleted even if...

20060230323 - Measuring elapsed time for a software routine: A method for determining if a measurement of an elapsed time for an execution of a software routine in a computer system is valid. A clock skew is used between the clocks of two processors such that the size of the clock skew is greater than the maximum possible elapsed...

20060230324 - Visual indication for hung applications: Methods and systems for providing a visual indication of hung applications are provided. When an application is in a hung state, an application window is replaced with a proxy window. The appearance of the proxy window is altered when a user attempts to interact with the proxy window....

20060230325 - Information recording and reproducing apparatus: An information recording and reproducing apparatus is disclosed. When a dual layer DVD disk is to be ejected before formatting is completed, the information recording and reproducing apparatus provides a middle area adjacent to a formatted area of the first recording layer, a middle area in the second recording layer...

20060230326 - Method for re-using test cases through standardization and modularity: A method is disclosed for creating test cases for simulating the design and operation of an integrated circuit having operational functionality that requires adherence to a multiplicity of operating rules, wherein the test cases are created in such a way that modularized component test cases can be combined and comprises...

20060230327 - Apparatus for and method of recording digital information signals: A recording apparatus for recording digital information signals on a removable rewritable disc like recording medium has been proposed. The apparatus comprises writing means (21, 22, 25) for recording the digital information signals and controls means (20) for controlling the recording. The apparatus is capable of performing initialization, formatting and...

20060230329 - Chip correct and fault isolation in computer memory systems: Systems and methods for implementing chip correct and fault isolation in computer memory systems are disclosed. An exemplary method may include interleaving check bits with a data word to form at least one interleaved data word. The method may also include writing the at least one interleaved data word to...

20060230328 - Device and method for recording information: A device for recording records information in blocks having logical addresses at a physical address in a track on a record carrier. The logical addresses are translated into the physical addresses in dependence of defect management information, such as primary and secondary defect lists and remapping tables, maintained in defect...

20060230330 - Device and method for recording information: A device records information in blocks having logical addresses at a physical address in a track on a record carrier. The logical addresses are translated into the physical addresses in dependence of defect management information (52,53,61,64), which includes defect entries indicating locations for replacing defective physical addresses. A read-only state...

20060224913 - Token with relatively moving components and separator assembly thereof: A token having a body member with an opening therein and is configured to translate across a support surface. The token includes a sensing object movable within the opening as the body member moves across the support surface. The sensing object can be freely mounted for rotation, or pivotally mounted...

20060224915 - Apparatus, method, and computer product for executing program: An operating computer or a standby computer can execute a program. The operating computer includes a first storage unit and the standby computer includes a second storage unit. Access to the first storage unit is frozen. Only minimum data required for the standby computer to execute the program that was...

20060224916 - Data storage device, reconstruction controlling device, reconstruction controlling method, and storage medium: A data storage device having a redundant storage area for processing data, the data storage device including an input-output state determining unit for determining whether a command process involved in one of input and output of processing data from and to an outside of the device is being performed or...

20060224914 - Raid system using regional error statistics for redundancy grouping: Geometrically-dependent error rates are used to identify sectors for XORing data in a RAID system for parity purposes in such a way that the probability of failure of any particular group is minimized....

20060224917 - Technique for correcting multiple storage device failures in a storage array: A method for storing data for correction of multiple data storage failures in a storage array is presented. The storage array is organized as a plurality of sub-arrays, each sub-array including a set of data storage devices and a plurality of local parity storage blocks, each of the plurality of...

20060224918 - Redundancy system having synchronization function and synchronization method for redundancy system: A redundancy system that can perform synchronization even if a failure occurs to an application. According to the redundancy system of the present invention, a synchronization data memory area, a management bit map table having a flag created for each segment of the synchronization data memory area, and a management...

20060224919 - Method, system, and computer program product for electronic messaging: A browser-based simulator may be used to create and send test messages to one or more transaction processing facilities (TPFs) to determine the response of the TPF system. It allows a user or plurality of users to create ISO 8583 messages, send the messages to the TPF systems, receive a...

20060224920 - Advanced switching lost packet and event detection and handling: Embodiments of the invention may provide a method to send a packet from an endpoint in an advanced switching fabric and starting a timer to run until receiving a response packet or receiving an event packet notifying of a device failure, save a copy of the sent packet, detect if...

20060224921 - Test effort optimization for ui intensive workflows: A system and method provide for determining optimal input combinations useable in testing program code that includes user interface intensive workflows. Various embodiments provides for determining an input set corresponding to the target program code, determining mutually exclusive feature groups corresponding to the input set and determining a set of...

20060224922 - Integrated circuit and method for sending requests: In networks on an integrated circuit a first module typically has access to an address space, wherein addresses identify locations within second modules. It may be necessary to address two or more second modules simultaneously. In that case, the first module replicates a request and sends the resulting plurality of...

20060224923 - Semiconductor device and method for testing semiconductor device: A method for testing a semiconductor device incorporating a controller, which generates first and second complementary signals, and a memory, which operates in accordance with the first and second complementary signals. The method includes selectively switching the first and second complementary signals to an intermediate potential signal having an intermediate...

20060224926 - Diagnostic program, a switching program, a testing apparatus, and a diagnostic method: A diagnostic program for making a control apparatus of a testing apparatus diagnose a test module is provided, wherein the diagnostic program includes an object diagnostic software module for making the control apparatus diagnose a test module which is an object to be diagnosed; a signal for diagnosis input and...

20060224924 - Generating finite state machines for software systems with asynchronous callbacks: Techniques and tools for generating finite state machines (“FSMs”) for a software system with asynchronous callbacks are described. For example, method invocations in a model of the software system are partitioned into observable and controlled method invocations. The controlled method invocations are those which can be run from a test...

20060224925 - Method and system for analyzing an application: An application is analyzed by obtaining the resource availability for one or more resources of a computer infrastructure. In particular, the resource availability can be obtained while the application is executing and when the application is not executing. By comparing respective resource availabilities, the resource consumption by the application can...

20060224927 - Security detection system and methods regarding the same: A security detection system is installed in a computer system. The security detection system comprises a monitoring module and a message database. The monitoring module is used for monitoring a change operation to the computer system. The message database is used for storing message for the change operation. The monitoring...

20060224928 - Apparatus and method to generate and save run time data: A method is disclosed to generate and save run time data. The method supplies an embedded device comprising a processor which includes a processor cache, memory, a hardware trace facility comprising a plurality of data buffers, where the embedded device is capable of communicating with one or more host adapter...

20060224929 - Content generating apparatus and method: A state management apparatus is disclosed which makes a determination whether or not to provide services based on a plurality of state information. For example, it is determined whether all the family members are going out or not based on state information of each family member. If all the family...

20060224930 - Systems and methods for event detection: A system accesses a log of events on more than one computing system and scans these logs in an effort to determine the likely cause of various items of interest, events, or problems. These items of interest often include improper or frustrating behavior of a computer system, but may also...

20060224931 - Data processing system for keeping isolation between logical partitions: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To...

20060224932 - Decentralized error response in cam disk axes: The invention relates to a method for error response when an error occurs in response to a motion, particularly of a drive mechanism in a machine, the motion taking place while using at least one master axis and at least one cam disk having at least one input and one...

20060224933 - Mechanism for implementing redundancy to mask failing sram: In some embodiments, an apparatus to implement redundancy for failure masking in memory is disclosed. The apparatus comprises a built-in self test (BIST) log to store BIST data representing faulty columns of a memory, a redundancy configuration logic to generate one or more select signals based on the BIST data,...

20060224934 - System correcting random and/or burst errors using rs (reed-solomon) code, turbo/ldpc (low density parity check) code and convolutional interleave: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed...

20060224935 - System correcting random and/or burst errors using rs (reed-solomon) code, turbo/ldpc (low density parity check) code and convolutional interleave: System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed...

20060224936 - Data transfer apparatus: A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates a bulk packet (or a control packet) which is a...