Error detection/correction and fault detection/recovery inventions 09/06

20060212740 - virtual private cluster: The present invention provides a system, method and computer-readable media for generating virtual private clusters out of a group of compute resources. Typically, the group of compute resources involves a group of clusters independently administered. The method provides for aggregating the group of compute resources, partitioning the aggregated group of...

20060212741 - Implementing a test regime for a network based telephony systems: A process of implementing a test plan for an IP-based telephony network. The process consists initially of installing a system test module as an integral component of the network-based system, whereby test procedures originate within the network-based system, employing system resources rather than outside components to accomplish testing. Further steps...

20060212742 - Prompt backup/recovery system and methods regarding the same: A backup/recovery system and methodology that provides seamless networking. According to the invention, backup/recovery system is suitable for a network. The backup/recovery system includes a server part and at least one client part for storing at least one incremental recovery point. The at least one client part sends at least...

20060212743 - Storage medium readable by a machine tangible embodying event notification management program and event notification management apparatus: An event notification management program 110 makes a computer function as processing means for controlling notification, given to a predetermined system 200, of information about an event occurred within the system 100 that is acquired from notification information provided from a component (20, 30, 40) within the system 100. The...

20060212750 - Automated recovery of computer appliances: Aspects of the invention provide methods and architectures for enhancing the reliability of computer appliances and reducing the possibilities that human intervention is necessary in the event of a system failure or failure condition. The provided architecture is extensible and provides a generalized framework that is adaptable to many different...

20060212749 - Failure communication method: A communication method for detecting failure and for performing immediate stop processing is provided. It is a failure communication method of a computer, comprising a plurality of units A, separated by partitions, and a unit B interconnecting the units A, in which the unit B broadcasts identical information, generated based...

20060212744 - Methods, systems, and storage medium for data recovery: A geographically distributed array of redundant disk storage devices are interconnected with high bandwidth optical links for disaster recovery for computer data centers. These provide recovery from multiple site failures with less disk storage, less bandwidth, and lower cost than conventional approaches and with potentially faster recovery from site failures...

20060212745 - Power relay or switch contact tester: Embodiments of the invention include a test circuit having an auxiliary low power test signal generator, filters, and a detector to test a power switch. The generator sends an auxiliary low power test signal having a different frequency than a power signal for the switch to an input of the...

20060212746 - Selection of migration methods including partial read restore in distributed storage management: A hierarchical storage system is constructed from file servers and a policy engine server by building upon a file migration service. Offline attributes are added to file system inodes in a primary file server, file system parameters are added in the primary server, an offline read access method field is...

20060212748 - Storage control apparatus and method: In a system for dispersively storing data and parity in a plurality of storage devices, information in a first storage device is restored by using information stored in the storage devices other than the first storage device when the first storage device fails. And information in a non-restored area in...

20060212747 - Storage control system and storage control method: A storage system enabling effective use of storage resources by immediately releasing a storage device provided as a spare from data recovery processing for a faulty storage device. Even before the completion of the collection copy, the faulty disk drive may be replaced with a new disk drive and a...

20060212751 - Volume and failure management method on a network having a storage device: A SAN manager acquires configuration information from devices constituting a SAN and produces a corresponding relationship between a host computer and a virtual volume (virtual volume mapping) and a corresponding relationship between the host computer and a real volume (real volume mapping). Based on those pieces of mapping information, the...

20060212752 - Method and apparatus for identifying a faulty component on a multiple component field replacement unit: The present invention is directed to a data storage system utilizing a number of data storage devices. The data storage system features one or more storage device sleds, which may each carry multiple storage devices. Each storage device sled and its interconnected storage devices may comprise a field replaceable unit....

20060212753 - Control method for information processing apparatus, information processing apparatus, control program for information processing system and redundant comprisal control apparatus: The present invention provides a control method for an information processing system, which includes a plurality of processing apparatuses performing a mutually equivalent operation, comprising the step of isolating the processing apparatus for which a fluctuation of power source voltage is relatively large, from the information processing system, if an...

20060212754 - Multiprocessor system: In a multiprocessor system in which a plurality of processors are managed by a management processor, and an access to a shared memory is controlled by a bus control device, the management processor or the bus control device provides to the processors time information synchronized at a time of a...

20060212755 - Method and apparatus for detecting the onset of hard disk failures: A system that detects the onset of hard disk drive failure. During operation, the system measures vibrations from the hard disk drive to produce one or more vibration signals. Next, the system generates a vibration signature for the hard disk drive from the measured vibration signals. The system then determines...

20060212756 - Highly specialized scenarios in random test generation: Improvements in functional verification of a design are achieved by providing a test template that specifies test parameters directed to a function of the design. An exemption mode of operation is associated with a portion of the template, in which constraints and variables associated with the template are revised. The...

20060212757 - Method, system, and program product for managing computer-based interruptions: The present invention provides a method, system, and computer program product for managing computer-based interruptions. The method comprises receiving an interruption directed at a user, and selectively suppressing delivery to the user of an interruption notification corresponding to the interruption, based on a current state of the user, a classification...

20060212759 - Conformance testing of multi-threaded and distributed software systems: Techniques and tools for testing multi-threaded or distributed software systems are described. For example, a multi-threaded system is instrumented and executed to produce logs of events that are performed by each of its agents. The agent logs contain a totally ordered series of events per agent, as well as information...

20060212758 - System and method for automated interaction diagram generation using source code breakpoints: A system and method for automated interaction diagram generation using source code breakpoints is presented. A user sets diagram breakpoints at locations in source code using an integrated development environment (IDE) that includes a diagram generation manager. The user sets the breakpoints at locations where the user wishes to capture...

20060212760 - System and method for sharing a communications link between multiple communications protocols: A system and method for sharing a communications link between multiple protocols is described that comprises a system comprising a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol...

20060212761 - Data and instruction address compression: An improved method, apparatus, and computer instructions for compressing trace data. An instruction stream is identified, and in response to identifying the instruction stream, the instruction addresses in the instruction stream are replaced with a stream identifier to form compressed trace data. Data addresses may be related to instructions in...

20060212762 - Error management topologies: A method according to one embodiment may include partitioning a plurality of processor cores into a main partition comprising at least one processor core capable of executing an operating system and an embedded partition comprising at least one different processor core. The embedded partition of this embodiment may be capable...

20060212763 - Error notification method and information processing apparatus: An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system...

20060212764 - Integrated circuit and method for testing memory on the integrated circuit: An integrated circuit and method for testing memory on that integrated circuit are provided. The integrated circuit comprises processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also...

20060212766 - Display device and driving method thereof: A display device includes an insulating substrate, a plurality of gate lines formed on the insulating substrate, a plurality of data lines across the gate lines, a plurality of pixels connected to the gate lines and the data lines, a data driver providing data voltages to the pixels, a first...

20060212765 - Integrated circuit with a control input that can be disabled: An integrated circuit comprises a control unit, a plurality of control inputs for the provision of control signals to said control unit and a deactivation circuit for disabling the provision of at least one of said control signals. After reception of a first coded message by said integrated circuit the...

20060212767 - Production plant: A production plant having a number of machine tools, a number of tools/instruments, and a computer system having a number of first memory cells containing work cycle descriptions, a number of second memory cells containing operation descriptions, a number of third memory cells containing step descriptions, a number of fourth...

20060212768 - Verification circuitry for master-slave system: Operation of a system including master and slave devices is verified through the use of system verification circuitry including a test master circuit that outputs test patterns on the system bus to emulate the operation of all master devices in the system, a built-in self-test and memory circuit that stores...

20060212769 - Apparatus and method for testing codec software by utilizing parallel processes: An apparatus for testing codec software includes a processor unit operative to execute a test program to read input data from a memory unit, to transform the input data according to transformation conditions by referring to data of the transformation conditions stored in the memory unit, and to generate a...

20060212770 - Error detection in compressed data: A device under test—DUT—, comprising the steps of receiving a first data sequence from the DUT in response to a first stimulus signal, wherein the data of a plurality of internal data sequences of the DUT is compressed into the first data sequence, comparing the first data sequence with expected...

20060212771 - System and method for automatically uploading analysis data for customer support: The invention enhances automatic incident control, problem control, and problem prevention using information provided by the analysis or analysis data. The burden on the part of both users and providers to resolve problems is reduced by using a method of automatic analysis data upload and intelligent problem analysis and resolution....

20060212772 - Method and apparatus for data encoding: A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addition (e.g. to a common store)...

20060212774 - Apparatus and method for transmission which encoding a message with space-time tubo code using feedback bit in mobile communication system: An apparatus and a method for transmission encoding a message with space-time turbo code using feedback information of the channel gain or the phase in digital mobile communication system having a plurality of transmit antennas are disclosed. The space-time turbo code using the feedback scheme has better performance than that...

20060212773 - Ultrawideband architecture: Architectures for ultrawideband transmitters and receivers including parallel processing chains. Some embodiments include a two byte interface with a MAC, and some embodiments include mappers mapping I-channel and Q-channel information from separate encoders....

20060212775 - System and method for tolerating communication lane failures: A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of...

20060212776 - Adaptive soft demodulation for reception of distorted signals: A satellite communications system comprises a transmitting ground station, including a transmitter and a receiver, a satellite transponder and a receiving ground station. The transmitter transmits an uplink signal to the satellite transponder, which broadcasts the received uplink signal as a downlink signal to the receiving ground station. The transmitting...

20060212777 - Medium storage device and write path diagnosis method: A medium storage device writes the data on a medium by a write element and executes the diagnosis of a write system path without dropping the performance of the device. For a write command from a host, write data is stored in a data memory, a response is returned to...

20060212778 - Hardware based memory scrubbing: This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory...

20060212779 - Dynamic speed control method for storage device: A method is disclosed for adjusting the rotational speed of a disk drive. According to the method, the proportion of time which the disc drive is reading data from the disc during a unit time T is calculated. Then, the increase of the rotational speed of the motor is avoided...

20060212780 - Method for encoding/decoding error correcting code, transmitting apparatus and network: A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c/a is...

20060212781 - Enhanced turbo product code decoder system: A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum...

20060212782 - Efficient implementation of reed-solomon erasure resilient codes in high-rate applications: A new high-rate Reed-Solomon erasure resilient codes (ERC) system and method for generating and efficiently implementing novel Reed-Solomon erasure-resilient codes for use in high-rate applications. High-rate applications are applications where the number of coded messages is significantly higher (such as an order of magnitude) than the number of original messages....

20060212783 - Method and apparatus for combined encoder/syndrome computer with programmable parity level: Methods and apparatus are provided for a combined encoder/syndrome computer with a programmable parity level. In one embodiment, a circuit is disclosed that generates check symbols during an encoding operation and generates error syndromes during a decoding operation. The circuit comprises a plurality of subfilters grouped into a multiple degree...

20060212784 - Block decoding methods and apparatus: In an embodiment, a method includes performing a redundancy check to determine if a baseline bit sequence is compliant. When the baseline bit sequence is not compliant, the method additionally includes performing an iterative process until a compliant, candidate bit sequence is identified. The iterative process includes identifying one or...

20060212785 - Calculation processing device, calculation processing device design method, and logic circuit design method: An operation device having the element number and delay time of the operation circuitry reduced is realized by a purely logical approach. An operation method based on encoding is concretely and efficiently logic-designed to provide an encoding operation device operators of an operation system are extended if required to treat...

20060212786 - Viterbi path generation for a dynamic bayesian network: Methods, systems, and apparatus are provided to generate a Viterbi path for a DBN. The DBN is converted to a chain of junction trees, where each tree represents a decision-making process. The trees are forwardly iterated and the Viterbi path is generated during the forward iteration (forward pass). This is...

20060206748 - Backup system for digital surveillance system: The present invention relates to a backup system for digital surveillance system comprising video cameras, main server(s), networking facilities, a data-switching system, management server(s), backup server(s) and a central control station of an existing surveillance system, wherein a plurality of the video cameras connect to the main server(s); the microprocessor(s)...

20060206747 - Computer system and data backup method in computer system: A data intermediate server 300 comprises the functions of reading data stored in storage servers ST1 through ST3 and sending the data to a media server 600 according to backup commands received from a backup control device 400 over a local area network LAN4. The data intermediate server 300 and...

20060206749 - Network device and method of operation: A network device to maintain resource management within a network may comprise an emulator or watchdog that may send an emulation request to a resource manager for emulating a request of a client. Operability of the resource manager may be identified based on a reply of the resource manager to...

20060206751 - Nonvolatile memory system, nonvolatile memory device, data read method, and data read program: A nonvolatile memory device has a controller and flash memory. The flash memory stores user data and an error correcting code for correcting an error in the user data. When there is a read command from the outside, the user data and error correcting code are read from the flash...

20060206750 - Recording medium reproduction device: An abnormality in text data recorded on a CD conforming CD-TEXT format is detected so that a proper display can be created. In the case of text data recorded in a double-byte character code (step 1002), if the text data is XX 00 (step 1006) or 00 XX (step 1008),...

20060206754 - Disk array control device, storage system, and method of controlling disk array: A disk array control device controls a disk array in accordance with a disk access request from a host device. The disk array control device includes a cipher unit which ciphers write data transmitted from the host device, using a key unique to the disk array control device, a write...

20060206753 - Disk array system and rebuild method thereof: Disclosed is a disk array system which includes a plurality of disks constituting a disk array and a backup storage for backing up data in the disk array and performs control so that when a failed disk among the disks constituting the disk array is replaced with the replacement disk,...

20060206752 - Storage system, control method thereof, and program: When a write-back request for writing back new data in a cache memory to disk devices forming a redundant configuration of RAID is generated, a write-back processing unit, reserves a parity buffer area in the cache memory, generates new parity, and then, writes the new data and the new parity...

20060206755 - Method and apparatus for managing disc defect using temporary dfl and temporary dds including drive & disc information disc with temporary dfl and temporary dds: A write once disc includes a defect management area that is present in at least one of a lead-in area and a lead-out area; a temporary defect management area that is present in at least one of the lead-in area and the lead-out area; and a drive & disc information...

20060206756 - Method and apparatus for managing disc defect using temporary dfl and temporary dds including drive & disc information disc with temporary dfl and temporary dds: A write once disc includes a defect management area that is present in at least one of a lead-in area and a lead-out area; a temporary defect management area that is present in at least one of the lead-in area and the lead-out area; and a drive & disc information...

20060206757 - System and method for managing software patches: In one embodiment, the method includes determining a first set of software patches based on a group of software patches installed on a computing device and a group of available software patches. The method can also include receiving the first set of software patches over a network connection. The method...

20060206758 - Replicated state machine: A replicated state machine includes multiple state machine replicas. In response to a request from a client, the state machine replicas can execute a service for the request in parallel. Each of the state machine replicas is provided with a request manager instance. The request manager instance includes a distributed...

20060206759 - Universal serial bus backup device: A universal serial bus (USB) backup device includes a computer host having a backup application installed therein, and a USB bridging having a push button provided thereon. The USB bridging is internally provided with a virtual storage device. As a result, it is not necessary to connect a storage device...

20060206760 - Method and apparatus for supporting verification of hardware and software, and computer product: An apparatus for supporting a verification for each of a plurality of functions of a target object, includes: a receiving unit that receives a use case diagram that includes a plurality of use cases each of which corresponding to each of the functions; an extracting unit that extracts a relation...

20060206761 - System and method for on-board timing margin testing of memory modules: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and...

20060206762 - Circuit arrangement, in addition to method for identifying interruptions and short-circuits in coupled systems: The circuit configuration according to the invention comprises an electrical signal line loop, several partial systems connected thereto, which evaluate the state of the signal line loop, wherein a first selectable switching means is looped in between a first end of the signal line loop and a first voltage connection...

20060206763 - Debugging system, semiconductor integrated circuit device, microcomputer, and electronic apparatus: A debugging system, comprising a pin-saving type debug tool and a target system to be a debug target of the debug tool, the target system includes: an integrated circuit device incorporating a CPU and an inner debug module, the inner debug module having a function to carry out asynchronous communication...

20060206764 - Memory reliability detection system and method: A memory reliability detection system and a memory reliability detection method are applied in a computer device to perform a detection process on a motherboard according to a basic input/output system (BIOS) program during power-on of the computer device, so as to allow the computer device to successfully enter an...

20060206765 - Recording medium for storing start position information for each zone and method of managing data using the information: A recording medium for storing start position information for each zone and a method of managing data using the information. In a disc having a plurality of zones which form a group, and a spare area which is allocated at the start portion or the end portion of the group...

20060206766 - System and method for on-board diagnostics of memory modules: A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory...

20060206767 - Diagnosis of redundant signal output channels connected in parallel: The invention relates to a device and a method for testing for wire breakage with a redundant signal output. To ensure the most fail-safe output in particular of a digital signal, whilst at the same time supplying a diagnosis function, it is proposed that two digital output modules should be...

20060206768 - Method and system for synchronizing replicas of a database: A method and system for synchronizing replicas of a database. The method includes detecting a failure of update data from a first replica to be applied to a second replica; determining a cause of the failure; and resolving the cause of the failure. According to the method and system disclosed...

20060206769 - Memory system and method having selective ecc during low power refresh: A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low...

20060206770 - Non-volatile semiconductor memory with large erase blocks storing cycle counts: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in...

20060206771 - Read-only memory and operational control method thereof: A read-only memory (ROM) and a related method for controlling operations of the ROM are disclosed. A built-in self-test (BIST) circuit of the ROM verifies system data stored in a system area of a plurality of memory cells of the ROM according to verification data stored in a verification area...

20060206772 - Method and apparatus for supporting test pattern generation, and computer product: In an apparatus for supporting test pattern generation, when an acquiring unit acquires connection information of a target circuit to be tested and an untested path, a detecting unit detects paths between all flip-flop cells in the target circuit to create an untested path list. A path extracting unit extracts...

20060206773 - Tester simulation system and tester simulation method using same: It is an object of the invention to implement a tester simulation system capable of checking timing margins of an input pattern in a short time, and a tester simulation method using the same. The invention is an improvement of a tester simulation system for simulating a test by a...

20060206774 - Data transmitting/receiving system and method thereof: A data transmitter transmitting a data packet containing identifier information including a kind of data, a sequence of data, and/or a packet generating sequence. A receiver extracting a packet number and the identifier information for an error-receipt occurring data packet based upon the identifier information recorded in a header of...

20060206775 - Encoder based error resilience method in a video codec: Improved error resiliency of an encoding device, such as a video codec or encoder, operating in a compressed data transmission system, is achieved by enabling the encoding device to “shadow” or mimic the error conditions of a decoding device that receives and decodes compressed data sent by the encoding device....

20060206777 - Memory efficient streamlined transmitter with a multiple instance hybrid arq: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal in response to a first intermediate signal and a second intermediate signal. The second intermediate signal comprises a series of bit pairs. The second circuit comprises...

20060206776 - System and method for communicating data using iterative equalizing and decoding and recursive inner code: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing...

20060206782 - Data recording method, recording medium and reproduction apparatus: A recording medium for storing a data stream is comprised of first error correcting codes obtained by encoding first information, and second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability. The second error correcting codes have a...

20060206778 - Ldpc decoder for dvb-s2 decoding: The LDPC decoder includes a processor for updating messages exchanged iteratively between variable nodes and check nodes of a bipartite graph of the LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processor includes P processing units. First variable nodes and check nodes...

20060206779 - Method and device for decoding dvb-s2 ldpc encoded codewords: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable...

20060206781 - Method for puncturing low density parity check code: A method is provided for puncturing a low density parity check (LDPC) code decoded by a parity check matrix that is expressed by a factor graph including a check node and a bit node, being connected to each other at an edge, and includes a parity part having a dual...

20060206780 - Scrambler circuit, encoding device, encoding method and recording apparatus: An encoding device includes a buffer for performing EDC generation, scrambling and ECC generation on user data arranged along user data direction Q that is read out from a data buffer of SDRAM and storing the operation results, a substitution buffer for repeatedly reading out the user data by burst...

20060206783 - Communication terminal device, communication system, communication method, and program: A communication terminal device, a communication system, a communication method, and a program which allow efficient communication processing via multicast communication, along with power saving. The communication terminal devices includes a wireless communication unit comprising: a multicast ACK generating unit which makes it possible to transmit packets having an ACK...

20060206784 - Data transmitting/receiving system and method thereof: A data transmitter transmitting a data packet containing identifier information including a kind of data, a sequence of data, and/or a packet generating sequence. A receiver extracting a packet number and the identifier information for an error-receipt occurring data packet based upon the identifier information recorded in a header of...

20060206785 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060206786 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060206787 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060206788 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060200695 - System and method for re-routing failed video calls: A system and method for re-routing a failed video call schedules one or more reserve video devices for use in the event of failure of the video devices selected to support a video call. Upon detection of a failure of a video device, the video network platform re-establishes the video...

20060200696 - Storage system: There is provided architecture of a storage system, which has high scalability, low performance ununiformity, and strong fault tolerance, and a control method thereof. The storage system is connected to a host computer. The storage system has four or more nodes. Each node has a host interface unit which is...

20060200698 - Information replication system mounting partial database replications: An information recovery system mounts partial database replications, such as selected tablespaces, on a target host....

20060200697 - Storage system, control method thereof, and program: A RAID control unit forms a redundant configuration of RAID with respect to a physical device including a plurality of disk devices. A cache control unit processes data in page units corresponding to a stripe of the disk devices. A cache area placement unit, when it receives a write request...

20060200699 - Integrated circuit with error correction mechanisms to offset narrow tolerancing: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially...

20060200700 - Data storage system: A system for efficiently storing application data is disclosed which allows a practically infinite number of physically separate storage devices to be used as archival storage means by one or more application programs. Application data is organized among the devices such that files with a similar expiry date (that is...

20060200701 - Kernel-mode in-flight recorder tracing mechanism: The subject invention relates to systems and methods that automatically monitor and record component-related activities to support remote diagnostic capabilities. In one aspect, an automated computer diagnostic system is provided. The system includes a trace component that monitors computer-related activities between a driver and an operating system component. The trace...

20060200702 - Method and system for recovering data from a hung application: An application is associated with a main thread that is running on an operating system. A secondary thread monitors the main thread to determine whether the application is in a hang state. A ghost window that matches the hung application window is displayed on a user interface and the hung...

20060200704 - Output system, device management apparatus and program, and output method: An output system including an output data storage section storing output data, an output data saving section saving the output data to the storage section, an authentication information acquiring section acquiring authentication information, a usability determining section determining usability of the output data depending on acquired authentication information, a power...

20060200703 - System and method for reduction of wait time for software updates: A system and method is disclosed for performing maintenance on a mission critical system while minimizing the unavailability of the system to the user. In one embodiment, the mission critical system is provided with software storage/media including at least a production portion and a separately and/or independently accessible/usable maintenance portion....

20060200705 - Method, system and program product for monitoring a heartbeat of a computer application: Under the present invention, parameters and configuration information (e.g., a file) for the monitoring process are read. Among other things, the configuration information specifies names of message queues for applications to be monitored. Thereafter, heartbeat messages are published to the message queues specified in the configuration information. If the heartbeat...

20060200707 - Image-processing system, image-processing method, and computer readable storage medium: An image-processing system having an image processor which performs image input or output processing, and a management communication apparatus connected to the image processor and connected via a communication line to a management center, the image processing system having: a retaining unit, provided in a nontarget apparatus which is not...

20060200706 - Method and device for building a variable-length error-correcting code: The invention relates to the construction of variable-length error-correcting (VLEC) code, using the main steps of: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples distant of the minimum diverging distance d′min! from the codewords...

20060200710 - Bit error rate performance estimation and control: There is provided a method and system for obtaining an enhanced estimate of bit error rate performance. A receiver module counts a predetermined number of bit errors and concurrently measures the time taken for the predetermined number of bit errors to occur. In this way an estimate of the bit...

20060200709 - Method and a device for processing bit symbols generated by a data source; a computer readable medium; a computer program element: A method for processing bit symbols generated by a data source, in particular a video, still image or audio source, comprising the following steps of constructing a plurality of bit-planes from the data source, each bit-plane comprising a plurality of bit-plane symbols; scanning the bit-plane symbols of each bit-plane to...

20060200708 - System and method for network error rate testing: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network...

20060200711 - Network diagnostic systems and methods for processing network messages: A networking system is provided. The networking system may include a diagnostic module. The diagnostic module may perform any of a variety of network diagnostic functions. The diagnostic module may include an analysis module, which may receive messages and perform any of a variety of network diagnostic functions using the...

20060200713 - Method and apparatus for memory self testing: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence...

20060200712 - System and method for testing memory: In another embodiment, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical...

20060200714 - Test equipment for semiconductor: A test equipment for semiconductor according to the present invention comprises a equipment main body and a memory cell provided in an outside of the equipment main body, wherein the equipment main body comprises a configurable device capable of making a hardware construction in a programmable manner and an interface...

20060200715 - Automatically detecting and routing of test signals: A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths (240, 242, 244). According to an example embodiment of the present invention, a microcontroller (205) is programmed to monitor input nodes (210) using an interrupt routine for automatically...

20060200717 - Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination: In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a second test operation is...

20060200716 - Skewed inverter delay line for use in measuring critical paths in an integrated circuit: An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay...

20060200718 - Boundary scan testing system: A boundary scan testing system may include a baseboard (102, 202), a computing module (104, 204) coupled to the baseboard, and a boundary scan test module (106, 206, 306, 406) coupled to the computing module, where the boundary scan test module is coupled to execute a boundary scan test (120,...

20060200719 - System and method for performing logic failure diagnosis using multiple input signature register output streams: A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a predetermined number of scan chains. During each scan cycle, the...

20060200720 - Generating and verifying read and write cycles in a pci bus system: A peripheral device to generate read and write cycles on a PCI bus comprises a PCI bus interface. A control unit has a data pattern generator to source a data pattern to a target via the interface during a write operation and to verify an incoming data pattern from the...

20060200721 - Tester simulation system and tester simulation method using same: It is an object of the invention to implement a tester simulation system capable of finding margins of respective expected value determining timings in a short time, and a tester simulation method using the same. The invention is an improvement of a tester simulation system for executing a test of...

20060200722 - Method for selection of the appropriate harq retransmission scheme for data transmission, a base station and a program module therefore: The invention concerns a method for selection of the appropriate HARQ (Hybrid Automatic Repetition Request) retransmission scheme within a base station for data transmission over a communication network to a terminal, whereby said selection is performed repeatedly during data transmission by means of at least one parameter that defines the...

20060200725 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060200723 - Method and apparatus for implementing enhanced vertical ecc storage in a dynamic random access memory: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can...

20060200724 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning: System and method for Slepian-Wolf coding using channel code partitioning. A generator matrix is partitioned to generate multiple sub-matrices corresponding respectively to multiple correlated data sources. The partitioning is in accordance with a rate allocation among the correlated data sources. Corresponding parity matrices may be generated respectively from the sub-matrices,...

20060200729 - Data storing method of dynamic ram and semiconductor memory device: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error...

20060200726 - Failure trend detection and correction in a data storage array: Method and apparatus for detecting and correcting parametric failure trends in a data storage array. A plurality of data storage devices, such as hard disc drives, are arranged to form a multi-device addressable memory array space. A controller controls access to the array space, and is configured to accumulate operational...

20060200727 - Semiconductor device: When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention...

20060200728 - Synchronous semiconductor storage device having error correction function: A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines...

20060200730 - Systems and methods for delineating a cell in a communications network: A method of performing cell delineation in a communications network is described. The method includes providing a data cell defined based on a communications protocol. The data cell forms at least a portion of a data stream. The method further includes mapping the data cell into frames defined based on...

20060200731 - System and method of error detection for unordered data delivery: A system and method of error detection for unordered data delivery. A data set is received, the data set including a plurality of data segments, each having a descriptor; a data packet for each of the plurality of data segments, each of the data packets including the data segment and...

20060200732 - Method and apparatus for providing a processor based nested form polynomial engine: A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data...

20060200733 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix may be partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning may be performed in accordance with a rate allocation among the plurality of correlated data sources....

20060200695 - System and method for re-routing failed video calls: A system and method for re-routing a failed video call schedules one or more reserve video devices for use in the event of failure of the video devices selected to support a video call. Upon detection of a failure of a video device, the video network platform re-establishes the video...

20060200696 - Storage system: There is provided architecture of a storage system, which has high scalability, low performance ununiformity, and strong fault tolerance, and a control method thereof. The storage system is connected to a host computer. The storage system has four or more nodes. Each node has a host interface unit which is...

20060200698 - Information replication system mounting partial database replications: An information recovery system mounts partial database replications, such as selected tablespaces, on a target host....

20060200697 - Storage system, control method thereof, and program: A RAID control unit forms a redundant configuration of RAID with respect to a physical device including a plurality of disk devices. A cache control unit processes data in page units corresponding to a stripe of the disk devices. A cache area placement unit, when it receives a write request...

20060200699 - Integrated circuit with error correction mechanisms to offset narrow tolerancing: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially...

20060200700 - Data storage system: A system for efficiently storing application data is disclosed which allows a practically infinite number of physically separate storage devices to be used as archival storage means by one or more application programs. Application data is organized among the devices such that files with a similar expiry date (that is...

20060200701 - Kernel-mode in-flight recorder tracing mechanism: The subject invention relates to systems and methods that automatically monitor and record component-related activities to support remote diagnostic capabilities. In one aspect, an automated computer diagnostic system is provided. The system includes a trace component that monitors computer-related activities between a driver and an operating system component. The trace...

20060200702 - Method and system for recovering data from a hung application: An application is associated with a main thread that is running on an operating system. A secondary thread monitors the main thread to determine whether the application is in a hang state. A ghost window that matches the hung application window is displayed on a user interface and the hung...

20060200704 - Output system, device management apparatus and program, and output method: An output system including an output data storage section storing output data, an output data saving section saving the output data to the storage section, an authentication information acquiring section acquiring authentication information, a usability determining section determining usability of the output data depending on acquired authentication information, a power...

20060200703 - System and method for reduction of wait time for software updates: A system and method is disclosed for performing maintenance on a mission critical system while minimizing the unavailability of the system to the user. In one embodiment, the mission critical system is provided with software storage/media including at least a production portion and a separately and/or independently accessible/usable maintenance portion....

20060200705 - Method, system and program product for monitoring a heartbeat of a computer application: Under the present invention, parameters and configuration information (e.g., a file) for the monitoring process are read. Among other things, the configuration information specifies names of message queues for applications to be monitored. Thereafter, heartbeat messages are published to the message queues specified in the configuration information. If the heartbeat...

20060200707 - Image-processing system, image-processing method, and computer readable storage medium: An image-processing system having an image processor which performs image input or output processing, and a management communication apparatus connected to the image processor and connected via a communication line to a management center, the image processing system having: a retaining unit, provided in a nontarget apparatus which is not...

20060200706 - Method and device for building a variable-length error-correcting code: The invention relates to the construction of variable-length error-correcting (VLEC) code, using the main steps of: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples distant of the minimum diverging distance d′min! from the codewords...

20060200710 - Bit error rate performance estimation and control: There is provided a method and system for obtaining an enhanced estimate of bit error rate performance. A receiver module counts a predetermined number of bit errors and concurrently measures the time taken for the predetermined number of bit errors to occur. In this way an estimate of the bit...

20060200709 - Method and a device for processing bit symbols generated by a data source; a computer readable medium; a computer program element: A method for processing bit symbols generated by a data source, in particular a video, still image or audio source, comprising the following steps of constructing a plurality of bit-planes from the data source, each bit-plane comprising a plurality of bit-plane symbols; scanning the bit-plane symbols of each bit-plane to...

20060200708 - System and method for network error rate testing: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network...

20060200711 - Network diagnostic systems and methods for processing network messages: A networking system is provided. The networking system may include a diagnostic module. The diagnostic module may perform any of a variety of network diagnostic functions. The diagnostic module may include an analysis module, which may receive messages and perform any of a variety of network diagnostic functions using the...

20060200713 - Method and apparatus for memory self testing: A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence...

20060200712 - System and method for testing memory: In another embodiment, a method for testing a memory having a plurality of bits is provided and includes initializing each value in a first register to zero. Next, each value in a second register is initialized to one. Further, each bit in the memory is initialized to zero. A logical...

20060200714 - Test equipment for semiconductor: A test equipment for semiconductor according to the present invention comprises a equipment main body and a memory cell provided in an outside of the equipment main body, wherein the equipment main body comprises a configurable device capable of making a hardware construction in a programmable manner and an interface...

20060200715 - Automatically detecting and routing of test signals: A circuit testing approach involves configurable switch control for automatically detecting and routing test signals along a plurality of test circuit paths (240, 242, 244). According to an example embodiment of the present invention, a microcontroller (205) is programmed to monitor input nodes (210) using an interrupt routine for automatically...

20060200717 - Semiconductor device including fuse and method for testing the same capable of suppressing erroneous determination: In a method for testing whether or not a fuse on a semiconductor substrate is disconnected, a first test operation is performed upon the fuse by determining whether or not a resistance value of the fuse is larger than a first threshold resistance value. Then, a second test operation is...

20060200716 - Skewed inverter delay line for use in measuring critical paths in an integrated circuit: An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay...

20060200718 - Boundary scan testing system: A boundary scan testing system may include a baseboard (102, 202), a computing module (104, 204) coupled to the baseboard, and a boundary scan test module (106, 206, 306, 406) coupled to the computing module, where the boundary scan test module is coupled to execute a boundary scan test (120,...

20060200719 - System and method for performing logic failure diagnosis using multiple input signature register output streams: A logic failure diagnosis system for performing logic failure diagnosis and methods for manufacturing and using same. The logic failure diagnosis system includes a signature register system and a space compaction system and, during testing, receives data values from a predetermined number of scan chains. During each scan cycle, the...

20060200720 - Generating and verifying read and write cycles in a pci bus system: A peripheral device to generate read and write cycles on a PCI bus comprises a PCI bus interface. A control unit has a data pattern generator to source a data pattern to a target via the interface during a write operation and to verify an incoming data pattern from the...

20060200721 - Tester simulation system and tester simulation method using same: It is an object of the invention to implement a tester simulation system capable of finding margins of respective expected value determining timings in a short time, and a tester simulation method using the same. The invention is an improvement of a tester simulation system for executing a test of...

20060200722 - Method for selection of the appropriate harq retransmission scheme for data transmission, a base station and a program module therefore: The invention concerns a method for selection of the appropriate HARQ (Hybrid Automatic Repetition Request) retransmission scheme within a base station for data transmission over a communication network to a terminal, whereby said selection is performed repeatedly during data transmission by means of at least one parameter that defines the...

20060200725 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060200723 - Method and apparatus for implementing enhanced vertical ecc storage in a dynamic random access memory: A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that multiple locations inside a group can...

20060200724 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning: System and method for Slepian-Wolf coding using channel code partitioning. A generator matrix is partitioned to generate multiple sub-matrices corresponding respectively to multiple correlated data sources. The partitioning is in accordance with a rate allocation among the correlated data sources. Corresponding parity matrices may be generated respectively from the sub-matrices,...

20060200729 - Data storing method of dynamic ram and semiconductor memory device: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error...

20060200726 - Failure trend detection and correction in a data storage array: Method and apparatus for detecting and correcting parametric failure trends in a data storage array. A plurality of data storage devices, such as hard disc drives, are arranged to form a multi-device addressable memory array space. A controller controls access to the array space, and is configured to accumulate operational...

20060200727 - Semiconductor device: When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention...

20060200728 - Synchronous semiconductor storage device having error correction function: A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines...

20060200730 - Systems and methods for delineating a cell in a communications network: A method of performing cell delineation in a communications network is described. The method includes providing a data cell defined based on a communications protocol. The data cell forms at least a portion of a data stream. The method further includes mapping the data cell into frames defined based on...

20060200731 - System and method of error detection for unordered data delivery: A system and method of error detection for unordered data delivery. A data set is received, the data set including a plurality of data segments, each having a descriptor; a data packet for each of the plurality of data segments, each of the data packets including the data segment and...

20060200732 - Method and apparatus for providing a processor based nested form polynomial engine: A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data...

20060200733 - Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning: System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix may be partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning may be performed in accordance with a rate allocation among the plurality of correlated data sources....