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Error detection/correction and fault detection/recovery August inventions list 08/06

20060195715 - System and method for migrating virtual machines on cluster systems: In one embodiment, a method comprises executing a plurality of virtual machines on a plurality of nodes of a cluster computing system, wherein at least one application is executed within each of the plurality of virtual machines, generating data that is related to performance of applications in the virtual machines,...

20060195716 - Central monitoring/managed surveillance system and method: A method for remotely monitoring a first location. The method includes providing surveillance equipment at the first location. Data is transmitted from the security equipment via IP connectivity to a second location that is remote from the first location. The data is monitored in real-time from the second location....

20060195717 - Mutli-layered information recording medium, reproduction apparatus, recording apparatus, reproduction method, and recording method: A multi-layered information recording medium comprising a plurality of recording layers, a user data area for recording user data, provided in at least two of the plurality of recording layers, and a defect list storing area for storing a defect list. When at least one defective area is detected in...

20060195718 - Mutli-layered information recording medium, reproduction apparatus, recording apparatus, reproduction method, and recording method: A multi-layered information recording medium comprising a plurality of recording layers, a user data area for recording user data, provided in at least two of the plurality of recording layers, and a defect list storing area for storing a defect list. When at least one defective area is detected in...

20060195719 - Mutli-layered information recording medium, reproduction apparatus, recording apparatus, reproduction method, and recording method: A multi-layered information recording medium comprising a plurality of recording layers, a user data area for recording user data, provided in at least two of the plurality of recording layers, and a defect list storing area for storing a defect list. When at least one defective area is detected in...

20060195720 - Amplifier fault detection circuit: An amplifier (1) adapted to receive an input signal and to generate an output signal at an amplifier output (7) according to the input signal, the amplifier (1) comprising: a feedback circuit arranged to provide a feedback signal indicative of the output signal; an error signal generating circuit (12, 44)...

20060195721 - Method and apparatus for qualifying debug operation using source information: A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provides debug information related to the processor. The circuitry identifies which of a plurality...

20060195722 - Pattern generator and testing apparatus: There is provided a pattern generator that generates a test pattern for performing a scan test for an electronic device. The pattern generator includes: a main memory that stores a scan pattern data block including pattern data for performing the scan test and a scan sequence data block including an...

20060195723 - Securing the test mode of an integrated circuit: An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable of being connected to the logic units, and having terminals for reception of command signals to write data into...

20060195724 - Method for determining code coverage: A method and system for determining code coverage of one or more software modules is disclosed. The disclosed method and system uses an enumeration module, a code coverage module and an analysis module. The enumeration module is used to identify portions of the code in the software module for which...

20060195727 - Data transmission management system, a mobile device and a server used therein: A data transmission control system includes a server configured to store an application program having a data area in which transmission control information containing a threshold value used to detect abnormal data transmission is stored and to allow the application program to be downloaded in response to a request, and...

20060195726 - Method and apparatus for semiconductor testing: A semiconductor testing system comprising an input; a display; multiple testing units; a memory in which is stored multiple applications that specify the operating procedure of the testing units and multiple categories that are related to the applications; and a controller that has the function of displaying the categories, displaying...

20060195725 - Method and system for generating and monitoring variable load on an application under test: A facility executes on a central computer system and applies a time-varying load to an application program under test (AUT). The facility executes in a multiple number of modes or hierarchical levels as dictated by information provided in its configuration file. An instance of the facility executing at the highest...

20060195729 - Reconfigurable processor module comprising hybrid stacked integrated circuit die elements: A reconfigurable processor module comprising hybrid stacked integrated circuit (“IC”) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (“FPGA”) die elements and interconnecting the same utilizing contacts that...

20060195728 - Storage unit data transmission stability detecting method and system: A storage unit data transmission stability detecting method and system is proposed, which is designed for use in conjunction with a storage unit, such as a RAID (Redundant Array of Independent Disks) unit, for the purpose of detecting the data transmission stability of the RAID unit; and which is characterized...

20060195730 - Method and apparatus for file management: File management method having first and second processing modes for storing file type information for discrimination between first and second processing modes in recording medium as file management information associated with file for file management. In first processing mode, when data in the form of file is written on a...

20060195731 - First failure data capture based on threshold violation: A first failure data capture mechanism receives threshold violation events. The end user may configure which threshold violations would trigger first failure data capture. A correlator may be used to select only the related log and trade data to fit the specific application. When a predetermined threshold violation event is...

20060195733 - Arc fault and ground fault circuit interrupter tester apparatus and method: A circuit tester comprising an AFCI (FIGS. 1 and 2) having two pairs of leads connected to the opposite end of each circuit tester in series for connecting an AFCI with ground fault circuit technology capabilities between an electrical circuit load and a power source to indicate electrical circuit and/or...

20060195735 - Circuit for distributing a test signal applied to a pad of an electronic device: The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the...

20060195736 - Electro-optical device: An electro-optical device includes a substrate, a plurality of unit circuits that includes a plurality of scanning lines, a plurality of data lines and electro-optical elements provided corresponding to intersecting regions of the scanning lines and the data lines and is formed in a display region of the substrate, a...

20060195732 - Method and system for executing test cases for a device under verification: The present invention relates to a method and system for executing test cases for a device by mapping sequences of instructions and/or operation into a data flow graph, which data flow graph includes a plurality of nodes (20) and a plurality of arcs (22) connecting the nodes (20). The method...

20060195734 - Semiconductor memory device and stress testing method thereof: A semiconductor memory device includes a core chip having at least memory cells formed in the core chip, an interface chip having at least peripheral circuits of the memory cells formed in the interface chip, and an external terminal group. The external terminal group includes at least a core power...

20060195738 - Merged misr and output register without performance impact for circuits under test: The output register of an array and the Multiple Input Signature Register (MISR) logic is implemented with one set of L1/L2 master/slave latches and single additional slave latch. This new combined logic uses less critical area on a chip without a performance impact on the array access time or circuit...

20060195737 - System and method for characterization of certain operating characteristics of devices: A system and method is provided for improving integrated circuit device characterization without requiring external tester hardware. On-chip circuitry is provided to measure the delay of a signal through a given scan chain when the scan chain latches have been placed in flush mode. A control signal generated by the...

20060195739 - Multiple device scan chain emulation/debugging: A method and system is provided for emulating individual JTAG devices in a multiple device boundary scan chain. The method includes coupling an emulator to the scan chain, and obtaining the topology of the scan chain. One device within the scan chain is then selected, and at least one other...

20060195740 - Clock duty cycle based access timer combined with standard stage clocked output register: An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured....

20060195741 - Shift clock generator, timing generator and test apparatus: There is provided a shift clock generator for phase-shifting a shift clock by inserting insertion pulses into the shift clock, wherein an insertion pulse generating section has a compensation memory for storing compensation data for calculating a number of insertion pulses to be inserted into the shift clock with respect...

20060195742 - Semiconductor memory device and method of testing the same: A semiconductor memory device includes at least one first built in self test (BIST) circuit configured to generate test pattern data, and at least one second BIST circuit configured to receive the test pattern data as received test pattern data and compare the received test pattern data to the test...

20060195743 - Semiconductor memory device: In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to...

20060195744 - Method and apparatus to simulate automatic test equipment: A virtual tester that simulates automatic test equipment (ATE). A translator converts program code of the ATE to pattern information and timing information. The virtual tester tests a software representation of a circuit, based on the program code of the ATE. The virtual tester uses the pattern information and/or the...

20060195745 - Methods and systems for repairing applications: In accordance with the present invention, computer implemented methods and systems are provided that allow an application to automatically recover from software failures and attacks. Using one or more sensors, failures may be detected in the application. In response to detecting the failure, the portion of the application's code that...

20060195746 - Variable clocked scan test improvements: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting...

20060195749 - Calibration control for pin electronics: An integrated circuit for automatic calibration control of pin electronics is disclosed. The integrated circuit includes a substrate, and both pin electronics and a calibration circuit integral with the substrate. The calibration circuit is dedicated to a single channel of automatic testing equipment for a single pin of a device...

20060195748 - Electronic product testing procedure supervising method and system: An electronic product testing procedure supervising method and system is proposed, which is designed for use in conjunction with a testing platform and a supervising platform in a factory, and which is characterized by the capability of recording a set of data related to the performance of each step in...

20060195747 - Method and system for scheduling tests in a parallel test system: An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a...

20060195751 - Fault recovery for real-time, multi-tasking computer system: System and methods for providing a recoverable real time multi-tasking computer system are disclosed. In one embodiment, a system comprises a real time computing environment, wherein the real time computing environment is adapted to execute one or more applications and wherein each application is time and space partitioned. The system...

20060195750 - Simplifying troubleshooting of errors in configurable parameter values associated with computer supported business-flows: A troubleshooting tool for simplifying troubleshooting of errors in configurable parameter values associated with computer supported business-flows. The parameter values affecting the business-flows are stored in the tables of a database system in one embodiment. An administrator specifies the set of parameters which determine the specific row of the table...

20060195752 - Power saving method for coded transmission: Conserving power for coded transmissions comprises ceasing to process parity packets once associated data packets are deemed correct or corrected. Once data packets are deemed correct or corrected, the receiving unit can shut off during the transmission of parity packets....

20060195753 - Bitmap manager, method of allocating a bitmap memory, method of generating an acknowledgement between network entities, and network entity implementing the same: A bitmap manager, a method of allocating a bitmap memory, a method of generating an acknowledgement between network entities, and a network entity implementing the same. The bitmap manager may include a bitmap memory for storing a block acknowledge of received frames based on a bitmap, a bitmap management information...

20060195754 - Amp (accelerated message passing) decoder adapted for ldpc (low density parity check) codes: AMP (Accelerated Message Passing) decoder adapted for LDPC (Low Density Parity Check) codes. A novel approach is presented by which the LDPC coded signals may be decoded in a more efficient, faster, and less computationally intensive manner. Soft bit information, generated from decoding a higher layer square sub-matrix of a...

20060195755 - Method and system for reducing volatile dram power budget: A portable device (114) includes a power source (120), a volatile memory (118) requiring refreshing to avoid data loss, and a memory management module (116). The volatile memory (118) is operably coupled to the power source (120) for power. The memory management module (116) is operably coupled to the volatile...

20060195756 - Radio transmitter apparatus, radio receiver apparatus, and radio transmission method: Transmission data in a different interleaving pattern is input for each retransmission via interleaver 31 to outer coding processing section 32 that performs coding processing with a strong correction capability for the burst error such as Reed-Solomon coding. Inner coding processing section 33 performs coding processing with a strong correction...

20060195757 - Error correction method for reed-solomon product code: The present invention relates to soft-decision decoding of Reed-Solomon product codes. According to the invention, a method for error correction of an encoded data stream comprises the steps of: saving the demodulated data stream in an input buffer; performing a first correction process on-the-fly in the input buffer; transferring the...

20060195763 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060195764 - Coding apparatus and decoding apparatus for transmission/storage of information: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code...

20060195762 - Hs-dsch transmitter and crc calculator therefor in a w-cdma system: An HS-DSCH transmitter in a W-CDMA system is provided. In the HS-DSCH transmitter, a memory stores input transmission data. A bit scrambling code ROM stores random sequences for bit scrambling of the input data. A CRC calculator generates a bit scrambled sequence by attaching a CRC to the input transmission...

20060195759 - Method and apparatus for calculating checksums: A method for calculating checksums includes calculating a first checksum based at least in part on a first block of data, and calculating a partial checksum based at least in part on a second block of data. The second block of data comprises a data portion followed by a fill...

20060195761 - Method of generating low-density parity check matrix and method of generating parity information using the low-density parity check matrix: A method of generating a parity check matrix and a method of generating parity information using the parity check matrix, wherein the method of generating a parity check matrix includes selecting elements of a low-density parity check (LDPC) matrix such that every element of a top right corner portion of...

20060195758 - Method of storing information on an optical disc: A method is described for writing information to a record medium (2). 152 code words [11(j)] each having 248 bytes [mI(ij)] and 12 BIS words each having 62 BIS bytes [b2(r,s)] are combined to form an ECC block (M3) having 38 440 elements [m3(v,w)], which elements are consecutively written. Also,...

20060195760 - Permuting mtr code with ecc without need for second mtr code: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint. In one embodiment, a system for processing data comprises a maximum transition run or timing-varying maximum transition run (hereinafter MTR) encoder configured to...

20060195765 - Accelerating convergence in an iterative decoder: An iterative forward error control code (FECC) decoder (28; 28′) is disclosed. The decoder (28; 28′) operates by adjusting probability values for codeword bits at a selected iteration in the decoding sequence. According to one disclosed embodiment, those probability values that are above a certain threshold value prior to one...

20060195766 - Semiconductor memory device: An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010-1017), and a...

20060195767 - Supporting hybrid automatic retransmission request in orthogonal frequency division multiplexing access radio access system: A method of supporting a hybrid automatic retransmission request (HARQ) in an orthogonal frequency division multiplexing access (OFDMA) radio access system is disclosed. Preferably, the method comprises receiving a downlink data frame comprising a data map information element and a data burst comprising a plurality of layers, wherein each layer...

20060195768 - Techniques for performing reduced complexity galois field arithmetic for correcting errors: Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(23), GF(23) is extended to...

20060195769 - Techniques for performing galois field logarithms for detecting error locations that require less storage space: To perform error detection and correction on a data sector, syndromes are calculated and used to determine error values and error locations. Logarithmic calculations in Galois field need to be performed to determine the error locations using the syndromes. Finite field vectors are represented as “complex” numbers of the form...

20060195770 - System and method for multi-mode multi-state path metric addressing: A wireless communication device comprises a first memory unit operable to store current and next stage memory low data of a path metric calculation of a trellis-based decoding processor, a second memory unit operable to store current and next stage memory high data of the path metric calculation of the...

20060195771 - Application of a meta-viterbi algorithm for communication systems without intersymbol interference: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed...

20060195772 - Method and apparatus for evaluating performance of a read channel: Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed,...

20060195773 - Viterbi decoder architecture for use in software-defined radio systems: A reconfigurable Viterbi decoder comprising a reconfigurable data path and a programmable finite state machine that controls the reconfigurable data path. The reconfigurable data path comprises a plurality of reconfigurable functional blocks including: i) a reconfigurable branch metric calculation block; and ii) a reconfigurable add-compare-select and path metric calculation block....

20060195774 - Error correction circuit and method: The present invention includes an error correction circuit with a data memory, a write tree, a parity memory, and a read tree. The data memory is configured to hold a set of data. The write tree is configured to receive the set of data and to generate parity data. The...

20060195775 - Method and apparatus for providing a read channel having combined parity and non-parity post processing: A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events...

20060195776 - Linear feedback shift register first-order noise generator: A first-order signal generator (135). The generator comprises a shift register (210′) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for...

20060190759 - Processing apparatus: A processing apparatus includes a plurality of operation units each of which performs a given operation for an input operand in accordance with an operating instruction and outputs an exception flag when a result of the operation is false, a first network which connects the storage unit which stores the...

20060190760 - System and method for failover: A node 1 and a node 2 are in a mutual failover relationship and share information used in failover through a shared LU. Of filesystems FS1A, FS1B that are mounted at the node 1, the actions of level 1 are allocated to FS1A and the actions of level 2 are...

20060190761 - Method and mechanism of improving system utilization and throughput: Disclosed are methods, systems, and mediums for improving system utilization and throughput. In some embodiments, application requests received at a primary site are routed to a secondary site for processing when the requests are found to be suitable for processing at the secondary site....

20060190763 - Redundant storage array method and apparatus: The present invention is directed to a data storage system utilizing a number of data storage devices. Each of the data storage devices stores primary and mirrored copies of data. Furthermore, the data is arranged such that no one data storage device stores both the primary and mirrored copies of...

20060190762 - Semiconductor memory and method of storing configuration data: Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration...

20060190765 - Method and system for correcting errors in read-only memory devices, and computer program product therefor: A system for correcting errors in read-only memory devices by means of memory patches, wherein patch data is used as read data in the place of erroneous data stored at a given location in the memory. The system includes a processing core, such as an ARM processor, adapted to perform...

20060190764 - System for providing an alternative communication path in a sas cluster: The present invention is directed to a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may establish the alternative path for communication but...

20060190766 - Disaster recovery framework: A system and method of orchestrating failover operations of servers providing services to an internal computer network includes a DR server configured to execute a control script that performs a failover operation. Information needed to perform the failover operation is stored on the DR server thereby eliminating the need to...

20060190767 - Optimization by using output drivers for discrete input interface: The invention relates to design optimization of microprocessors using spare driver outputs for discrete input interfaces. An output driver or pre-FET driver is used to interface a discrete input for a microprocessor. To read the discrete interface, a fault detection mechanism of the pre-FET driver or the output driver is...

20060190768 - Rack management system, management terminal, configuration retaining apparatus and rack apparatus: In order to rapidly specify a failed apparatus in such an environment at a data center that handles a large number of electronic devices exemplified by servers with ease so that maintainability can be improved, when each configuration retaining apparatus receives information concerning an apparatus specified by a management terminal,...

20060190772 - File control system and file control device: A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices,...

20060190770 - Forward projection of correlated software failure information: A method, apparatus and article of manufacture are provided for analyzing a program for failures. Error reporting data concerning the program's failures is collected from customer computers. Source code associated with the program is analyzed to generate analysis data. The analysis data is correlated with the error reporting data to...

20060190769 - Method and system for setting a breakpoint: A method for setting a breakpoint includes the following: receiving an input specifying a location for insertion of a breakpoint in the executable program; determining a breakpoint address for insertion of the breakpoint in the executable program based on the specified location of the breakpoint; writing a breakpoint instruction into...

20060190773 - Software self-repair toolkit for electronic devices: A device and method supporting the identification and correction of firmware and/or software errors is described. Upon the occurrence of a firmware/software error or exception, an embodiment in accordance with the present invention may gather parameters for identifying the error or exception, and the execution environment in which the error...

20060190771 - System and method for model based generation of application programming interface test code: Systems and methods for model based generation of API test code are disclosed. A number of interfaces are employed to enable flexible and extensible visual representations of test parameter input data. One such interface may enable diagramming of a test model that depicts sequencing dependencies among a set of API's...

20060190774 - Network router having an internal automated backup: A network router having an internal automated backup is provided. Specifically, the present invention provides a network router having at least one primary port facility, a switched fabric, and a backup card array. When a router card connected to a primary port facility fails, a failure message is automatically sent...

20060190775 - Creation of highly available pseudo-clone standby servers for rapid failover provisioning: Near clones for a set of targeted computing systems are provided by determining a highest common denominator set of components among the computing systems, producing a pseudo-clone configuration definition, and realizing one or more pseudo-clone computing systems as partially configured backups for the targeted computing systems. Upon a planned failover,...

20060190776 - Method and device for generating and detecting a fingerprint functioning as a trigger marker in a multimedia signal: This invention relates to a device and a method of relating one or more trigger actions with a multimedia signal and corresponding method and device for detecting one or more trigger actions in a multimedia signal. One fingerprint is generated on the basis of a segment of the multimedia signal...

20060190777 - Memory command unit throttle and error recovery: A network device for minimizing latency and correcting errors associated with information transmitted from an external memory device. The network device includes a management unit for requesting information stored on at least one external memory device. The network device also includes a command unit for transmitting a request from the...

20060190780 - High reliability memory module with a fault tolerant address and command bus: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a...

20060190778 - Method for reducing sram test time by applying power-up state knowledge: Methods (400, 500, and 600) are disclosed for testing a memory device by tailoring an algorithm (460) used in the testing based on the preferred or intrinsic data state 425 that is obtained upon power-up of an advanced technology SRAM memory device (100). The methods (400, 500, and 600) take...

20060190779 - Semiconductor integrated circuit for reducing number of contact pads to be probed in probe test: A semiconductor chip is composed of first and second contact pads; a first latch circuit connected with the first contact pad; a second latch circuit connected with the second contact pads; an internal circuit electrically connected with the first and second latch circuits; and a control circuit controlling data transfer...

20060190781 - Clock control circuit for test that facilitates an at speed structural test: When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a...

20060190782 - Mechanism to provide test access to third-party macro circuits embedded in an asic (application-specific integrated circuit): Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the...

20060190783 - On-chip high-speed serial data analyzers, systems, and associated methods: In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined voltage to produce analysis data, and capturing the...

20060190785 - In-situ monitor of process and device parameters in integrated circuits: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing...

20060190784 - Method and circuit using boundary scan cells for design library analysis: A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan...

20060190786 - Semiconductor integrated circuit and method of tesiting semiconductor integrated circuit: A semiconductor integrated circuit having an internal circuit which is tested based on a scanning method is provided. The internal circuit has: memory elements including a first memory element and a second memory element; combinational circuits including a first combinational circuit receiving an external input data, a second combinational circuit...

20060190787 - Target system, debugging system, integrated circuit device, microcomputer and electronic apparatus: A debugging system that includes a debugging tool in a small pin count package and a target system that is a debugging object of the debugging tool, wherein the substrate of the target system includes an integrated circuit device with a built-in CPU and a communicator for generating and outputting...

20060190788 - Method and apparatus for verifying memory testing software: A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester....

20060190789 - Synchronization point across different memory bist controllers: A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates...

20060190790 - In-situ monitor of process and device parameters in integrated circuits: In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can...

20060190791 - Enabling special modes within a digital device: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test...

20060190792 - Electronic element comprising an electronic circuit which is to be tested and test system arrangement which is used to test the electronic element: An electronic element, test system and method of testing an electronic circuit are provided. The electronic circuit has input and output terminals. The input terminals receive a test signal sequence to test the electronic circuit. Actual value signals of a 3-value logic of the electronic circuit are provided at the...

20060190793 - Establishing a reference bit in a bit pattern: A method establishes a reference bit in a bit pattern. The method includes (a) identifying a series of bit sequences in the bit pattern including all bit sequences having the largest number of consecutive bits with a common logic state and (b) assigning a reference bit based on one bit...

20060190794 - Test apparatus and testing method: There is provided a testing apparatus that tests a device under test. The testing apparatus includes: a command executing unit operable to sequentially execute commands included in a test program for the device under test every command cycle; a test pattern memory operable to store pattern length identifying information identifying...

20060190795 - Systems and methods for performing quality assurance on interactive television and software application data delivered via a network: A system and method for providing quality assurance for interactive television and software application data packages delivered via a network. By employing “code checks” that determine “code points” based on the original package, content or data packages may be checked for errors at any later point within the network path...

20060190796 - Radio transmission device and radio transmission method: An RV pattern selection section (103) stores at least two RV parameter tables, for QPSK and 16QAM, selects a corresponding RV parameter Xrv from the RV parameter tables based on a correlation between an estimated transmission count input from a transmission count estimation section (101) and a coding rate input...

20060190801 - Apparatus and method for generating low density parity check code using zigzag code in a communication system: A method for generating a low-density parity check (LDPC) code supporting various code rates. The method includes finding a plurality of parity check matrixes showing the best performance at a predetermined code rate; matching the parity check matrixes in terms of the number of ‘1’s per row in units of...

20060190800 - Copy protected dvd disc and method for producing and validating same: A copy protected DVD disc and a method for producing a signature on the disc is provided. In an embodiment of the invention, the method for protecting a DVD disc includes producing a signature on the disc by non-destructively altering the content of at least one sector in the data...

20060190799 - Decoding apparatus and method and program: A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding...

20060190797 - Low complexity decoding of low density parity check codes: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a...

20060190798 - Verifier for remotely verifying integrity of memory and method thereof: A verifier for remotely checking integrity of a device connected via a network, includes a calculator which fills free areas in a memory of the device with random numbers and generates a local check code; an interface which transmits integrity check parameters that are used by the device to generate...

20060190802 - Method and device for building a variable length error-correcting code: The invention relates to a variable-length error-correcting (VLEC) code construction method, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1-tuples distant of the minimum diverging distance d ‘min! from...

20060190803 - System and method for error correction in high definition tv signal: An input signal such as a HDTV signal is split into a primary signal, which can be decoded if desired, and an secondary signal, which can remain compressed. The primary signal may be delayed and then both signals are transmitted to a receiver. If no error in the primary signal...

20060184819 - Cluster computer middleware, cluster computer simulator, cluster computer application, and application development supporting method: A “session” is used to describe states of cluster computer middleware. The “session” is a sequence of coherent processes and satisfies the following two conditions. (a) A notification is issued to an application each time the session starts or terminates. (b) Two sessions maintain any of anteroposterior relation, inclusion relation,...

20060184818 - Product information providing apparatus and method: A product information providing apparatus for providing, via a network, product information for supporting operations of a product, comprises an electronic product information storage that stores electronic product information which contains a group of hicrarchized files having a file format browsable through a Web browser; a table holder that holds...

20060184820 - Storage system: The failure management sections of a host computer and a storage unit are connected through a failure reporting interface. When a failure occurs in the storage unit, the failure information is notified from the failure management section of the storage unit to the failure management section of the host computer...

20060184821 - System and method for enabling a storage system to support multiple volume formats simultaneously: A system and method enables a storage system to support multiple volume type simultaneously. A volume type field is contained within a file system information block that permits the storage system to determine the type of volume of a particular volume associated therewith. The storage operating system may then interpret...

20060184822 - Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor: A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to...

20060184823 - Access control device and interface installed in same: The access control device comprises a first interface (IF) which receives access requests from a host device, and a second IF which respectively accesses one or a plurality of access destination candidates in an external device. The second IF attempts to access a particular access destination candidate if the first...

20060184824 - System and method for effectively implementing an immunity mode in an electronic device: A system and method for effectively implementing an immunity mode in an electronic device includes a processor module for executing processing tasks for the electronic device. The processor module includes processor information, such as processor states and processor data, for executing the processing tasks. The electronic device also includes a...

20060184825 - Reliability centered maintenance system and method: A reliability centered maintenance system having an input device and logic that receives and stores data indicative of a function, a functional failure, a failure mode, and a failure effect, via the input device, displays the received data to a display device in response to a first user input, and...

20060184826 - Using a description language to build a management system: Functionality and corresponding procedures are described for building a management system. The management system provides description language content (such as markup language content) which describes different aspects of the management system in a declarative manner. The management system also includes generic resource content for performing various general purpose tasks that...

20060184827 - Method for responding to a control module failure: A method is provided for saving system information immediately following a hardware or software failure that causes a processor to reset. After failure is imminent and before the processor allows the reset to occur, the processor is instructed to copy a fixed amount of the system stack SRAM, in addition...

20060184828 - Transient shared computer resource and settings change bubble for computer programs: Described is a mechanism that preserves the state of computer system shared resources and/or settings, and ensures that changes thereto are reverted when an application exits. A shared resource change bubble logically surrounds application code that causes system resource and/or setting data to change. The bubble preserves existing data before...

20060184829 - Web-based analysis of defective computer programs: A method and system for web-based analysis of defective computer programs is disclosed. One aspect of the invention involves a method at a third-party computer remote from a customer computer with a defective program and remote from a set of computers associated with a support provider for the defective program....

20060184830 - Disk device and disk processing method: A disk device has a reading portion that reads out from a disk having a rewritable area, a plurality of defect management areas and a plurality of position information areas indicating an optimum position used for reproduction in the plurality of the defect management areas, a recording portion that records...

20060184831 - Passing debug information: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but...

20060184832 - Method and apparatus for achieving high cycle/trace compression depth by adding width: A trace array with added width is provided. Each trace array entry includes a data portion and a side counter portion. When a programmable subset of trace data repeats, a side counter is incremented. When the programmable subset of the trace data stops repeating, the trace data and the side...

20060184835 - Method, apparatus, and computer program product for synchronizing triggering of multiple hardware trace facilities using an existing system bus: A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a...

20060184837 - Method, apparatus, and computer program product in a processor for balancing hardware trace collection among different hardware trace facilities: A method, apparatus, and computer program product are disclosed in a data processing system for balancing hardware trace collection between hardware trace facilities. A first hardware trace facility is included within a first processor. The first processor includes multiple processing units coupled together utilizing a first system bus. A second...

20060184834 - Method, apparatus, and computer program product in a processor for concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers: A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility...

20060184836 - Method, apparatus, and computer program product in a processor for dynamically during runtime allocating memory for in-memory hardware tracing: A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a...

20060184833 - Method, apparatus, and computer program product in a processor for performing in-memory tracing using existing communication paths: A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is...

20060184838 - Parallel software testing based on a normalized configuration: A method and a system perform parallel software testing based on a normalized configuration. In some embodiments, a system includes a first hardware system having one or more hardware components to execute a first version of software. The system also includes a second hardware system having one or more hardware...

20060184839 - Erasure determination procedure for fec decoding: A method and a decoder for determining erasures in an FEC (Forward Error Correction) decoding process decoding data encoded with concatenated codes is provided. First output data are generated by decoding first input data Second output data are generated by decoding second input data, the second input data including at...

20060184840 - Using timebase register for system checkstop in clock running environment in a distributed nodal environment: A mechanism is provided for determining a cause of a primary error in a complex communications topology without clockstop. A time of day register, or another synchronized register, is provided in each node of the topology for another existing purpose. When an error is encountered, a copy of the register...

20060184841 - Integrated apparatus for multi-standard optical storage media: An integrated apparatus for multi-standard optical media includes a compact disc/digital versatile disc (CD/DVD) processor, a high-definition DVD (HDDVD) processor and a Blu-ray disc (BD) processor; a memory unit connected to the CD/DVD processor, the HDDVD processor and the BD processor to provide a storage resource; and a shared error...

20060184842 - Methods and systems for software watchdog support: Methods and systems consistent with the present invention allow a program designer to conveniently specify and support watchdog checking of a program under development. The resulting programs are more robust than programs developed without watchdog support. The method and systems provide a convenient, automated mechanism for adding watchdog support to...

20060184843 - Data recording using carbon nanotube electron sources: A method and apparatus for data recording using carbon nanotube electron sources is described. The present invention relates to using a Carbon Nanotube as a source for an electron beam suitable for real-time writing of data to a storage medium. Carbon nanotube electron emitters are used as electron sources for...

20060184845 - Data encoding apparatus, data decoding apparatus and data encoding/decoding system: A data encoding apparatus extracts valid data to be encoded from received data and encodes the data, and realigns the encoded data in units of a predetermined data width and outputs the data having each unit of the predetermined data width. A data decoding apparatus extracts valid data to be...

20060184844 - Synchronous data transfer circuit, computer system and memory system: A circuit synchronizes parallel data of different timing for transfer. The synchronous data transfer circuit includes a plurality of first flip-flop circuits in which the parallel data are set by a data strobe signal, a plurality of delay circuits, and a plurality of second flip-flop circuits. By configuring the second...

20060184846 - System and method for managing mirrored memory transactions and error recovery: In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling...

20060184847 - Semiconductor device tested using minimum pins and methods of testing the same: The present invention provides semiconductor devices capable of being tested using one test pin and using an input/output pin without any test pins, and methods of testing the same. One semiconductor device comprises a test pin for inputting/outputting test data, an operation mode controller for activating an enable signal in...

20060184848 - Semiconductor integrated circuit having test function and manufacturing method: The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching...

20060184849 - Test pattern generator and test pattern generation method for onboard memory devices: A test pattern generator generating a test pattern for performance testing of an onboard memory is provided for a device having a memory macro, a serial input interface, and a latch circuit latching the serial input signal and outputting the result to the memory macro in parallel format. This test...

20060184850 - Apparatus for preventing bus reset when removing a device from an ieee 1394 network: Disclosed is an apparatus for preventing bus reset when a node is removed in an Institute of Electrical and Electronics Engineers (IEEE) 1394 network. The apparatus includes a tone signal generator for generating a tone signal substantially identical to a tone signal generated by a second node and transferring the...

20060184851 - Embedding a upnp av mediaserver object id in a uri: A UPnP-compliant MediaRenderer-Control Point combination is enabled to exploit an organizational context of a content item as represented in a UPnP Content Directory Service. To this end, the combination is enabled to receive a URI representative of a Content Directory Service description, together with an objectID representative of the content...

20060184852 - Transient noise detection scheme and apparatus: A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture...

20060184854 - Allocating data bursts and supporting hybrid auto retransmission request in orthogonal frequency division multiplexing access radio access system: The present invention relates to allocating data regions in an orthogonal frequency division multiplexing access system. The present invention comprises receiving a message comprising information for locating a data region of a data map allocated to a mobile station identified in the message for transmitting and receiving information, and identifying...

20060184853 - Operating method for a motorized roller blind: The method describes the operation of a roller blind including a moving element that can be operated via an actuator and a handheld-type remote control used to set the value of an operating parameter of the system, the value of this parameter being modifiable between two limit values. In this...

20060184855 - Turbo decoder architecture for use in software-defined radio systems: A reconfigurable turbo decoder comprising N processing units. Each of the N processing units receives soft input data samples and decodes the received soft input data samples. The N processing units operate independently such that a first processing unit may be selected to decode the received soft input data samples...

20060184857 - Data recording method, recording medium and reproduction apparatus: A recording medium is provided for storing a data stream containing first error correcting codes obtained by encoding first information, second error correcting codes obtained by encoding second information, and synchronization signals. The first error correcting codes have a first correction capability, and the second error correcting codes have a...

20060184856 - Memory circuit: A memory circuit includes a data storage section for storing a plurality of data sets and a plurality of redundant data sets, which are used for error correction for the data sets; and an error correction section for performing at least error detection for the data sets in the data...

20060184858 - Memory circuit, such as a dram, comprising an error correcting mechanism: A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address...

20060184859 - Predictive diagnosis of a data read system: A data read system comprising a read channel for processing a signal, and a diagnostic controller in communication with the read channel. The diagnostic controller is configured to measure at least one metric of the read channel during processing of a signal containing unknown data. The measured metric is then...

20060184860 - Data repeating device and data communications system with adaptive error correction: A data repeating device that can maintain the data integrity in error-prone circumstances, without sacrificing the efficiency of data transmission in normal conditions. A network system involves a data communications device and a data repeating device interconnected via a transmission line. The data repeating device has an error detector for...

20060184861 - Method and system for lost packet concealment in high quality audio streaming applications: The present invention provides an audio streaming system and method for transmitting audio signals with high quality. The advantages of the present invention include easy implementation, computational efficiency, and provision of better audio quality. More particularly, the present invention provides a Multi-band Time Expansion algorithm for lost packet concealment. The...

20060184863 - Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one...

20060184862 - Orthogonal frequency division multiplexing/modulation communication system for improving ability of data transmission and method thereof: An orthogonal frequency division multiplexing (OFDM) communication system and method for improving frequency utilization efficiency. In the system, a Reed-Solomon encoder codes input information data, and outputs a Reed-Solomon block comprised of a second number of Reed-Solomon symbols each comprised of a first number of Reed-Solomon symbol elements. An interleaver...

20060184864 - Error detection: A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but...

20060174154 - Method and system for communicating predicted network behavior between interconnected networks: A method of communicating predicted network behavior includes generating network topology structure data describing at least part of a topology of a first network. Demand structure data is generated, the demand structure data describing at least some traffic demands relating to a source in the first network and a destination...

20060174155 - System, method and computer program product for testing software: A system, method and computer program product are provided for testing software to be run on a data processing apparatus having a processor for performing data processing operations, a memory for storing data for access by the processor, and at least one temporary storage located between the processor and the...

20060174156 - Cache redundancy for lsi raid controllers: Disclosed is a 2-level cache system for a Redundant Array of Independent Disks (RAID) device used as part of a Storage Area Network (SAN) system. The RAID controller of the RAID device contains a level 1 cache contained in the RAID controller RAM, and a level 2 cache is created...

20060174157 - Dynamically expandable and contractible fault-tolerant storage system with virtual hot spare: A dynamically expandable and contractible fault-tolerant storage system employs a virtual hot spare that is created from unused storage capacity across a plurality of storage devices. This unused storage capacity is available if and when a storage device fails for storage of data recovered from the remaining storage device(s). On...

20060174158 - Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domains: An integrated circuit chip includes multiple functional components and a central interconnect (CI) module. Each functional component communicates with the CI module via a respective internal bus sharing a common architecture which does not dictate any particular data alignment. The chip architecture defines an alignment mechanism within the CI module,...

20060174159 - Fail-over support for legacy voice mail systems in new world ip pbxs: An Integrated Communication System (ICS) with fail-over serial data connectivity is disclosed. In one aspect, an ICS may comprise a chassis including a System Switch Processor (SSP) for providing connectivity to a plurality of slots. A Serial Alarm Processor (SAP) may be operatively coupled to the ICS through one of...

20060174160 - Method for transmitting and downloading streaming data: A method for transmitting and downloading streaming data is disclosed. The method comprises (a) establishing connections with a plurality of nodes; (b) sending a request for sub blocks of streaming data to the plurality of nodes where connection is established to download the sub blocks; (c) monitoring download state of...

20060174163 - Software breakpoints for use with memory devices: System and method for providing software breakpoints for use with memory devices. One aspect of the invention includes a microprocessor, a memory device accessible through a data bus and an address bus coupled to the microprocessor, and processing logic coupled to the memory device and to the microprocessor. The processing...

20060174162 - System and method for self-testing of mobile wireless devices: The use of mobile wireless devices is on the increase. Mobile manufactures design, develop, and release new devices to the market at regular intervals. In order to keep the market leadership, such companies need to have techniques, processes, and tools to quickly design and test their products. One of the...

20060174161 - Viewer for test apparatus hardware: A common viewer framework simplifies the viewer development process and significantly reduces the development time and cost of viewer development. Based on this framework, viewers for different hardware devices are developed according to a common application programming interface (API) and operate as plug-ins to a common viewer tool. Also, the...

20060174164 - Methods, systems, and computer program products for implementing condition monitoring activities: Methods, systems, and computer program products are provided for implementing condition monitoring activities. Systems include a processor in communication with a machine being monitored. The processor receives signals output by the machine via a signal conversion element associated with the machine. Systems also include a display device in communication with...

20060174165 - System and method for tracing and logging for software module: A method and system for tracing and logging for a software module is provided. The method includes the steps of detecting at least one error and analyzing at least one error message corresponding to each detected error. The method further includes the step of monitoring the resources of a computer...

20060174166 - Proactive driver response to an operating system if a drive is removed from a raid configuration: A method for responding to a particular drive being removed from a drive array, comprising the steps of (A) determining a maximum drive response time of the particular drive being removed from the drive array; (B) determining a duration of each of one or more commands needing completion; (C) if...

20060174167 - Self-creating maintenance database: A maintenance database is described. Maintenance entries are maintained in the maintenance database relating to repair actions for failure modes in a target system. The failed components of the target system are identified for each failure mode, and repair actions are recorded along with the sequence of repair actions for...

20060174168 - Parallel data storage device: A parallel data storage device includes a data storage medium having a first cluster and a second cluster. The first cluster includes a first patch and the second cluster includes a second patch. The parallel data storage device also includes a first reader for reading the first patch of the...

20060174169 - Io direct memory access system and method: Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may...

20060174170 - Integrated reporting of data: Application-specific terminology for a test data element produced by a test management tool is converted into a standard terminology. A mapping strategy is used to map the application-specific terminology to the standard terminology. A report showing the test data element expressed in the standard terminology is delivered....

20060174171 - Method and apparatus for reducing transmission errors caused by periodic transients in digital subscriber line (dsl) communication systems: A transient pre-emptor includes a processor configured to detect transients in a communications system. After the processor detects a transient in the communications system, it causes a data communications equipment to suspend or reduce data transmission during the occurrence of a subsequent transient....

20060174172 - Toggle memory burst: A controller for a toggle memory that performs burst writes by reading a group of bits in the toggle memory and comparing each received data word of the burst with a portion of the group to determine which cells to toggle to enter the data of the burst write in...

20060174173 - Built-in test circuit for an integrated circuit device: An integrated circuit device can be tested using a built-in test circuit, in the IC device, that tests the operation of an I/O cell. The built-in test circuit includes a pattern generator for generating a series of simulation signals. The built-in test circuit successively stores and retrieves the simulation signals...

20060174174 - Method, system, and storage medium for estimating and improving test case generation: A technique for estimating and improving the test coverage for large machines, while accumulating minimum information of past test cases (i.e., minimum feedback) is provided. The technique is scalable in the sense that the number of machine instructions needed to measure the test coverage can range from a few instructions...

20060174175 - Array self repair using built-in self test techniques: A soft-fuse test algorithm is distributed on-chip from an ABIST engine through an LSSD shift register chain to dynamically evaluate a plurality of arrays with redundancy compensation for bad elements and repair those that are fixable. Each arrays outputs are monitored by a different multiple input signature register (MISR) with...

20060174176 - Semiconductor integrated circuit and method for testing the same: In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power...

20060174177 - Apparatus and method for using mems filters to test electronic circuits: A mixed-signal integrated circuit testing device includes test electronics for generating a test signal for input to a device under test and receiving a response signal from the device under test, and an interface connected between the test electronics and the device under test. The interface includes at least one...

20060174178 - Programmable scan shift speed control for lbist: Systems and methods for performing logic built-in-self-tests (LBISTs) in digital circuits, where scan shift operations of the LBIST circuitry are performed at reduced rates. In one embodiment, a base clock signal is gated before being provided to LBIST circuitry. The clock signal is gated to produce an effective clock rate...

20060174179 - Erasure detection for a transport channel with an unknown format: To perform erasure detection for an intermittently active transport channel with unknown format, a receiver determines an energy metric and a symbol error rate (SER) for a received block with CRC failure. The receiver computes uncorrelated random variables u and v for the received block based on the energy metric...

20060174180 - Meta-viterbi algorithm for use in communication systems: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel characterized by intersymbol interference. Each of the one or more codewords incorporates one or encodes one or more parity bits. The codewords...

20060174181 - Identifying uncorrectable codewords in a reed-solomon decoder for errors and erasures: Nerrors and nerasures represent, respectively, a number of errors and erasures, with respect to an error locator polynomial σ(x) and an erasure locator polynomial Λ(x), 2T is the strength of a Reed-Solomon code, ω(x) is an errata evaluator polynomial, and T(x) is a modified syndrome polynomial. A detector circuit 300...

20060174182 - Trial-and-error multi-bit error correction: An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting parameters. The data word is associated with...

20060174183 - Method and apparatus for soft-output viterbi detection using a multiple-step trellis: Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the...

20060174184 - Method and apparatus for encoding and decoding data using a pseudo-random interleaver: A pseudo-random bit interleaver and de-interleaver comprising a source for generating pseudo-random numbers and transformation logic that transforms each pseudo-random number generated by the source into a plurality of different pseudo-random numbers. Each of the transformed pseudo-random numbers identifying a parity equation to which an incoming bit will be assigned...

20060174185 - Method and apparatus for encoding and precoding digital data within modulation code constraints: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of...