Error detection/correction and fault detection/recovery inventions 07/06

20060168467 - Load testing methods and systems with transaction variability and consistency: Disclosed are load testing methods and systems with transaction variability and consistency....

20060168469 - Method and system for correcting program for use in composite video apparatus: A method and system for correcting a program for use in a composite video apparatus can correct a program when an error occurs in a microprocessor including a masked Read Only Memory (ROM). The method and system correct a program of a video apparatus in which a plurality of devices...

20060168468 - Method for recovering control of a continually resetting control module: A method for recovering control of a continually resetting control module is provided. The method recovers control by monitoring a vehicle's communication links for a very short period each time the boot program starts and before control is passed to the application program. Alternatively, control may also be recovered using...

20060168470 - Random access memory with post-amble data strobe signal noise rejection: A random access memory includes a control circuit configured to receive a strobe signal and generate a pulse after one edge of the strobe signal and before the next edge of the strobe signal for each cycle of a clock signal and a latch circuit configured to receive the strobe...

20060168471 - Automatically triggered snapshot data dump for storage unit with embedded system: In a system and method for failure analysis of a hardware system having an embedded specialized application computer as a firmware stored in a firmware memory and which controls and is part of the hardware system, with a snapshot dump system associated with the hardware system, detecting for an error....

20060168472 - Data storage unit failure condition responding method and system: A data storage unit failure condition responding method and system is proposed, which is designed for use in conjunction with an access control interface that is coupled between a computer system and a data storage unit for responding to an event of a failure condition in the data storage unit;...

20060168473 - Method and system for deciding when to checkpoint an application based on risk analysis: Briefly, according to the invention in an information processing system including a plurality of information processing nodes, a request for checkpointing by an application includes node health criteria (or parameters). The system has the authority to grant or deny the checkpointing request depending on the system health or availability. This...

20060168474 - Power failure detection and correction in a flash memory device: A transactional file system developed to function with flash memory is described. The file system performs power-failure detection and ensures data integrity in the event of a power failure. In one described implementation, a power failure event can be detected by a file system, components of the file system, or...

20060168475 - Automated performance analysis and failure remediation: A service diagnosis tool for performance analysis and failure remediation of electromechanical devices, e.g. printers or copiers. The tool communicates with an actual device of a specific type, and accesses data from a knowledge data set containing knowledge relating to properties of devices of the specific type, a device data...

20060168476 - System, apparatus, computer program product and method of performing functional validation testing: A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be...

20060168477 - Multilayered architecture for storage protocol conformance testing of storage devices: A storage protocol test server interfaced with a storage device and a client includes a multi-layered architecture for testing a conformance of the storage device to a storage protocol as dictated by the client. The layers operate to participate in a test case session between the server and the client...

20060168478 - Dynamic discovery algorithm: A method for monitoring exception events generated by a software application including operating the software application to generate exception event data responsive to an exception event, monitoring the software application to identify an occurrence of the exception event and to obtain the exception event data, examining the exception event data...

20060168480 - Method and apparatus for enforcing safety properties of computer programs by generating and solving constraints: A method and apparatus is disclosed herein for generating and solving constraints. In one embodiment, the method comprises modifying program code by inserting one or more dynamic annotations having unsolved variables, generating one or more constraints based on the one or more dynamic annotations using a verifier, solving the one...

20060168479 - Real time event logging and analysis in a software system: An apparatus and associated method is provided comprising a software system resident in a memory space configured to execute a service request which results in a plurality of events carried out by the software system to complete the service request, and creates a plurality of entries associated with the events,...

20060168481 - Trace information collecting system, method and program: Occurrence of a failure in a computer system is appropriately detected, and information required for removing the failure is automatically collected. A trace information collecting system of the present invention which collects trace information indicating the course of processing of a program comprises a history recording section for recording a...

20060168482 - Information recording medium, defect management method, information reading/writing device and information reading device: To specify defect management information to be used in a short time in an information recording medium having a defect information area capable of recording plural sets of defect management information and a selection information area capable of recording plural sets of selection information for selecting a set of defect...

20060168483 - On-chip circuitry for bus validation: Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise...

20060168484 - System and method for process degradation problematic tool identification: A method and system are provided for detecting suspect production tools, including testing produced products using a test sequence, said testing producing yield data, said yield data related to a production batch and a production process, said production process identified with a process tool. For each production process, a first...

20060168485 - Updating instruction fault status register: In a pipeline architecture, an instruction fault status register (FSR) is used to save the reason for a fault between the time an instruction is fetched and when it is executed. Sequential faults for different reasons cause an overwrite of the FSR and invalid abort codes upon the execution of...

20060168486 - Desktop computer blade fault identification system and method: A method and system for remotely isolating faults in computer network devices coupled to a computer network. A plurality of first computer units are coupled to the computer network. The plurality of first computer units are located on a user side of the computer network. A plurality of second computer...

20060168487 - System pulse latch and shadow pulse latch coupled to output joining circuit: In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal...

20060168488 - Method and system for testing ram redundant integrated circuits: System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die....

20060168489 - System and shadow circuits with output joining circuit: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal...

20060168490 - Apparatus and method of controlling test modes of a scannable latch in a test scan chain: Apparatus for controlling an operational test mode of a scannable latch in a test scan chain, the scannable latch comprising a scan latch and a functional latch coupled thereto, comprises: first circuit for gating a clock signal to the functional latch, the functional latch being responsive to the gated clock...

20060168491 - Automated tests for built-in self test: A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the...

20060168492 - Graceful load fail over: Systems and methodologies that facilitate real time recognition of missing and/or invalid objects in a component based framework, via employing a graceful load fail over engine that can self heal a component based application that has missing or invalid references, to be properly read, validated and executed on a user's...

20060168493 - Data detection and decoding system and method: A data detection and decoding system includes a SOVA channel detector that uses single parity (SOVASP) to improve the accuracy with which the detector estimates bits. Each column or row read back from the read channel constitutes a code word and each code word is encoded to satisfy single parity....

20060168495 - Computation of cyclic redundancy check: In one aspect, a method and apparatus for advancing a state of a cyclic redundancy check (CRC) computation on a transmitted message via a look-up table (LUT) storing a plurality of entries associated with possible states of the CRC computation is provided. A plurality of indexes is computed based on...

20060168494 - Error protecting groups of data words: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for use in protecting groups of data words. One embodiment manipulates these data words to generate a resultant data word and an error correction code thereon for use in identifying a position of a bit error, with error...

20060168496 - Systems and methods for implementing cyclic redundancy checks: The present invention provides systems and methods for implementing cyclic redundancy checks to improve link initialization processing and to exchange system error information. In one aspect, a cyclic redundancy check (CRC) checker is provided that includes a unique pattern detector, a CRC generator, a CRC initializer and a CRC verifier....

20060168497 - Multi-thread parallel segment scan simulation of chip element performance: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware...

20060168498 - Test apparatus and program for testing a dut: There is provided a test apparatus including a pattern generator that generates test patterns, a logic comparator that decides the good or bad of the electronic device, and a fail memory that stores decision results of the logic comparator every address of the electronic device, in which the pattern generator...

20060168499 - Data archive verify software: The invention is directed to verify software to determine the quality and accuracy of data recorded on an optical data storage disk by an optical disk drive. A verify software module receives error information from the optical disk drive indicative of errors associated with the recovered data. The verify software...

20060168500 - Iterative decoding with likelihood weighting: The invention relates to an error correcting decoder apparatus (100) and method. The decoder apparatus (100) comprises a likelihood estimator (101) which generates a sequence of bit value likelihood estimates, such as log likelihood ratios, for multi bit symbols of a data sequence. The decoder apparatus (100) further comprises a...

20060168501 - Viterbi decoder for executing trace-back work in parallel and decoding method: A Viterbi decoder for executing a trace-back work in parallel and a decoding method. The Viterbi decoder includes a branch metric calculator which calculates a branch metric from a branch code passing each state on a trellis diagram and a predetermined input code, at least one adder/comparator/selector which adds the...

20060168502 - Decoder with m-at-a-time traceback: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics,...

20060168503 - Systems and methods for mitigating latency associated with error detection and correction: Systems and methods for mitigating latency associated with error detection and correction of a data structure are disclosed. One embodiment of a system may comprise a packet generator that builds a response packet associated with a request for a data structure based on a tag portion of the data structure....

20060168504 - Method and devices for error tolerant data transmission, wherein retransmission of erroneous data is performed up to the point where the remaining number of errors is acceptable: A method and an apparatus for transmitting error-tolerant data is disclosed employing the ARQ technique, wherein the retransmission of erroneous data is performed up to the point where the remaining amount of errors is acceptable (for instance because the erorrs will not be perceived by the recipient of the information,...

20060168505 - Integrated memory device and method for operating the same: A memory device includes an array of memory cells that include a memory element having a non-reactive resistance whose magnitude is programmable to assume a high-resistance state or a low-resistance state. Sets of first and second lines provide access to the memory cells, wherein the memory element of each memory...

20060161802 - Backup/recovery system and methods regarding the same: A network backup/recovery system is provided which can furnish backup service and/or recovery service via a network, which can minimize time consumption and cost. The network backup/recovery system comprises a management unit for managing at least one client and a processing unit for providing the backup/restore service and transmitting the...

20060161801 - Secured web based access of failed flows in an integration server: A method for accessing failed events in an integrated server environment is disclosed. The method comprises providing a thin client in an application server within the environment, wherein the thin client provides role-based access to a failed event, and wherein the role-based access is based upon a user's ability to...

20060161800 - System and method for error reporting: A system and method are provided for reporting errors in an object-oriented software architecture environment. The method comprises: an application calling an initial method; in response to the initial method call, at least one object encountering an error in response to a subsequent method call; accumulating error information; and, creating...

20060161803 - Memory bisr architecture for a slice: The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the...

20060161804 - Memory bisr controller architecture: The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN...

20060161805 - Apparatus, system, and method for differential rebuilding of a reactivated offline raid member disk: An apparatus, system, and method are disclosed for rebuilding only changed stripes of an offline member disk in a RAID array that is configured with redundancy and no hot standby disk. A work-in-progress (“WIP”) map tracks the changed stripes of the offline member disk prior to a reactivation and records...

20060161809 - Disk connection unit, disk package, disk apparatus and disk connection method: There are provided a disk connection unit, a disk package, a disk apparatus and a disk connection method that can improve the speed of operation and the reliability of the RAID categories. A disk connection unit 31 to be used to utilize a plurality of disks 32 by means of...

20060161806 - Method and system of configuring a software program: Methods and systems are presented herein to correct a defective variable value entered into a system during configuration. In some embodiments, in response to a runtime error, a variable may be identified; help-text specific to the variable may be output; new data may be read and used to replace the...

20060161808 - Method, apparatus and program storage device for providing intelligent copying for faster virtual disk mirroring: A method, apparatus and program storage device for providing intelligent copying for faster virtual disk mirroring is disclosed. The present invention provides a mirrored virtual disk by copying on a first virtual disk to a mirrored virtual disk without copying uninitialized regions of the first virtual disk....

20060161810 - Remote replication: A remote replication system for reading data, without server involvement, from any industry standard Fibre Channel LUN and producing an exact copy on a specified virtual volume is provided. The remote replication system further produces remote mirrored copies of virtual volumes on another storage platform and remote mirrored copies of...

20060161807 - System and method for implementing self-describing raid configurations: A system and method is disclosed for the implementation of self-describing configurations in storage array. Each storage drive of the storage array includes at a defined location in the storage drive a self-describing function. When the storage controller receives a request to access a data block in the storage array,...

20060161811 - Method and system for use in restoring an active partition: The present embodiments perform active volume restores on actively running initial operating systems in an active partition. The methods identify available memory within a partition, duplicate at least a portion of an initial operating system image into the identified available memory providing a duplicate operating system, remap access from an...

20060161812 - Remote controller code format(s), transmitting/receiving apparatus thereof, and transmitting/receiving method(s) thereof: Remote controller code format(s), transmitting/receiving apparatus thereof, and transmitting/receiving method(s) thereof are provided by which data can be transmitted/received using an intrinsic remote controller code format to prevent reciprocal compatibility with another remote controller of a different manufacturer. The remote controller code format(s) may include a header code, a custom...

20060161813 - Computer system and method having isolatable storage for enhanced immunity to viral and malicious code infection: An apparatus and method of supporting the backup and recovery of a computing device. The computing device typically includes both a user computing environment and a supporting environment which enhances the stability and functionality of the user computing environment....

20060161814 - Method and system of data analysis using neural networks: A system and method of computer data analysis using neural networks. In one embodiment of the invention, the system and method includes generating a data representation using a data set, the data set including a plurality of attributes, wherein generating the data representation includes: modifying the data set using a...

20060161815 - Multiple test access port protocols sharing common signals: A method of causing an interface to implement a mode from a plurality of selectable modes in which the interface operates according to a plurality of states defined by a state machine comprises sequencing through a sequence of the states, and detecting a predetermined sequence of the states. The predetermined...

20060161816 - System and method for managing events: Systems and methods to manage logs from log sources distributed across one or more networks using a log event management system, herein called a Thunder console. The Thunder console is a log aggregator that allows networks to deploy servers which collect, normalize, and analyze a large number of log events....

20060161817 - Physical layer loop back method and apparatus: The network device includes a transceiver, a pattern generation unit and a pattern recognition unit. The transceiver connects to a communications medium. The pattern generation unit connects to the transceiver. The pattern generation unit is configured to generate a first code word in response to a self-test signal. The pattern...

20060161818 - On-chip hardware debug support units utilizing multiple asynchronous clocks: A system for interfacing a debugger, the debugger utilizing a test clock, with a system under debug, the system under debug utilizing one or more system clocks includes a test-clock unit, utilizing the test clock, connected in communication with the debugger, and one or more system-clock units, each of which...

20060161819 - History-based prioritizing of suspected components: A method for servicing a computerized system includes detecting a failure of a given type in the computerized system, and generating a list of corrective actions in response to the failure, using an automated maintenance program. A record of one or more previous failures of the given type in the...

20060161820 - Highly reliable distributed system: The highly reliable distributed system is composed of a communication protocol processing unit which comprises a mailbox for storing a communication message, and executes communication protocol processing between data of an application program and a network controller using the network controller performing network communication of the message in the mailbox;...

20060161821 - Increasing software fault tolerance by employing surprise-removal paths: The subject invention relates to systems and methods for automatic recovery from errors in a computing environment. A system is provided to facilitate failure recovery in the computing system. The system includes at least one driver component that enumerates at least one layer of a driver stack. A module associated...

20060161822 - Method and apparatus for compressing error information, and computer product: An error-information compressing apparatus acquires a hardware error from a hardware, stores reference data in a storing unit, compresses the hardware error by using the reference data into compressed hardware error, and writes the compressed hardware error in a storage device. The hardware error is compressed by calculating a difference...

20060161823 - Disk array system configuring a logical disk drive having a redundancy function: A disk array system includes a plurality of physical disks (10 to 25) configuring a logical disk (101 to 104) having a redundancy function, and a plurality of spare disks (50 to 53) for storing recovered data recovered from the physical disks (10 to 25) by the redundancy function upon...

20060161825 - Non-volatile memory device supporting high-parallelism test at wafer level: A non-volatile memory device includes a chip of semiconductor material. The chip includes a memory and control means for performing a programming operation, an erasing operation and a reading operation on the memory in response to corresponding external commands. The chip further includes testing means for performing at least one...

20060161824 - System and method of testing a plurality of memory blocks of an integrated circuit in parallel: A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width...

20060161826 - Method and system of modifying data in functional latches of a logic unit during scan chain testing thereof: A method of modifying data of functional latches of a logic unit during scan chain testing thereof to verify a test case failure of a suspected cell comprises: (a) determining a test case failure in the logic unit through scan chain testing thereof; (b) suspending clocked operations of the logic...

20060161827 - Over-voltage test for automatic test equipment: Automatic test equipment including a digital test instrument that may test for and respond to over-voltage conditions. Information on over-voltage conditions may be used in detecting or diagnosing fault conditions within a system under test. Over-voltage conditions may be monitored as part of a test to determine the time and...

20060161828 - Digital logic test method to systematically approach functional coverage completely and related apparatus and system: A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially...

20060161829 - Test apparatus and test method: A test apparatus includes: an instruction execution unit for sequentially executing instructions in a test program for a DUT in each instruction cycle; a default pattern memory for storing default pattern sequence to be associated with default pattern identification information for identifying that default pattern sequence, the default pattern sequence...

20060161830 - Combined-replica group-shuffled iterative decoding for error-correcting codes: A method generates a combined-replica group-shuffled iterative decoder, comprising. First. an error-correcting code and an iterative decoder for an error-correcting code is received by the method. Multiple group-shuffled sub-decoders for the error-correcting code are constructed, based on the iterative decoder. Then, the multiple group-shuffled sub-decoders are combined into a combined-replica...

20060161831 - Lowering voltage for cache memory operation: Setting a minimum operating voltage (Vcc min) of the cache to a voltage value at which the number of cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining cells continue to function correctly at the...

20060161832 - System and method for generating a cyclic redundancy check: A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3rd to Nth order CRC polynomial key word, wherein N is an integer...

20060161833 - Software testing: A system and method for generating executable units suitable for unit testing of a module for integration errors, the method comprising; recording, for a module, an interface specification that specifies pre-condition constraints on input values of methods of the module and post-condition constraints on output values of the methods of...

20060161834 - Error correction decoder: An error correction decoder possessing a decoding method with high error correction performance and capable of operating at a low operating frequency and on a reduced circuit scale. A decoding method based on the SOVA method for improving error correction performance and boosting reliability of the soft decision output by...

20060156051 - Module for reading a data carrier: A module for reading a data carrier, with a processor arrangement and a memory arrangement, • wherein the module is designed for incorporation in a data processing device, • wherein the data carrier comprises data sequences and information on the data sequences, and the data sequences are stored in a...

20060156052 - Method and apparatus for management of data on handheld devices: A method and apparatus for a backup and restore service is provided. The backup and restore functionality provides the ability to use fleet-based provisioning, as well as the ability to delete personal data from a lost handset. Since restoration is also possible using this system, if the handset is recovered—or...

20060156053 - A ground-based software tool for controlling redundancy management switching operations: Systems, methods, and computer program products for easily altering redundancy management data values associated with redundancy management logic that is executed by redundant data processing systems. The redundancy management data values are altered on a computer device remote from the system that includes the redundant data processing systems....

20060156054 - Milarrs systems and methods: An add-on module provides extrinsic management functionality to legacy and other devices. Contemplated modules include: (a) a state agent that provides at least one of the MILARRS function, and (b) a product agent that communicates with the device using at least one serial interface. Implementations are contemplated for both legacy...

20060156055 - Storage network that includes an arbiter for managing access to storage resources: A cluster network is disclosed that includes a set of nodes coupled to a storage enclosure. The storage enclosure includes an arbiter for managing contention for ownership of the storage drives of the storage enclosure. The arbiter receives ownership commands and arbitrates the ownership of the storage drives on the...

20060156058 - Data management apparatus, data management method and data management program: There is disclosed a technique that can reliably erase data to achieve an enhanced level of security, while suppressing the problem of low operability and that of poor response of some other process due to an increased load. A data management apparatus for managing the data of a file system...

20060156057 - Method and system for preserving crash dump in a diskless system: The invention discloses a method for preserving crash dump data in case of operating system crash in a diskless device. The method and the system according to the invention uses two stage booting where in a primary and a secondary kernel are loaded. The primary kernel is a compact kernel...

20060156056 - Write once recording medium and recording device and recording method for write once recording medium: A spare area 12 is divided into partial spare areas 12A to 12D, and a defect list 15 is divided into partial defect lists 15A to 15D, with the partial spare areas 12A to 12D corresponding to the partial defect lists 15A to 15D, respectively. When a defect is detected,...

20060156061 - Fault-tolerant computer and method of controlling same: A fault-tolerant computer has duplex systems each comprising a CPU subsystem for controlling access to a CPU and a storage unit, and an IO subsystem for controlling data which are input to the IO subsystem from an external circuit and output from the IO subsystem to the external circuit. Data...

20060156059 - Method and apparatus for reconstructing data in object-based storage arrays: A method and apparatus for placing objects on a storage device of a storage system and reconstructing data of objects in the storage device. The storage system stores data as objects and implements a RAID architecture including a plurality of the storage devices, and a disk controller for processing Object-based...

20060156060 - Method, apparatus, and computer program product for using an array of high performance storage drives included in a storage array to reduce accessing of an array of lower performance storage drives included in the storage array: A method, apparatus, and computer program product are disclosed for controlling accesses of drives in a storage subsystem. A first array of a first type of drive is provided. The first type of drive is a server class of drive. A second array of a second type of drive is...

20060156062 - Method for effecting the controlled shutdown of data processing units: Methods are provided for effecting functional control of program flow and/or data flow in digital signal processors and in processors which have closed and separated modules for effecting the program and data flow control or which operate in parallel arithmetic-logic units. The methods enhance the functionality of the signal processor...

20060156063 - Instant messaging transaction integration: A system and method are provided that allow an instant messaging (IM) user device to conduct transactions with transaction systems that do not natively allow IM inputs or message processing, wherein an intermediate functionality translates or transforms IM messages from the user device into non-IM communications that can be processed...

20060156064 - System and method for maintaining checkpoints of a keyed data structure using a sequential log: A system and method for maintaining checkpoints of a keyed data structure using a sequential log are provided. The system and method are built upon the idea of writing all updates to a keyed data structure in a physically sequential location. The system and method make use of a two-stage...

20060156065 - Correlation technique for determining relative times of arrival/departure of core input/output packets within a multiple link-based computing system: A method is described that comprises receiving a timing exposure packet having timestamp information. The timestamp information identifies a cycle of a clock signal at which the packet was made available for transfer from a core to a physical layer within a component of a link-based computing system. The packet...

20060156069 - Bdx data in stable states: A method implemented in a test system comprises a test debug system and a target system, said target system comprising a test access port that functions according to a plurality of states and also comprising an adapter. The method comprises the adapter transferring data to the test debug system while...

20060156068 - Conveying state data through state transitions and number of stays in states: A method comprises performing at least one zero-bit scan across an interface link. The at least one zero-bit scan defines a command window. The method further comprises an interface adapter counting a number of inert scans in the command window, and the number of inert scans defines a particular command...

20060156070 - Locating and labeling device in a multi drop configuration: An identification (ID) process comprises in each of a plurality of bit times, a debug test system asserting a control signal at a predefined state to a plurality of target systems, and each target system, having a bit pattern and the bit patterns being different among the target systems, outputting...

20060156066 - Preventing distrubtion of modified or corrupted files: An administrator node (130) adjusts a trustworthy-measure associated with nodes (110) that are suspected of unauthorized modifications of content material. The original provider of the content material to a network binds an identifying code to it. Upon receiving the material from a source node (110), a target node (120) computes...

20060156067 - Using zero bit scan as a control event: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans....

20060156071 - Approach for resolving printer driver incompatibility problems: A manner of resolving printer driver incompatibility problems is described. Print data is received from a printer driver. The print data reflects an incompatibility between the application program used to create the print data and the printer driver. Next, updated print data is generated that corrects the incompatibility between an...

20060156072 - System and method for monitoring a computer apparatus: A method and system for monitoring a computer application, including selecting the computer application, inputting condition information, monitoring the computer application and generating an alert when a condition of the selected computer application satisfies the condition information. The monitoring step may be accomplished by inserting dynamic watchers into 1 byte...

20060156073 - Method for monitoring the functions and increasing the operational reliability of a safety-relevant control system: A method for monitoring the functions and increasing the operational reliability of a complex safety-relevant control system, e.g. a motor vehicle control system, such as a brake system (ABS, TCS, ESP, EHB, EMB), a steering aid (‘steering-by-wire’), etc., and for detecting and evaluating system errors comprises the steps of: detecting...

20060156074 - Method and apparatus for utilizing an exception handler to avoid hanging up a cpu when a peripheral device does not respond: A method and apparatus utilizes an exception handler to implement LOAD and STORE instructions for moving data between a peripheral device and CPU registers. TLB entries for peripheral devices are flagged invalid during initialization and an exception handler occurs when LOAD or STORE instructions are executed by the CPU. The...

20060156075 - Semiconductor integrated circuit: Error recovery processing is performed to minimize the influence of malfunction when an error is detected. When an error occurs in a normal program execution state, control branches to a predetermined error handling routine shown by exceptional handling vectors or the like. While executing the instruction that writes zero to...

20060156076 - Radar system for motor vehicles: A radar system for motor vehicles, having an antenna, a first processor which is developed to transform signals supplied by the antenna via a primary signal path into a spectrum, and a second processor for the additional evaluation of the spectrum, wherein at least a part of the signals received...

20060156077 - System and method for updating end user error reports using programmer defect logs: A system and method for correlating end user error reports with software developer defect logs to thereby update the end user error reports with information from the developer defect logs. With the system and method, when support personnel open an end user error report to address the problem encountered by...

20060156078 - Method for restoring administrative data records of a memory that can be erased in blocks: The invention relates to a method for restoring administrative data records of a non-volatile memory that can be written in segments and erased in blocks, said records being stored in a more rapidly accessible internal volatile flag memory of an assigned memory controller. According to the invention, a reconstruction table...

20060156079 - Shift register system, driving method, and driving circuit for a liquid crystal display: An exemplary shift register system (31) includes a counter (316), a shift register (311) and a plurality of switches (312, 313, 314, 315). The counter includes a signal receiving pin which is for connection to a first external circuit, a pulse output pin, and a number of signal output pins....

20060156080 - Method for the thermal testing of a thermal path to an integrated circuit: According to one embodiment of the present invention, a method for detecting a defect in an integrated circuit using an optimized power pulse includes applying a first pulse of power to a first integrated circuit for an optimized pulse duration. The optimized pulse duration is determined as a function of...

20060156083 - Method of compensating for a byte skew of pci express and pci express physical layer receiver for the same: A method of compensating for a byte skew of a PCI Express bus, the method including determining whether received data are in a training sequence or not, setting an alignment point corresponding to each of the lanes based on a comma symbol included in the training sequence when the received...

20060156084 - Multiphase clock generation: A first-phase clock signal is generated in response to a first input clock signal. A second-phase clock signal is generated one clock cycle of the first input clock signal after generating the first-phase clock signal in response to the first input clock signal. A third-phase clock signal is generated one...

20060156081 - Semiconductor component test procedure, as well as a data buffer component: A data buffer component and a semiconductor component test procedure for testing a memory module are provided. At least one memory component with a series-connected buffer is included. The procedure includes testing the memory module by using a pulse signal, which has been chronologically retarded or advanced by a predetermined...

20060156082 - Signal dividing circuit and semiconductor device: To provide a constitution capable of reducing production cost in a semiconductor device for display of a type integrally formed with a drive circuit with a digital signal as an input signal and a pixel matrix unit, a signal dividing circuit is formed on a substrate where drive circuits and...

20060156085 - Method and tester for determining the error rate of a mobile radio device with variable block allocation: A method and tester for determining the error rate of a mobile radio device with variable block allocation is provided. Transmission blocks are sent to a mobile radio device to be tested. The mobile radio device to be tested receives and evaluates the transmission blocks and transmits a first and...

20060156086 - System and method for integrating multiple data sources into service-centric computer networking services diagnostic conclusions: A system for diagnosing impairments in computer networking services a plurality of connector gateways for interfacing to a plurality of data sources to provide access by the system to computer network data, business-related data, and extra-enterprise environmental data in the plurality of data sources. The system includes a knowledge manager...

20060156087 - Bit distributor for multicarrier communication systems employing adaptive bit loading for multiple spatial streams and methods: In a multicarrier transmitter that transmits two or more spatial data streams, a bit distributor assigns encoded bits to the spatial data streams based on bit-loading capabilities of the streams and in a manner to intermix the bits among the spatial streams....

20060156090 - Memory array manufacturing defect detection system and method: The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and...

20060156092 - Memory technology test apparatus: A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data...

20060156089 - Method and apparatus utilizing defect memories: A method and apparatus utilizing defect memories is based on damaged section blocks corresponding high bit address division types. A switch set is used to reset an electrical connecting mode between high bit address input end and high bit address output end of the control chip such that high bit...

20060156088 - Method and bist architecture for fast memory testing in platform-based integrated circuit: The present invention provides a method and BIST architecture for fast memory testing in a platform-based integrated circuit. The method may include steps as follows. An Mem-BIST controller transmitter is started to generate input signals for a memory in a platform using a deterministic and unconditional test algorithm. The input...

20060156091 - Methods and apparatus for testing a memory: In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit...

20060156093 - Synchronous memory interface with test code input: A synchronous non-volatile memory device has address input connections and data input/output connections. A test operation can be initiated that use signals provided on the address input connections and not the data input/output connections. The test mode can be entered using either commands or a combination of commands and an...

20060156095 - Fault detecting method and layout method for semiconductor integrated circuit: The present invention provides a fault detecting method and a layout method for a semiconductor integrated circuit. The fault detecting method performs detection for faults in a semiconductor integrated circuit using a fault list corresponding to information on sites in the semiconductor integrated circuit where a fault is likely to...

20060156094 - Interleaving/de-interleaving using compressed bit-mapping sequences: A method of mapping input bit positions in an input sequence to output bit positions in an output sequence uses compressed mapping sequences stored in memory derived from a predetermined mapping function. The mapping function is decompressed into periodic component functions that are used to generate the compressed mapping sequences....

20060156097 - Analog counter using memory cell: A non-volatile memory may include at least one cell that functions as an analog counter. In one embodiment, the counter may count the number of cycles experienced by the memory and provide an indication when a predetermined number of cycles have been completed. The completion of the given number of...

20060156103 - Apparatus and method for bit pattern learning and computer product: A computer calculates bit patterns of syndromes for all candidate bit patterns of reception words that are input in ECC-EOR circuits of a logic circuit. The bit patterns of the syndromes are stored as possible bit patterns. Request bit patterns are propagated when an error occurs, and are allocated to...

20060156105 - Data receiving apparatus capable of compensating for reduced timing margin caused by inter-symbol interference and method thereof: Provided are a data receiving apparatus that can determine data by adjusting a reference level for determining a logic value of inputted data based on Inter-Symbol Interference in a data signal inputted through a transmission line, and receive the data without errors by compensating for timing margin decrease caused by...

20060156115 - Device, system, and method for providing error information in xht network: A device, a system, and a method for displaying error information within an expandable Home Theater (XHT) network, and more particularly, to a device, a system, and a method for providing error information within the XHT network by displaying error information of slave devices in the XHT network to a...

20060156098 - Method and apparatus for testing an electronic device: An apparatus for testing an electronic device is provided. More specifically, there is provided a method comprising placing a first integrated circuit into a test mode, wherein the first integrated circuit is coupled to a conductive interconnect, causing a register assembly located on the first integrated circuit to transmit a...

20060156101 - Method and system for testing distributed logic circuitry: A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing procedure utilizes enabling one of a plurality of independent programmable...

20060156099 - Method and system of using a single ejtag interface for multiple tap controllers: Aspects of a method and system of using a single EJTAG interface for multiple TAP controllers may comprise communicating information to a plurality of debugging interfaces, the method comprising simultaneously broadcasting a single debug message to a plurality of TAP controllers where the debug message is received via a single...

20060156107 - Method for testing semiconductor chips by means of bit masks: A method for testing semiconductor chips is disclosed. In one embodiment, a chip to be tested which has a test logic, at least one test mode is set, the test modes are executed in the chip and test results or the status of the test modes are output from the...

20060156108 - Method for testing semiconductor chips using check bits: A method for testing semiconductor chips is disclosed. A chip to be tested has a test logic, at least one test mode is set in the form of a serial first bit string, the test modes are executed in the chip and test results or the status of the test...

20060156110 - Method for testing semiconductor chips using register sets: A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register...

20060156112 - Reduced signaling interface method & apparatus: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a...

20060156113 - Reduced signaling interface method & apparatus: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a...

20060156114 - Semiconductor device for accurate measurement of time parameters in operation: A memory-logics LSI device forms an input/output path for testing. A memory device has a memory input/output unit, which includes an input/output selector with test function. A test clock signal, TCLK, directly supplied in the test mode, is used to selectively take in one of input signals DI<k:0>, COM<i:0> and...

20060156102 - System and method to control data capture: One disclosed embodiment may comprise a system that includes a data capture system that stores a set of data from an associated data source in response to a store signal while enabled based on a control signal. A control system provides the control signal based on a number of store...

20060156111 - Test circuit and display device having the same: A test circuit and a test method capable of easily and accurately determining the presence or absence of a defect as well as defective points. The test circuit of the invention has a plurality of shift registers, a plurality of latch circuits, a plurality of first NOR circuits, a plurality...

20060156109 - Test mode circuit and reset control method therefor: A power control circuit is provided in a vehicle control ECU mounted in a vehicle. The control circuit, when making a shift to a test mode by a test mode circuit, closes a relay to supply a power voltage from a battery to a power line in the similar manner...

20060156106 - Test system: A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test target system such as a logic circuit is tested, data of the...

20060156100 - Test wrapper including integrated scan chain for testing embedded hard macro in an integrated circuit chip: An apparatus and method are disclosed for testing a hard macro that is embedded in a system on a chip (SOC) that is included in an integrated circuit chip. The SOC includes the hard macro. A logic design and operation of the hard macro are unknown. A test wrapper is...

20060156096 - Voltage converting device, computer readable recording medium with program recorded thereon for causing computer to execute failure processing, and failure processing method: A control device detects whether or not an up-converter fails, based on a DC voltage from a voltage sensor, an output voltage from a voltage sensor, and a duty ratio in controlling switching of NPN transistors. If a failure in the up-converter is detected, the control device then controls an...

20060156104 - Wrapper testing circuits and method thereof for system-on-a-chip: A wrapper testing circuit and method thereof for System-On-a-Chip is provided for electrical tests of core circuits of an integrated circuit. The testing circuit includes a decoding logic with an encoding table for receiving test signals and delivering control signals in response to the test signals according to the table;...

20060156121 - Emission control driver and organic light emitting display using the same: An emission control driver compensates for the threshold voltages of transistors to provide uniform brightness using a plurality of emission control signal generating circuits....

20060156120 - Light emitting device and method of driving the same: The present invention relates to a light emitting device for reducing consumption of an electric power in screen protecting mode. The light emitting device includes a plurality of data lines, a plurality of scan lines, a plurality of pixels, a controller, a data driving circuit and a scan driving circuit....

20060156122 - Mask network design for scan-based integrated circuits: A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit 207 in a selected scan-test mode 232 or selected self-test mode. The...

20060156116 - Method and apparatus for controlling ac power during scan operations in scannable latches: A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a functional data output and a scan data output. A switching control is provided with the functional data output. The switching control is driven to prevent switching...

20060156117 - Processor, its error analytical method and program: A plurality of error holding latches built in CPU cores formed on a LSI chip are connected and constituted into a line of error collecting scan chain, and the interior of the error collecting scan chain is divided into CPU latch groups corresponding to the CPU cores, and mask circuits...

20060156118 - Scan driver and organic light emitting display for selectively performing progressive scanning and interlaced scanning: A scan driver and an organic light emitting display (OLED) for selectively performing progressive scanning and interlaced scanning. The scan driver includes a plurality of scan units. A scan unit generates an odd-number scan signal or an even-number scan signal and includes a flip-flop and a scan signal generator. The...

20060156119 - Semiconductor apparatus and clock generation unit: A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input and output of data in the internal circuit, a clock generator for generating a launch clock signal for sending data to...

20060156124 - Boundary scan apparatus and interconnect test method: An electronic device, such as chip, card, system and in situ boundary scan test facilities are disclosed. The boundary scan test facility includes a boundary scan cell (Level Sensitive Scan Design, LSSD structure and selector) connected between output pads of the electronic device. By so doing the test path for...

20060156123 - Fault free store data path for software implementation of redundant multithreading environments: A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked reaches protected memory without any faults. The present...

20060156125 - Shift register system, method and driving circuit: An exemplary shift register system (31) includes a shift register (311), and four switches (312-315). The shift register includes input pins, output pins, a start pin, a reset pin, a first controlling pin, and a second controlling pin. Each switch includes input pins according to the output pins of the...

20060156126 - Semiconductor test instrument: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator...

20060156127 - Method for transmitting data: A method for transmitting data, in which a first signature is formed according to a specifiable signature formation method as a function of the data to be transmitted, the first signature is transmitted together with the data a second signature is formed according to the signature formation method as a...

20060156128 - System and method for implementing postponed quasi-masking test output compression in integrated circuit: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit....

20060156129 - System for maintaining data: The invention provides a method for maintaining data stored in a processing device the method comprising the steps of: generating a signature indicative of the data stored in the processing device; communicating the signature to a maintenance node; and receiving updated data from the maintenance node, the updated data being...

20060156133 - Flexible memory built-in-self-test (mbist) method and apparatus: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing....

20060156131 - Method of reducing hardware overhead upon generation of test pattern in built-in sef test: A method of reducing hardware overhead upon the generation of a test pattern in a built-in self test is introduced, in which two pieces of hardware perform a lot of functions even prior to generation of deterministic patterns, thereby reducing the amount of hardware required for conventional pseudo-random pattern generation...

20060156134 - Programmable memory built-in-self-test (mbist) method and apparatus: Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing....

20060156130 - Self test method and apparatus for identifying partially defective memory: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the...

20060156132 - Semiconductor device with built-in scan test circuit: The clock cycle during the shift operation is set shorter than the clock cycle during the capture operation in the scan test circuit. For example, the clock cycle during the shift operation is set to 20 nano second, while the clock cycle during the capture operation is set to 100...

20060156135 - Tabbed form with error indicators: An improved graphical user interface having a tab feature. In addition to conventional tabs, each one containing a specific field to be filled, an image is added to all tab captions to indicate if each tab is correctly filled. If the tab is not correctly filled, there is an error...

20060156136 - System for storing device test information on a semiconductor device using on-device logic for determination of test results: A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on...

20060156139 - Systems and methods for facilitating testing of integrated circuits: Systems and methods for testing integrated circuits (ICs) are provided. In this regard, a representative method involves an IC having a first pad configured as a signal interface for components external to the IC, the first pad having a first receiver configured to receive an input signal from a component...

20060156138 - Test pattern generating apparatus, circuit designing apparatus, test pattern generating method, circuit designing method, test pattern generating program and circuit designing program: A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into test pattern generating object blocks and test pattern copying object blocks...

20060156137 - Test program set generation tool: A test specification and test program set for a given unit under test and a given automated test equipment platform is generated in an automated manner using information stored in a repository....

20060156140 - Network equipment and a method for monitoring the start up of such an equipment: The invention concerns a network equipment for connection to a local network and a method for monitoring the start up of a such an equipment. This equipment comprises a persistent memory for storing software, and advantageously also comprises: communication means for connection to said network, means for monitoring the start...

20060156142 - Automatic test pin assignment: A tool for facilitating automatic test pin assignment for a programmable platform device comprising: a process for collecting information related to the programmable platform device, a process for automatically initializing a test pin assignment for the programmable platform device, a process configured to receive user specifications for IOs and a...

20060156141 - Defect symptom repair system and methods: The present invention is related to the repair of defective items where the defect symptom does not readily suggest the action to repair the item. Test and repair technicians isolate and repair defects. The defect symptom repair system provides a means for the technicians to pool their experience without extensive...

20060156147 - Method and apparatus for measuring group delay of a device under test: A method of measuring group delay of a device under test is provided. The method includes the steps of providing an analog input signal with a predetermined period to the device under test to obtain a delayed output signal from the device under test, converting the analog input signal and...

20060156143 - Method for testing drive circuit, testing device and display device: A method of testing a drive circuit including a scan line drive circuit and a data line drive circuit for driving a display is disclosed. The display may include a plurality of scan lines and a plurality of data lines, each of said scan lines including an initial terminal coupled...

20060156144 - Removing the effects of unknown test values from compacted test responses: Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the...

20060156146 - Simplified high speed test system: A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter...

20060156145 - Using patterns for high-level modeling and specification of properties for hardware systems: This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties for design verification. This eliminates the need to code extra RTL to handle features such as...

20060156150 - Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal processor-based integrated circuit digital delay lines: A circuit board with a processing unit and a delay line with a controllable number of delay elements fabricated thereon includes apparatus for testing and calibrating the delay line elements. In the test mode, a calibrated pulse is delayed by the delay line while determining the logic state of pulse...

20060156148 - Application specific integrated circuit with internal testing: Application specific integrated circuits (ASICs) and methods are provided which allow for internal testing of an ASIC. One ASIC embodiment includes a processor on the ASIC. A memory is coupled to the processor. A test circuit is integrated on the ASIC and coupled to the processor to perform testing internal...

20060156149 - Semiconductor component, arrangement and method for characterizing a tester for semiconductor components: A tester for semiconductor components with a plurality of channels is connected to a specific semiconductor component in order to characterize the signal path between tester and semiconductor component under production conditions. The specific semiconductor component includes measuring units that are connected to connection contacts and in each case provide...

20060156154 - Addressing error and address detection systems and methods: Addressing error detection systems and methods are disclosed. A target address is written to a memory in an electronic system and subsequently output on an address path through which the memory is addressable. An addressing error is detected by determining whether the target address output on the address path is...

20060156159 - Audio data interpolation apparatus: An audio data interpolation apparatus and method for creating interpolated data corresponding to an error position in audio data using a filter having a filter characteristic that corresponds to a feature amount of the audio data, in accordance with at least data pieces before the error position of the audio...

20060156157 - Checkpoint restart system and method: The subject invention pertains to a systems and methods of restarting programs upon failure. In particular, the systems and methods provide for generation of a checkpoint component including program execution status or completion data as well as state. This checkpoint component can then be employed by an execution engine to...

20060156152 - Critical finalizers: A finalizer may include a notification that no tolerance for failure or corruption is expected. Any potential failure point, which may be induced by a runtime execution environment routine or subroutine that is associated with the finalizer may then be prepared apart from the finalizer....

20060156155 - Detecting errors in directory entries: In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured...

20060156161 - Dvi link with parallel test data: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of...

20060156156 - Error detection in a data processing system: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register...

20060156151 - Method and system for widening the synchronization range for a dmt multicarrier single pilot tone system: A system and method of widening the synchronization range for a DMT multicarrier single pilot tone system includes detecting a first phase error in a received pilot tone; detecting a second phase error in a received second two bit constellation data channel; converting the second phase error to a first...

20060156153 - Method of handling errors: An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine....

20060156160 - Methods and apparatus for error detection and correction of an electronic shelf label system communication error: An electronic price label (ESL) system with communication error correction is described. In one aspect, the ESL system automatically detects ESL communication errors which may result in incorrect data in the ESL's registers, and then automatically takes corrective action to update the ESL's memory with the correct data. In one...

20060156158 - Two-dimensional optical cdma system, pn coded wavelength/time encoder and decoder therein, and method of encoding/decoding: Disclosed herein are a CDMA optical system and encoder and decoder included therein. Time domain encoding means creates a time domain code having a sequence according to inputted data bits or a complementary code which is complementary to the time domain code. An optical modulation means selectively outputs lights, in...

20060156162 - Apparatus and method for retransmitting data in mobile communication system: In retransmitting data at high speed by a PHY layer in a mobile communication system, when data to be transmitted to the receiver is received from the MAC layer of the transmitter, the PHY layer of the transmitter transmits the data to the PHY layer of the receiver, receives first...

20060156163 - Method and device for decoding packets of data within a hybrid arq scheme: A device for decoding an incident FEC encoded packet of data within an ARQ scheme. The device includes a processor or processing means for performing successive decoding processes of successive intermediate FEC code encoded packets related to the incident FEC code encoded packet. The processor or processing means includes a...

20060156165 - Auto re-transmission request system and method in a wireless communication system: An ARQ system and method for a BWA communication system are provided. A transmitter activates an ARQ timer if exist transmission data or retransmission data and transmits the transmission data or the retransmission data to a receiver. The transmitter then receives a response signal for the transmitted data or the...

20060156164 - Data unit sender and method of controlling the same: A data unit sender and method of controlling a data unit sender are presented, in which a time-out monitoring procedure implements a first, longer time-out period (SRTO), and a second, shorter time-out period (QRTO), where a retransmission is executed after the shorter time-out period if the available transmission capacity value...

20060156166 - Operation of a forward link acknowledgement channel for the reverse link data: An acknowledgement method in a wireless communication system. Initially, a reverse supplemental channel (R-SCH) frame is received at a base station. The base station then transmits an acknowledgement (ACK) signal if quality of the received R-SCH frame is indicated as being good. A negative acknowledgement (NAK) signal is transmitted only...

20060156168 - Construction of irregular ldpc (low density parity check) codes using rs (reed-solomon) codes or grs (generalized reed-solomon) code: Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. A novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than...

20060156169 - Ldpc (low density parity check) coding and interleaving implemented in mimo communication systems: LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. Initially, a novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than regular LDPC codes...

20060156170 - Methods for the generation of s-random interleavers for turbo decoders with a parallel structure: The method allows to obtain, starting from an initial S-random interleaver permutation, stored in memory devices and having a spread S, a size K and a degree of parallelism M<K, and collision-free, an interleaver permutation having an increased size, which is also collision-free, by an expansion technique which is carried...

20060156167 - Running minimum message passing ldpc decoding: The invention relates to a decoding method for decoding Low-Density Parity Check codes in transmission and recording systems. The method comprises a running minimum loop comprising the following iterative sub-steps:—reading a reliability value from the input sequence of input reliability values,—comparing said reliability value with a stored value,—overwriting the stored...

20060156172 - Apparatus and method for interleaving channels in a mobile communication system: An apparatus and method interleaving symbols coded by a turbo encoder in a communication system that uses the turbo encoder for encoding transmission information into coded systematic symbols and at least one parity symbol pair, and maps the coded symbols using a second or higher modulation order before transmission. An...

20060156171 - Combining spectral shaping with turbo coding in a channel coding system: A method of combining spectral shaping with turbo coding in a channel coding system. The method comprises encoding user data with spectrally shaped encoding to provide a suppressed DC user data sector output. The method also comprises generating turbo coded redundant bits for the suppressed DC user data sector. The...

20060156173 - Method and apparatus for the efficient implementation of a totally general convolutional interleaver in dmt-based xdsl systems: The present invention provides a method and apparatus for the efficient implementation of a totally general convolutional interleaver in a discrete multi-tone (DMT)-based digital subscriber line (xDSL) system, such as a modem or the like, that uses forward error correction (FEC) and convolutional interleaving to combat the effects of impulse...

20060156179 - Construction of ldpc (low density parity check) codes using grs (generalized reed-solomon) code: Construction of LDPC (Low Density Parity Check) codes using GRS (Generalized Reed-Solomon) code. A novel approach is presented by which a GRS code may be employed to generate a wide variety of types of LDPC codes. Such GRS based LDPC codes may be employed within various types of transceiver devices...

20060156176 - Crc format automatic detection and setting: An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC format detection and switching without requiring a user...

20060156178 - Data error control: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one...

20060156180 - Device and method for determining a defective area on an optical media: A device and method for determining a defective area on an optical media (disc) by counting the number of errors within ECC blocks of t