Error detection/correction and fault detection/recovery inventions 05/06

20060112296 - Data recovery system for appliances: An improved data recovery system for appliances is provided. The system includes an operating module with operating memory which controls the appliance, a recovery module which recovers operation of the device upon a power disturbance, and a data storage device. During operation, critical data is saved to the data storage...

20060112297 - Fault tolerance and recovery in a high-performance computing (hpc) system: In one embodiment, a method for fault tolerance and recovery in a high-performance computing (HPC) system includes monitoring a currently running node in an HPC system including multiple nodes. A fabric coupling the multiple nodes to each other and coupling the multiple nodes to storage accessible to each of the...

20060112299 - Implementing application specific management policies on a content addressed storage device: Implementing application specific management policies on a content addressed storage device is disclosed. In one embodiment, each data object stored on the content addressed storage device is associated with one of a plurality of data sets. A corresponding data set specific management policy is associated with at least each of...

20060112298 - Method and computer program product to migrate legacy data to a raid array while contemporaneously providing user access to legacy data: A method and related computer program product for migrating legacy data to a RAID array while contemporaneously providing user access to legacy data, comprising connecting the legacy drive to the RAID controller, converting the legacy drive into a legacy array, selecting the legacy array and selecting the RAID array to...

20060112305 - Apparatus, system, and method for limiting failures in redundant signals: An apparatus, system, and method are disclosed for limiting failures in redundant signals. A coordination module generates a power status signal for each of a plurality of power modules. An input module receives a source signal. A signal generation module generates a plurality of output signals from the source signal...

20060112303 - Local backup device with remote management capability and method for remote backup management: Local backup operations in a computer are organized from a remote computer. The local computer has an intermediate device controller and at least one additional hard disk drive for backup. There are two types of backup operations provided. The first is an image backup which assures that the backup hard...

20060112300 - Method and computer program product for backing up and restoring online system information: A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage devices from being accessed by the operating system, and selectively revealing one or more of said hidden storage devices as needed to permit...

20060112301 - Method and computer program product to improve i/o performance and control i/o latency in a redundant array: A method and computer program product for improving I/O performance and controlling I/O latency for reading or writing to a disk in a redundant array, comprising determining an optimal number of I/O sort queues, their depth and a latency control number, directing incoming I/Os to a second sort queue if...

20060112302 - Method, system, and software for rebuilding a storage drive: When a storage drive used as part of a redundant storage system is rebuilt, a drive controller obtains information for the rebuild process from an operating system (OS) specific agent. The information may include a bitmap, which indicates portions of a logical unit being used by the operating system. The...

20060112304 - Methods and structure for detection and handling of catastrophic scsi errors: Methods and associated structure for rapidly detecting a catastrophic failure of a bus structure within a storage subsystem. Features and aspects hereof associated with SCSI bus storage system configurations coordinate such failure detection with standard monitoring features of the SAF-TE enclosure monitoring specifications. In particular, standard polling operations of a...

20060112306 - Method and apparatus for classifying memory errors: One embodiment of the present invention provides a system that determines the cause of a correctable memory error. First, the system detects a correctable error during an access to a memory location in a main memory by a first processor, wherein the correctable error is detected by error detection and...

20060112307 - System and method for error injection using a flexible program interface field: A system and method for injecting hardware errors into a microprocessor system is described. In one embodiment, a software interface between system software and system firmware is established. Software test and debug for software error handlers may thus be supported. The software interface may support both a query mode call...

20060112308 - Selection of status data from synchronous redundant devices: Techniques are provided for selecting status data. Redundant views are obtained from multiple synchronous redundant devices. It is determined that the redundant views from the multiple synchronous redundant devices are conflicting. A redundant view score is calculated for each of the redundant views based on one or more characteristics from...

20060112309 - Method and apparatus to backup data in a hard disk drive: Making backups of active data stored in hard disk drive, by copying one or more disk surfaces within the hard disk drive. The hard disk drives implement the method. The hard disk drive may include more than two disk surfaces. Copying a second disk surface to a first disk surface...

20060112310 - Storage of trace data within a data processing apparatus: The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to...

20060112311 - Device driver rollback: A system and method for device driver management/installation is provided. The device driver management system can be employed by a user to selectively rollback a currently installed device driver to one or a plurality of previously installed device driver(s). Additionally, the system can be employed by the user to revert...

20060112312 - Apparatus, system, and method for adjusting trace data granularity: An apparatus, system, and method are disclosed for adjusting trace data granularity. An initialization module sets a base granularity for trace data recorded for a component. A registration module registers a condition counter comprising a condition set. The threshold module sets a count threshold for the condition counter. An increment...

20060112313 - Bootable virtual disk for computer system recovery: A method of operating a computer including initiating an operating system boot process utilizing critical files stored in associated standard locations on a first peripheral device. After a successful boot, files critical to the standard operating system boot process are copied from the standard locations to a boot image residing...

20060112314 - Computer health check method: A method for providing maintenance services to client computers is disclosed, in which a health check software application periodically runs in each client computer to obtain health information of each client computer and then automatically transmits the obtained health information to a remote service provider for monitoring and diagnosing the...

20060112315 - Method and device for controlling operational processes, especially in a vehicle: The present invention relates to a method and a device for controlling operational sequences, in particular in a vehicle. In this context, a functional unit (3) for forwarding and receiving data via at least one connecting unit (4) is in contact with at least one bus system (2). Functional unit...

20060112317 - Method and system for managing information technology systems: Embodiments in accordance with the present invention include methods and systems for managing information technology systems. A method includes monitoring, with a computer system, service operations of a service provider; detecting, with the computer system, a failure; diagnosing, with the computer system, the failure to determine a cause of the...

20060112316 - Method of monitoring status of processor: A method of monitoring interrupts transmitted between a processor and a computer used for verifying the processor. The computer and the processor communicate with each other through an interconnect circuit. The method includes detecting a first interrupt transmitted either from the computer to the processor or from the processor to...

20060112318 - Image processing device: An image processing device is disclosed that includes a main CPU, and a display control CPU that controls the display on a display unit in accordance with commands from the main CPU. When the display control CPU is notified of the occurrence of an abnormality in the main CPU, the...

20060112320 - Test pattern compression with pattern-independent design-independent seed compression: The present invention is directed to a logic testing architecture with an improved decompression engine that compresses the seeds of a linear test pattern generator in a manner that is independent of the test pattern set....

20060112321 - Transparent error correcting memory that supports partial-word write: A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The...

20060107084 - Supercomputing: P

20060107085 - Recovery operations in storage networks: Exemplary storage network architectures, data architectures, and methods for creating and using snapdifference files in storage networks are described. One exemplary method may be implemented in a processor in a storage network. The method comprises detecting a failure in a source volume, and in response to the failure: terminating communication...

20060107088 - Apparatus for managing a device, program for managing a device, storage medium on which a program for managing a device is stored, and method of managing a device: A remote site managing system manages, in a unified fashion, computers and peripheral devices installed at a customer site. The remote site managing system automatically receives information indicating a failure which has occurred or indicating a high possibility that a failure will occur in some of PC/servers or peripheral devices...

20060107086 - Method and system for network fault analysis: A method and system for locating a fault in a network. According to the system, an address analyzer and interface analyzer of a network manager of the network detect that there is a failure associated with a node of the network, a node analyzer of the network manager determines if...

20060107087 - System for optimizing server use in a data center: A system and method for analyzing the usage of servers and their associated applications and providing suggestions on how to best make use of the resources of the servers. Numerous forms of analysis are utilized to provide suggestions to a user for efficient use of the servers. Should a suggestion...

20060107095 - Accelerated low power fatigue testing of fram: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches...

20060107093 - Algorithm to encode and compress array redundancy data: A method, an apparatus and a computer program product are provided for the compression of array redundancy data. Array redundancy data can be lengthy and take up a lot of space on a processor. This invention provides an algorithm that can compress array redundancy data for storage, and decompress and...

20060107089 - Diagnosing a path in a storage network: Described herein are exemplary storage network architectures and methods for diagnosing a path in a storage network. Devices and nodes in the storage network have ports. Port metrics for the ports may be ascertained and used to detect link problems in paths. In an exemplary described implementation, the following actions...

20060107090 - Dynamic memory architecture employing passive expiration of data: Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word...

20060107094 - Method for estimating the early failure rate of semiconductor devices: According to one embodiment of the invention, a method for estimating the failure rate of semiconductor devices includes obtaining accelerated stress duration data for a plurality of semiconductor devices, determining which of the semiconductor devices fail, classifying the defects for the failed semiconductor devices, determining a distribution model for the...

20060107092 - Performing retry operations: A method of performing a retry procedure may begin with detecting an error in a first zone of a data storage medium. Upon detecting the error, it is determined whether any retry procedure of a sequence of retry procedures has been performed upon detecting a previous error in the first...

20060107091 - System and method for recovery of data for a lost sector in a storage system: A system (and method) for a recovery of data from a lost sector in a storage system, which includes a set of readable and lost sectors in a plurality of disks in the storage system, includes identifying a lost sector of at least one disk of the storage system, determining...

20060107098 - Computer system: In A computer system, the processing load for the computer to acquire fault information from the storage system is reduced. The computer system includes a computer, a first storage system configured to be communicable with the computer, and a second storage system configured to be communicable with the first storage...

20060107097 - Data protection in a mass storage system: A method for distributing data over a set of N storage devices. The method includes apportioning the data into groups of (N−2) or fewer blocks, and adding to each group a parity block so as to form a parity set. The method further includes distributing the blocks of each parity...

20060107101 - Disk array subsystem, method for distributed arrangement, and signal-bearing medium embodying a program of a disk array subsystem: A disk array subsystem including D disk apparatuses, wherein, there is a redundancy of N (N is an integer equal to or larger than 3), the disk array subsystem includes data regions of each of the disk apparatuses and (N−1) copy regions on each of the disk apparatuses, first copies...

20060107096 - Method and system for network storage device failure protection and recovery: A method for executing a write request in a clustered computing environment, comprising a plurality of computers connected in a network, including at least one client computer accessing data blocks stored on a first storage device of a shared aggregated pool of storage devices. Data blocks stored on the first...

20060107099 - System and method for redundant storage with improved energy consumption: A system and method for reducing energy consumption in an information storage system is disclosed which takes advantage of the redundancy in a typical storage system....

20060107100 - Systems and methods for implementing content sensitive routing over a wide area network (wan): Systems and methods for optimizing storage network functionality. The methods and systems of the present invention are particularly useful for optimizing storage network performance for cases in which some components of the network may be separated by significant distances and/or which include communication links with relatively limited bandwidth. In certain...

20060107103 - Apparatus and method for recovering destroyed data volumes: In an embodiment of the invention, a method is provided for updating configuration information associated with a data volume. The method reduces the occurrences of updates of saved configuration information of a data volume by updating the saved configuration information only when a change occurs in a configuration of the...

20060107102 - Checking storage reconfiguration: A method for reconfiguring a storage system communicating with a host, consisting of the steps of formulating a proposed reconfiguration of the storage system from an original configuration, and generating a record of operations of the storage system during an evaluation period in the original configuration. In response to the...

20060107104 - Patching device for a processor: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A...

20060107105 - Error recovery level optimization in network system: To provide a technique whereby a value of an error recovery level determined in negotiation processing between an initiator and a target can be set to a suitable value that is intended by a manager. A storage system comprises a storage section containing a target module that is connected to...

20060107109 - Communication processing apparatus and method and program for diagnosing the same: The present invention makes it possible to detect abnormality in an error detecting function early while minimizing adverse effects on transfer performance. The present invention provides a method for diagnosing a transfer data ensuring system in which a transmitting apparatus transmits transmission data provided with an error detection code and...

20060107108 - Service clusters and method in a processing system with failover capability: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network...

20060107106 - System and method for maintaining in a multi-processor system a spare processor that is in lockstep for use in recovering from loss of lockstep for another processor: According to one embodiment, a method comprises assigning a first processor of a multi-processor system a role of spare processor for at least a second processor, and responsive to detecting loss of lockstep (LOL) for any of the at least a second processor, the first processor replaces the processor for...

20060107107 - System and method for providing firmware recoverable lockstep protection: According to at least one embodiment, a method comprises detecting loss of lockstep for a pair of processors. The method further comprises triggering, by firmware, an operating system to idle the processors, and recovering, by the firmware, lockstep between the pair of processors. After lockstep is recovered between the pair...

20060107110 - Supercomputing: A method of operating a supercomputer having a plurality of computing elements each connected to a fast communications link is disclosed, the method comprising the steps of: scheduling specified elements to perform computing tasks in specified cycles of a computing operation; in the event of failure of a fast communications...

20060107112 - System and method for establishing a spare processor for recovering from loss of lockstep in a boot processor: A system comprises a plurality of processors, and data storage storing information that assigns a role of boot processor to one of the plurality of processors and assigns a role of spare processor to another of the plurality of processors. The system further comprises logic operable, responsive to detecting loss...

20060107113 - System and method for facilitating bi-directional test file transfer: In one embodiment systems and methods are utilized that eliminate synchronization between cycles of a repetitive communication network quality test. This is accomplished by time-shifting each sample transmission to compensate for the time shift due to communication network delay and asymmetrical operation of network testers. In one embodiment, a dual-tone...

20060107111 - System and method for reintroducing a processor module to an operating system after lockstep recovery: According to one embodiment, a method comprises, responsive to detection of loss of lockstep (LOL) for a processor module in a system, setting status information stored to the system for the processor module to indicate that the processor module has an error. The method further comprises reestablishing lockstep for the...

20060107117 - System and method for configuring lockstep mode of a processor module: A system comprises a processor module that supports lockstep mode of operation. The system further comprises non-volatile data storage having stored thereto configuration information specifying whether the processor module is desired to operate in lockstep mode. A method comprises storing configuration information to non-volatile data storage of a system, wherein...

20060107116 - System and method for reestablishing lockstep for a processor module for which loss of lockstep is detected: According to one embodiment, a method comprises, responsive to detection of loss of lockstep (LOL) for a processor module in a system, firmware requesting an operating system to idle the processor module. The method further comprises the operating system idling the processor module and returning control of the processor module...

20060107115 - System and method for system firmware causing an operating system to idle a processor: According to one embodiment, a method comprises system firmware instructing a system's operating system to idle a processor, and responsive to the instructing, the operating system idling the processor and returning control over the processor to the system firmware. According to one embodiment, a method comprises detecting loss of lockstep...

20060107114 - System and method for using information relating to a detected loss of lockstep for determining a responsive action: According to one embodiment, a method comprises detecting a loss of lockstep (LOL) for a processor module. The method further comprises determining a type of LOL that is detected, and, based at least in part on the determined type of LOL, determining a responsive action to take for the LOL....

20060107118 - Apparatus to facilitate functional shock and vibration testing of device connections and related method: An apparatus and associated method are disclosed for facilitating the testing of device connections, including functional shock and vibration testing of peripheral card slots or any other desired connector interface. In part, a power supply located on the peripheral device, or some other external power source, is used to power...

20060107119 - Self-contained computer servicing device: Servicing a computer using a self-contained computer servicing device. The device includes a memory storing an operating system. The device includes a first interface for connecting the device to the computer and a second interface for connecting the device to a network. A driver for the second interface is also...

20060107120 - Microprocessor design support for computer system and platform validation: Elements of a computer system are tested by generating harassing transactions on a bus. A first transaction is detected on the bus. The first transaction including a first data request to a first address. In response to and based upon detecting the first address, a second data request is generated...

20060107121 - Method of speeding up regression testing using prior known failures to filter current new failures when compared to known good results: A method, system, and program product for regression testing computer code. The first step is regression testing is providing a regression test of a pre-change body of computer code, where the regression test of the pre-change code has known failures. The main body of code, that is the changed and...

20060107122 - Methods and apparatus for emulating software applications: Methods and apparatus for adjusting processing capabilities permit obtaining identification information that is indicative of a version of a software program stored in the storage medium; determining whether processing capabilities of one or more processors on which the software program is to be executed should be adjusted in accordance with...

20060107123 - Processor and development supporting apparatus: A processor includes a statically scheduled command removal unit which removes a statically scheduled command upon receiving a command issuing signal, a command execution condition establishing signal, and a statically scheduled execution determination signal that indicates a command for which execution is determined in advance, an encoding unit which encodes...

20060107124 - Storage apparatus: This invention provides a storage apparatus which can avoid a data lost even when a short-circuit fault occurs in a power source line which is not made redundant for a plurality of hard disk drives. In the storage apparatus, a storage control unit comprises a host interface control unit, a...

20060107125 - Recoverable machine check handling: A technique for handling hardware errors in a computing system, such as a data storage facility, while avoiding a system crash. An interface is registered with an operating system of the computing system to process hardware errors. When a hardware error is detected, the interface checks an error register to...

20060107126 - Edge selecting triggering circuit: A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having...

20060107127 - Data management technique for improving data reliability: A method for managing data stored in a non-volatile memory having a plurality of memory blocks includes, first, determining if an error occurs in the read data in a selected memory block. If an error occurs in the read data in the selected memory block, then a region to which...

20060107128 - Qos control method, transmission apparatus and storage medium: An automatic detection of failure occurrence on a network and selection of QoS table defining a priority for communication among the nodes constituting the network in response to a degeneracy situation of the network caused by the failure upon detection thereof make communications among the nodes by using the selected...

20060107129 - Method and computer program product for marking errors in bios on a raid controller: A method and related computer program product of preventing write corruption in a redundant array in a computer system, comprising detecting a write failure from a calling application to at least one disk of the redundant array, writing failure information to non-volatile storage; returning an I/O error to the calling...

20060107131 - Multi-platter disk drive controller and methods for synchronous redundant data operations: The present disclosure pertains to multiple-platter disk drive digital data storage with integrated redundancy operations for improved reliability. Within a single disk drive assembly (300), one or more individual storage platters (304) can be used to store redundant data, enabling recovery of user data in the event that another platter...

20060107130 - System and method of reading non-volatile computer memory: The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a data sector of the non-volatile computer memory. The first portion of the redundant memory area includes data associated with the data sector....

20060107135 - Row-diagonal parity technique for enabling efficient recovery from double failures in a storage array: A “row-diagonal” (R-D) parity technique reduces overhead of computing diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of two storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity...

20060107136 - Smart verify for multi-state memories: The present invention presents a “smart verify” technique whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations. It does so by providing “intelligent”...

20060107132 - System and method for testing a memory for a memory failure exhibited by a failing memory: A system and method for testing a memory under test on automated test equipment (ATE) that includes capturing operating conditions for a memory exhibiting a memory failure in a sequence of records corresponding the operating conditions over a period of time that includes the occurrence of the memory failure and...

20060107133 - Tampering-protected microprocessor system and operating procedure for same: A tampering-protected microprocessor system includes a microprocessor, an internal write/read memory integrated with the microprocessor into a common module, and a second memory in which at least a portion of an operating program to be executed by the microprocessor is stored. At least one procedure of the operating program which...

20060107134 - Test apparatus for semiconductor memory device: A test apparatus for a semiconductor memory device applies a test input pattern to the semiconductor memory device to produce a test output pattern. The test apparatus compares the test output pattern to an expected output pattern using a plurality of comparators to determine whether the semiconductor memory device is...

20060107137 - Chip testing methods and chips: Testing methods and chips preventing sampling errors caused by asynchronous effect. The chip comprises a first logic portion driven by a first clock signal with a first operating frequency, and a second logic portion driven by a second clock signal with a second operating frequency. The first operating frequency is...

20060107141 - Database mining system and method for coverage analysis of functional verification of integrated circuit designs: Database mining, analysis and optimization techniques in conjunction with the model-based functional coverage analysis are used to turn raw verification and coverage data into design intelligence (DI) and verification intelligence (VI). The required data and attributes are automatically extracted from verification, simulation and coverage analysis databases. Design finite state machine...

20060107140 - Semiconductor device with termination resistor circuit: A semiconductor device includes a signal line, a test load circuit and a termination circuit. The signal line is connected with an input/output node of the semiconductor device. The test load circuit has a test resistor and is provided between the signal line and a first one of power lines...

20060107139 - Sequential control circuit: A sequential control circuit operates according to an input signal. When the input signal is determined at a first state, the sequential control circuit asserts a plurality of control signals in a predetermined sequence. When the input signal is determined at a second state, the sequential control circuit de-asserts the...

20060107138 - Transceiver module: A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC...

20060107143 - Organic light emitting display: An organic light emitting display including a demultiplexer on each data line that splits and supplies each data signal to a plurality of data lines, thereby decreasing the number of output lines required and reducing production cost. Further, voltages corresponding to the data signals are sequentially charged in data capacitors,...

20060107144 - Power reduction in module-based scan testing: A circuit and method for reducing the power consumed by module-based scan testing. In one embodiment constant data is provided to inputs, such as 33, of scan chains not used in testing, such as 32. Another embodiment is a method whereby transitions in a subset of scan chains, such as...

20060107142 - Semiconductor integrated circuit: A semiconductor integrated circuit for performing processing relating to a test of a plurality of memory units provided therein while suppressing an increase of a circuit area is provided, wherein testing input data generated in a testing circuit is shifted successively on registers of a first data shift circuit formed...

20060107145 - Combinatorial at-speed scan testing: A processor including a first distributed shift generator associated with a first time domain, wherein the first distributed shift generator is coupled to a first group of scan chains, the first distributed shift generator to send a shift-enable-flop signal to be received by the first group of scan chains. The...

20060107146 - Demultiplexing circuit, light emitting display using the same, and driving method thereof: A demultiplexing circuit, a light emitting display using the same, and a driving method thereof, in which the number of output lines provided in a data driver is reduced. The light emitting display includes: a scan driver for supplying scan signals to scan lines in sequence; a data driver provided...

20060107147 - Semiconductor device with timing correction circuit: A semiconductor device includes a timing correction circuit coupled to an external terminal for receiving an input data signal to change a relative timing between the input data signal and an internal clock signal to generate a plurality of relative latch timings to latch one of the input data signal...

20060107151 - Automatic fault-testing of logic blocks using internal at-speed logic-bist: System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The...

20060107148 - Automatic self-testing of an internal device in a closed system: A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from an external device. In addition, a closed system including automatic,...

20060107149 - Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit: A method of controlling test data with a boundary latch module having a plurality of latches to facilitate logic built-in self-testing of an integrated circuit (IC) is provided which includes providing a plurality of selection devices for selecting initialization data to store in the plurality of latches of the IC's...

20060107150 - Semiconductor device and test method thereof: A semiconductor device having a plurality of circuits with the same configuration, wherein since expected values in the number corresponding to the number of circuits are not required, operation tests are effectively performed in a short time. The semiconductor device has first, second and third digital filters with the same...

20060107153 - Linear associative memory-based hardware architecture for fault tolerant asic/fpga work-around: A programmable logic unit (e.g., an ASIC or FPGA) having a feedforward linear associative memory (LAM) neural network checking circuit which classifies input vectors to a faulty hardware block as either good or not good and, when a new input vector is classified as not good, blocks a corresponding output...

20060107152 - Testing using policy-based processing of test results: A testing technique and apparatus are described for apply a test to a System Under Test (SUT) in one or more configurations of the SUT. The test can generate and store multiple output results that capture the behavior of the SUT in performing the test. Policy analysis logic applies a...

20060107154 - Through-core self-test with multiple loopbacks: An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured...

20060107156 - Hub for testing memory and methods thereof: A hub for testing memory and methods thereof. The hub may include a test block a test block and a transparent mode block. The test block may be configured to generate a pseudo random pattern based on received memory control information and to write the pseudo random pattern to at...

20060107155 - Semi-conductor component test device, in particular data buffer component with semi-conductor component test device, as well as semi-conductor component test procedure: h

20060107158 - Functional coverage driven test generation for validation of pipelined processors: A functional coverage based test generation technique for pipelined architectures is presented. A general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. A functional fault model is developed and used to define the functional coverage for pipelined architectures. Test...

20060107157 - Method and apparatus of fault diagnosis for integrated logic circuits: In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input signal lines and the output signal lines, different symbols are injected into fanout branches of one faulty...

20060107159 - Intelligent storage of device state in response to error condition: An algorithm helps ensure recordation of the state corresponding to an error or a catastrophic failure that requires a failing device to be sent to the manufacturer, rather than just the state of a byproduct error or failure or the state of an unrelated error or failure....

20060107160 - Method and apparatus for optimized parallel testing and access of electronic circuits: A Parallel Test Architecture (PTA) is provided that facilitates concurrent test, debug or programmable configuration of multiple electronic circuits (i.e., simultaneously). The PTA includes a communications path, a primary test controller, and a number of local test controllers. The primary controller provides stimulus, expected, and mask data to the local...

20060107161 - Flexible rate and punctured zigzag codes: A generalized zigzag code is described where the code segments (each including one parity bit and information bits) of a block are not necessarily of uniform length. For coding rates in which the average code segment length is not an integer, all code segment lengths may be identical. The number...

20060107162 - System and method for checking bios rom data: A system for checking BIOS ROM data is disclosed. The system includes a keyboard (10), a display (20), a computer host (30), and a checking device (40). The computer host (30) has a BIOS ROM (301) installed therein. The checking device (40) includes: a data dividing module (400) for dividing...

20060107163 - Turbo decoding apparatus and interleave-deinterleave apparatus: In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory...

20060107166 - Enhanced block acknowledgement: Embodiments disclosed herein address the need in the art for enhanced block acknowledgement. In one embodiment, a receiver indicates a decoding delay for a maximum size aggregate frame in Block Ack negotiation, which may be used by a transmitter to determine to which Block Ack Request a Block Acknowledgement is...

20060107164 - Method and apparatus for adjusting service rate to adapt to channel conditions: An approach is disclosed for a satellite terminal to utilize a lower transmit rate when transmission conditions do not permit the terminal to successfully transmit at a higher, preferred service rate. The terminal monitors retransmissions to determine whether transmission is possible at the higher rate. As an initial measure, the...

20060107167 - Multiple antenna communication system using automatic repeat request error correction scheme: An Automatic Repeat reQuest (ARQ) error correction transmitting apparatus and method in a multiple antenna system are provided. In the ARQ error correction apparatus, a serial-to-parallel converter converts serial input data to parallel data, a retransmission processor determines a permutation transmission mode with respect to an initial transmission mode, in...

20060107165 - Transmitting apparatus, receiving apparatus, and re-transmission control method: A wireless communication device performs error correction decoding after combining newly received data from a new transmission of data and retransmitted received data from a retransmission of the data. The wireless communication device comprises a storage unit operable to store newly received data, a reception quality evaluation unit operable to...

20060107168 - Method and apparatus for transmitting/receiving virtual block information for multiple segment recovery in data network using transmission control protocol: A method and an apparatus are provided for acknowledging a bitwise block for multiple segment recovery when data is transmitted using a TCP in a data network. A transmitter generates a BBACK including virtual block information consisting of a bit array, each bit of which represents a virtual block of...

20060107172 - Apparatus for accessing and transferring optical data: An accessing/transferring apparatus has a first memory having multiple memory banks, each of the memory banks having multiple logical memory sections, each of the logical memory sections forming a memory matrix; a memory controller that uses the page-mode function or alternate-bank-access function of the first memory to write the data...

20060107173 - Data processing method, data recording apparatus and data transmission apparatus: The present invention provides a data processing method that can reduce the number of data blocks belonging to a same error-correcting code word for two-dimensional error bursts that give rise to errors over a plurality of transmission channels. There is provided a data processing method for coding digital data by...

20060107171 - Interleaver and de-interleaver systems: This invention relates to bit interleaver and de-interleaver apparatus, methods and processor control code for use in MIMO (Multiple-input multiple-output) communications systems, in particular MIMO systems employing OFDM (orthogonal frequency division multiplexing). We describe a block interleaver for a MIMO communications system, said interleaver being configured to interleave a block...

20060107170 - Methods for the determination of fec parameters in dmt based xdsl systems in the presence of system imposed constraints: The present invention provides procedures for computing Forward Error Correction (FEC) parameters given a set of constraints on maximum interleaver memory, maximum interleaver depth, maximum codeword size, maximum number of check bytes, maximum number of FEC codewords per Discrete Multi-Tone (DMT) symbol, and minimum number of DMT symbols that the...

20060107169 - Support of a forward error correction: To support a forward error correction scheme, in which a code of the forward error correction scheme is employed at a transmitting end for encoding data for a transmission to a receiving end, the transmitting end compresses at least one binary parity check matrix associated to the employed code of...

20060107174 - Seamless change of depth of a general convolutional interleaver during transmission without loss of data: Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and an interleaver depth is adjusted according to the monitored impulse noise without interrupting communication service....

20060107179 - Amplifying magnitude metric of received signals during iterative decoding of ldpc (low density parity check) code and ldpc coded modulation: Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection...

20060107180 - Apparatus and method for constructing low-density parity check matrix: An apparatus and method for constructing a low density parity check matrix. A p-th positive-shift block is generated by shifting all elements of an identity matrix p times to the right; a p-th negative-shift block is generated by shifting all elements of the identity matrix p times to the left;...

20060107176 - Concatenated iterative and algebraic coding:

20060107182 - Data storage systems: Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream...

20060107181 - Decoder architecture system and method: A decoder may perform node data reordering for bit node processing and node data reordering for bit node to check node interconnections. The decoder may also utilize a single barrel shifting operation on data read from an edge memory for bit node processing or check node processing during a memory...

20060107183 - Error-correction coding method, error-correction decoding method, error-correction coding apparatus, and error-correction decoding apparatus: An error-correction coding method and an error-correction decoding method utilize error detection and error correction for an audio signal when a video signal and the audio signal are multiplexed and transmitted by a DVI. After an error correction code is added to each sample of the digital audio signal, n...

20060107177 - Information storage device: A control unit transfers user data and an ECC that are read from a magnetic disk and stored in an FIFO to a data buffer. An erasure position movement control unit shifts an erasure start position from a predetermined initial value at predetermined intervals of erasure movement step, and an...

20060107178 - System and method for data entry: A system and method for data entry by an operator uses data containing a first component and a second component derived therefrom, wherein the second component has error detection and correction abilities therein. The second component of the entered data is used to detect and correct error in the data...

20060107175 - System, method and storage medium for providing fault detection and correction in a memory subsystem: A memory subsystem with a memory bus and a memory assembly. The memory bus includes multiple bitlanes. The memory assembly is in communication with the memory bus and includes instructions for receiving an error code correction (ECC) word in multiple packets via the memory bus. The ECC word includes data...

20060107184 - Bit failure detection circuits for testing integrated circuit memories: A bit failure detection circuit supports reliability testing of a memory device by accumulating a sum of data errors in data read from the memory device. The detection circuit compares a plurality of bytes of data read from the memory device against a plurality of bytes of reference data supplied...

20060107185 - Recording medium having spare area for defect management and information on defect management, and method of allocating spare area and method of managing defects: A recording medium having a spare area for defect management and the management information of the spare area, a spare area allocation method, and a defect management method. When a primary spare area is allocated for slipping replacement and linear replacement upon initialization, and a remaining portion of the primary...

20060107189 - Assembling forward error correction frames: The invention relates to a method for assembling FEC frames for a sequence of groups of coded media packets. In order to reduce a buffer delay at a decoding end (15), it is proposed that the FEC frame is aligned with the groups of media packets. To this end, a...

20060107187 - Buffering packets of a media stream: Buffering packets of a media stream for transmission from a transmitting device to a receiving device. Media packets are formed from at least one kind of media information in a stream generator; forward error correction data is formed on the basis of the media packets; one or more repair packets...

20060107188 - Packet transmission device and packet transmission method: A packet transmission device that is connected to a plurality of communication lines, and transmits a packet received, includes a failure detecting unit that monitors a condition of the communication lines, and detects a failure in the communication lines; and a packet transmitting unit that transmits, when the failure detecting...

20060107186 - System, method and storage medium for providing a high speed test interface to a memory subsystem: A buffer device for testing a memory subsystem. The buffer device includes a parallel bus port adapted for connection to a slow speed bus and a serial bus port adapted for connection to a high speed bus. The high speed bus operates at a faster speed than the slow speed...

20060107190 - Even-load software reed-solomon decoder: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is...

20060107191 - Program development support system, program development support method and the program thereof: Development of a program is supported by presenting importance of each part of the program. A program development support system comprises: a metrics information storage part 32 that stores metrics information for each part of the program, with the metrics information indicating complexity of the part in question in relation...

20060107192 - Hybrid automatic repeat request system and method: A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value...

20060107193 - Method and apparatus for efficiently decoding low density parity check code: A method and apparatus are provided for decoding a forward error correction code in a mobile communication system using a LDPC code. A check node processor performs check node processing on information received with a plurality of check nodes and an accumulator accumulates check node output values from the check...

20060101304 - Disk array subsystem: A disk array subsystem makes a diagnosis of a memory device while maintaining performance of a normal access to the memory device contained in a controller, thus enhancing reliability of the memory data. In the disk array subsystem having a disk drive and a controller, the controller has a cache...

20060101302 - Method and computer program product of keeping configuration data history using duplicated ring buffers: A method and related computer program product for storing first configuration information for a plurality of logical devices coupled to a RAID controller. Subsequent configuration information is stored for the plurality of logical devices coupled to the RAID controller while retaining previously written configuration information. Finally, in the event of...

20060101303 - Self-repairing of microprocessor array structures: A level of indirection is utilized when writing to a microprocessor array structure, thereby masking hard faults in the array structure. Among other benefits, this minimizes the use of a backward error recovery mechanism with its inherent delay for recovery. The indirection is used to effectively remove from use faulty...

20060101305 - Memory array repair where repair logic cannot operate at same operating condition as array: Memory array repair where the repair logic cannot operate at the same operating condition as the memory array is disclosed. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is...

20060101306 - Apparatus and method of initializing processors within a cross checked design: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent...

20060101307 - Reconfigurable computing machine and related systems and methods: A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit...

20060101308 - System and method for problem determination using dependency graphs and run-time behavior models: A problem determination system and method reduces the time and effort required by system administrators to trouble shot transaction processing difficulties in a large distributed I/T environment by monitoring system component performance and computing operational performance threshold limits based on dependency graphs for the system. Using this data, a prioritized...

20060101309 - Debugging simulation of a circuit core using pattern recorder, player & checker: Debugging a simulation of a circuit core uses a pattern recorder, a pattern player and a pattern checker to record input stimuli provided to a first core, record output generated by the first core due to the input stimuli, provide the recorded input stimuli to a second core, and determine...

20060101310 - Device, system and method for verifying integrity of software programs: A method, device and system for using a first verification algorithm or program to evaluate the integrity or authenticity of a second verification program. The first verification program may be stored in a device and may compare a result of such evaluation with a stored expected result. The second verification...

20060101311 - Connectivity between a scan tool and a remote device and method: A hand-held diagnostic tool is designed to operate and easily upgrade software applications developed for automotive diagnostics. The diagnostic tool, which communicates with a plurality of motor vehicle control units, provides application upgrades and/or modifications and/or new algorithms that are developed/adapted via remote updating. The tool comprises full diagnostic capability...

20060101312 - Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit: A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting...

20060101313 - Method and apparatus for decoding multiword information: A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective words can be ECC data, BIS data and LDC data, respectively. In...

20060101314 - Methods and apparatus for parallel execution of a process: In one embodiment, a process may be performed in parallel on a parallel server by defining a data type that may be used to reference data stored on the parallel server and overloading a previously-defined operation, such that when the overloaded operation is called, a command is sent to the...

20060101315 - Leakage current reduction system and method: An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a...

20060101316 - Test output compaction using response shaper: An improved test output compaction architecture and method is disclosed that takes advantage of a response shaper in order to minimize masking of faults during compaction....

20060101317 - Can system: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a...

20060101318 - Method and device for building a variable-length error code: The invention relates to a variable-length error-correcting (VLEC) code technique, in which the main steps are: defining all the needed parameters, generating a code having a fixed length L1, storing in a set W thus obtained all the possible L1−tuples distant of the minimum diverging distance d[min] from the codewords...

20060101319 - Input buffer device for de-rate matching in high speed turbo decoding block and method thereof: A high speed input buffer device for a turbo decoder and an input method thereof are provided. The input buffer device comprises a combing buffer for outputting stored symbols based on read addresses; a write MUX for dividing the output symbols into systematic, parity-1, and parity-2 symbols based on a...

20060095812 - Exception tracking: A method, apparatus, system, and signal-bearing medium that, in an embodiment, log trace data in response to an exception if the exception meets a filter criteria and create quality data from the trace data if a class in a call stack associated with the exception is owned by a user...

20060095813 - Disk array system and interface converter: The present invention aims to provide a high-reliability, low-cost disk array by emulating an ATA drive so that it can be used in the same way as an FC drive. To achieve this object, a disk array system of the present invention includes: a storage device having a logical unit...

20060095814 - Determining signal quality and selecting a slice level via a forbidden zone: In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier based on the number of data transitions at the first and second slice levels. Furthermore,...

20060095815 - Root cause correlation in connectionless networks: A method for correlating routing errors to link failures in a network, the method including detecting a link failure between a first and a second router NODES in a network, associating a first node address indicated in a first routing table of the first router with a first partition of...

20060095816 - Test clocking scheme: A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme...

20060095817 - Buffer for testing a memory module and method thereof: In a method, a test pattern and an associated input mode may be received where the input mode may indicate a manner of applying the test pattern. An output test pattern is applied to at least one of a plurality of memory interface pins in accordance with the input mode....

20060095819 - Method and system for clock skew independent scan register chains: A method and system for system for clock skew independent scan chains are disclosed. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second...

20060095818 - System and method for automatic masking of compressed scan chains with unbalanced lengths: A scan test architecture is implemented. The scan test architecture provides a method of performing scan test of unbalanced scan chains. The scan test architecture generates a control signal (i.e., masking signal) to mask bits in an unbalanced scan chain. In one embodiment, the control signal is generated with a...

20060095820 - Method, system, and program product for boundary i/o testing employing a logic built-in self-test of an integrated circuit: A testing method is provided which includes verifying at least one external signal path of an electronic package environment by testing an input/output (I/O) circuit of an integrated circuit of the electronic package environment with a logic built-in self-test (LBIST) of the integrated circuit, wherein the external signal path being...

20060095821 - Executing checker instructions in redundant multithreading environments: A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until...

20060095822 - Generation of test vectors for testing electronic circuits taking into account of defect probability: A method for generating test pattern signals weighted by the fault probability to greatly simplify the test process and to reduce the number of test vectors required for conducting the integrated circuit functionality tests. The method takes into consideration that the electrical short conditions occur mostly between adjacent nodes. The...

20060095823 - Test apparatus: There is provided a test having a pattern generating section for generating a test pattern, an expected value generating section for generating an expected value, an inversion cycle generating section for generating an expected value pattern of an output signal in which bits in a cycle of the expected value...

20060095824 - Determining circuit behavior: Systems, methodologies, media, and other embodiments associated with automatically determining circuit behavior are described. One exemplary system embodiment includes a data acquisition logic that is configured to access a netlist that describes a computer circuit. The exemplary system may also include a logical behavior logic that is configured to facilitate...

20060095825 - Firmware management apparatus and method: An apparatus for firmware management. A non-volatile memory device stores encoded data comprising an instruction and an error correction code. A processing unit acquires the encoded data, and corrects the encoded data based on the error correction code when an error in the encoded data is detected. The processing unit...

20060095826 - Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips: A semiconductor memory module includes a plurality of semiconductor memory chips. Each semiconductor memory chip includes an interface circuit that is configured to detect a transmission error in a write datum and is further configured to output, via a separate signal path, a repeat request signal for the repeated transmission...

20060095827 - Method and apparatus of turbo encoder: Briefly, an apparatus, a method and a wireless communication device are provided. The wireless communication device includes a turbo encoder to generate an encoded data block and a transmitter to transmit a data sub-block of the encoded data block in a time slot of a physical channel of the wireless...

20060095828 - Running digital sum coding system: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce...

20060095829 - Semiconductor device: A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source voltage not lower than...