Error detection/correction and fault detection/recovery inventions 02/06

20060041775 - Method and device for producing component data: A method of producing component data for use with an electronic component mounting apparatus includes a process of imaging a component whose component data is to be produced, by an imaging apparatus and displaying a component image on a display, the component image on the display having an outline further...

20060041774 - Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method: A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51...

20060041776 - Embedded software application: A system includes a platform on which a plurality of platform-specific I/O and fault-tolerance mechanisms are implemented. The system also includes an embedded software application operating on the platform and middleware which acts as a buffer between the application and the platform. In operation, the middleware logically separates the embedded...

20060041777 - Method and apparatus for seamless management for disaster recovery: A method, apparatus, article of manufacture, and system are presented for establishing redundant computer resources. According to one embodiment, in a system including a plurality of processor devices and a plurality of storage devices, the processor devices, the storage devices and the management server being connected via a network, the...

20060041779 - Method and apparatus for using a serial cable as a cluster quorum device: A method for obtaining a quorum vote by a first node using a quorum cable, wherein the quorum cable comprises a first end connected to the first node and a second end connected to a second node, including determining whether the quorum cable is reserved by the second node using...

20060041778 - Method and apparatus for using a usb cable as a cluster quorum device: A method for obtaining a quorum vote by a first node using a Universal Serial Bus (USB) quorum cable, wherein the USB quorum cable comprises a first end connected to a first node and a second end connected to a second node, including determining whether the USB quorum cable is...

20060041781 - Bounding defective regions of a tape storage medium: Systems and methods for storing data on a tape medium and coping with defective regions on the tape medium are provided. The method includes: writing a plurality of envelopes of data onto the tape medium, each envelope of data comprising a plurality of blocks of data; detecting a defective region...

20060041780 - Using parallelism for clear status track processing during error handling behavior in a storage system: Tracks of meta data are cleared in a storage server by allocating task control blocks for executing associated tasks in parallel. Throttling and recycling of task control blocks is provided to efficiently use memory and processing resources. Under the control of a master task, task control blocks are allocated to...

20060041783 - Enclosure for computer peripheral devices: A canister is for use with a data storage device and a casing of a computer peripheral enclosure with the casing having at least one compartment. Each compartment has a rectangular cross-section and a depth. Each compartment also has two guide rail guides. The canister includes a u-shaped tray and...

20060041782 - System and method for recovering from a drive failure in a storage array: A system and method for recovering from a drive failure in a storage array is disclosed in which a spare drive array is provided in the event of a failure in one of the active drives of the storage array. The spare drive array is comprised of multiple drives that...

20060041784 - Method and apparatus for retrieving data: The invention relates to a method of caching data stored in allocation units of a memory (102), preferably a harddisk drive system, of which retrieval incurs a performance penalty. An example of this is data in a spare sector (215), located in a spare area (210) on the hard disk...

20060041785 - Reception data synchronizing apparatus and method, and recording medium with recorded reception data synchronizing program: A synchronism pattern detecting timing recorder (20) records a synchronism pattern detecting timing at which a synchronism pattern is detected in reception data, a synchronism decider (12) collates the reception data with reference data to decide whether or not the reception data is consistent in phase with the reference data,...

20060041786 - Method of checkpointing parallel processes in execution within plurality of process domains: An embodiment of a method of checkpointing parallel processes in execution within a plurality of process domains begins with a step of setting communication rules to stop communication between the process domains. Each process domain comprises an execution environment at a user level for at least one of the parallel...

20060041787 - Camera test system: A test system for digital camera modules used in consumer electronics, e.g. cellular phones and PDA's is shown. The test system comprises of a tester and a module handler that is aimed at reducing test time by an order of magnitude. The Test system has an image-processing unit that uses...

20060041788 - Protecting code from breakpoints: A method, apparatus, system, and signal-bearing medium that, in an embodiment, prohibit breakpoints from being set within a protected range. In an embodiment, a protected range may be an atomic operation synchronization code range, either based on instructions generated by a compiler or based on source statements that are compiler...

20060041790 - Maximum change data pattern: In an embodiment of the invention, an apparatus for generating a maximum change data pattern, includes: a shift stage configured to shift a generated signal to the right by one bit and to generate a shifted signal; a logic stage configured to perform an XOR function on the signal and...

20060041789 - Storage system with journaling: A storage system including journaling comprises a controller capable of coupling to at least one storage device and to at least one journaling device, and a process executable on the controller. The executable process comprises a resolve utility capable of determining logical unit, track, and sector identification for a selected...

20060041791 - Hardware assist for microcode tracing: Debugging microcode is facilitated by a hardware assist that takes over from the microcode the basic management of handling the data for a trace entry, thereby reducing the load on the microcode to a single micro-instruction per trace operation and thereby permitting more trace points to be included in the...

20060041792 - Method, system and program for identifying a test specification for testing a file element: A file validator technique for identifying a test specification to be used for testing validity of a file element associated with a file is provided. The test specification is a member in one of a set of test specifications embedded in the file validator and a set of test specifications...

20060041794 - Methods, systems and computer program products for providing system operational status information: Methods for providing operational status information associated with a distributed application environment can include monitoring performance of actions occurring on separate components in a distributed application environment in response to a requested operation to determine operational status information of the distributed application environment based on reports provided by the separate...

20060041793 - System, method and software for enhanced raid rebuild: A system, method and software for enhancing a redundant array of independent disks (RAID) rebuild process are provided. In association with the RAID, one or more bit maps is maintained corresponding to one or more data blocks of the RAID. During input/output (I/O) operations directed to the RAID, the I/O...

20060041795 - Data-fusion receiver: This invention is an ultra-low frequency electromagnetic telemetry receiver which fuses multiple input receive sources to synthesize a decodable message packet from a noise corrupted telemetry message string. Each block of telemetry data to be sent to the surface receiver from a borehole tool is digitally encoded into a data...

20060041797 - Jitter applying circuit and test apparatus: There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an oscillating signal corresponding to a given reference signal, a variable delay circuit for outputting said clock signal in which said oscillating...

20060041796 - Method and apparatus for eliminating errors in a seek operation on a recording medium: A method and apparatus for eliminating errors in a seek operation on a recording medium are provided. Given a target address on a recording medium, a reading device is moved to seek the target address, and it is determined whether or not a signal is read out at the location...

20060041798 - Design techniques to increase testing efficiency: Specific test logic may be added into a semiconductor logic or memory device, which does not change the normal operation of the device, but which allows under test mode the device to perform both parallel read-compare and parallel write operations of the blocks within the device, which provides significant reduction...

20060041799 - Test apparatus, phase adjusting method and memory controller: An inventive test apparatus has a timing comparator for obtaining an output value of an output signal outputted from a memory-under-test with timing of a strobe signal, a logical comparator for comparing the output value obtained by the timing comparator with an expected value and for outputting a comparison result...

20060041800 - Method and apparatus for generating and detecting initialization patterns for high speed dram systems: A method and apparatus for determining the characteristics of a communications channel within a high speed memory system includes generating a first signal having a known and repeating pattern and generating a second signal having a pseudo-random pattern. The first and second signals are combined to produce a combined signal....

20060041801 - Acceleration of the programming of a memory module with the aid of a boundary scan (bscan) register: In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the...

20060041803 - Apparatus and method for dynamic in-circuit probing of field programmable gate arrays: A dynamic probe system for probing a FPGA with at least one core. A trace core is added to the FPGA, the trace core in communication with a plurality of signal banks, each signal bank comprising a plurality of signals in the at least one core. A logic analyzer, in...

20060041804 - Apparatus and method for testing semiconductor memory device: A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local...

20060041805 - Array substrate, display device having the same, driving unit for driving the same and method of driving the same: An array substrate of an N-line inversion type includes data lines, scan lines and pixels. A number of the data lines is ‘m’, and the data lines are extended in a first direction. A number of the scan lines is ‘n’, and the scan lines are extended in a second...

20060041802 - Functional frequency testing of integrated circuits: A method and circuits for testing an integrated circuit at functional lock frequency by providing a test controller generating control signals that assure proper latching of test patterns in scan chains at tester frequency and propagation of the test pattern through logic circuits being tested at functional clock frequency....

20060041806 - testing method for semiconductor device and testing circuit for semiconductor device: There is provided a testing method for a semiconductor device which has a test object circuit, a non-test object circuit, and a plurality of register circuits which carry out fetching and holding of data based on a clock signal, the semiconductor device including a plurality of first scan chains configured...

20060041807 - Integrated circuit: An integrated circuit has a memory block including a RAM macro, a first scan circuit and a second scan circuit having a plurality of SFFs, and a serial access memory BIST circuit. The first scan circuit has an input scan FF group capable of supplying data to the memory block...

20060041810 - Generating test patterns used in testing semiconductor integrated circuit: A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur...

20060041809 - Method for optimizing a pattern generation program, a program, and a signal generator: A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory,...

20060041808 - Test-pattern generation system, test-pattern analysis system, test-pattern generation method, test-pattern analysis method, and computer product: An activation test sequence: 11XX0 with a test sequence ID: 8 is input to an ATPG to generate an activation test sequence: 11000. A propagation test sequence: 11XX1 with a test sequence ID: 8 is input to the ATPG to generate a propagation test sequence: 11011 with a test sequence...

20060041813 - Adaptive fault diagnosis of compressed test responses: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the...

20060041811 - Circuit for testing power down reset function of an electronic device: A circuit for testing a power down reset function of an electronic device includes a reference power source (Vref), a first variable resistor (R1) with one end connected to the reference power source, a second variable resistor (R2), and a jumper (10). One end of the second variable resistor is...

20060041812 - Fault diagnosis of compressed test responses: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree....

20060041814 - Fault diagnosis of compressed test responses having one or more unknown states: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs...

20060041815 - System and method for retransmission of voice packets in wireless communications: A system and method for retransmission of voice packets in wireless communications are provided. The method includes transmitting a voice packet from a base station to a communication unit or from a communication unit to a base station at a rate faster than a generation rate of the voice packet....

20060041816 - Method for designing optimum space-time code in a hybrid automatic repeat request system: A method for designing an optimum STC in an HARQ system is provided, in which kth codes are detected which maximize the minimum squared Euclidean distance of the signal matrix of a combination code created by combining first to (k−1)th codes with a kth code. A kth code whose signal...

20060041817 - Accounting for error carryover in error correction on m-bit encoded links: 64/66b encoding (IEEE 802.3ae Standard for 10 Gigabit Ethernet) is based on a self-synchronous scrambler which inherently duplicates errors occurring in the transmission line. An error carryover indicator ECI vector is used to correct duplicated errors crossing the codeword boundary and entering into the next codeword. The ECI vector is...

20060041818 - Method and apparatus for mitigating fading in a communication system: Systems and methods are provided for mitigating fading in a wireless communication system. A wireless communication, having an associated communication channel, includes a coder that provides coding to a digital input signal. A block interleaver has an associated interleaving depth and interleaving span. The associated interleaving span is selected as...

20060041819 - Data decoding method and the system thereof: This specification discloses a data decoding method and the corresponding system. By improving the execution order of the error detection process during data decoding and using a descramble hardware processing structure, the method and the system can effectively reduce the number of times of memory access during the data decoding....

20060041822 - Error correction in rom embedded dram: Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM)....

20060041820 - Method and apparatus for receiving a control channel in a wireless communication system: A higher layer at a base station generates and passes messages to Layer 2, which generates and appends a CRC value to each message. The messages are encapsulated in frames at the physical layer, which generates and appends a CRC value to each frame. The base station transmits the frames...

20060041821 - Short length ldpc (low density parity check) code and modulation adapted for high speed ethernet applications: A short length LDPC (Low Density Parity Check) code and modulation adapted for high speed Ethernet applications. In some instances, the short length-LDPC code and modulation may be employed within the recommended practices currently being developed by the IEEE 802.3an (10GBASE-T) Task Force. The IEEE 802.3an (10GBASE-T) Task Force has...

20060041823 - Method and apparatus for storing and retrieving multiple point-in-time consistent data sets: A method, apparatus, and article of manufacture containing instructions for processing multiple point-in-time consistent data sets. The method consists of creating multiple point-in-time data sets associated with a backup appliance which is associated with backup storage. Upon the transfer of a first update from a primary storage controller to the...

20060041825 - Cyclic code circuit with parallel output: A cyclic code is generated by a circuit including a group of logic gates that generate one multiple-bit code segment from another multiple-bit code segment. The logic gates may, for example, receive B initial bits, where B is the degree of the generator polynomial, and generate one complete (2B−1)-bit code...

20060041824 - Method and apparatus for computing parity characters for a codeword of a cyclic code: A method for computing parity characters for a codeword of a cyclic code successively generates a sum of an output value and a respective message character of a first message section adjacent to parity characters within a first block. The method then successively multiplies a respective sum by corresponding coefficients...

20060041826 - Methods and apparatus for error correction of transparent gfp (generic framing procedure) superblocks: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder...

20060036889 - High availability multi-processor system: A method and system are provided for enabling replacement of a failed processor without requiring redundancy of hardware. The system is a multiprocessing computer system that includes one or more processor chips. Each processor chip may include one or more logical processors. During system initialization, one or more logical processors...

20060036890 - Remote computer disaster recovery and migration tool for effective disaster recovery and migration scheme: Computer tools and methods novelly combine periodic backup and restore features with migration features to transfer the components of a failed system to a new system, which new system may be dissimilar to the old system. As well as backing up and transferring critical data files during the disaster recovery...

20060036891 - System and method for i/o error recovery: A system and method for recovering from an I/O error in a distributed object-based storage system that includes a plurality of object storage devices for storing object components, a manager coupled to each of the object storage devices, wherein the object storage devices coordinate with the file manager, and one...

20060036892 - Apparatus and method for establishing tunnel routes to protect paths established in a data network: A computer readable storage medium containing a program element for execution by a computing device in a network having a plurality of linked nodes, wherein paths for conveying data traffic are defined in the network, each path traversing an ordered set of nodes from among the plurality of nodes. The...

20060036894 - Cluster resource license: A method, apparatus, system, and signal-bearing medium that, in an embodiment, receive a license to a number of resources in a cluster. The licensed resources may be activated and deactivated at any computer system in the cluster, so long as the number of active resources in the cluster is less...

20060036895 - Combined computer backup, disaster recovery and migration in a shared environment: Computer tools and methods novelly combine periodic backup and restore features with migration features to transfer the components of a failed system to a new system, which new system may be dissimilar to the old system. As well as backing up and transferring critical data files during the disaster recovery...

20060036896 - Method and system for consistent cluster operational data in a server cluster using a quorum of replicas: A method and system for increasing server cluster availability by requiring at a minimum only one node and a quorum replica set of replica members to form and operate a cluster. Replica members, independent from the nodes, maintain cluster operational data. A cluster operates when one node possesses a majority...

20060036893 - Method and system for debugging ethernet: A system is disclosed and claimed for debugging Ethernet adapters and Ethernet adapter device drivers by automatically monitoring Ethernet adapter functionality and automatically turning on debug traces upon detecting incorrect Ethernet adapter functionality. An embodiment maintains a counter representing the number of incorrect Ethernet adapter functionality events minus the number...

20060036897 - Data storage device: A data storage device comprises a flash memory controller having an interface controller, a buffer, a buffer management device, and a microcontroller therein. The interface controller receives several pieces of data and transfers them to the buffer management device, which temporarily stores the data into the buffer and can read/write...

20060036898 - File operation management device: The present invention provides file operation management devices, methods and processing systems which allow better utilization of application-processing units. It also provides file system operation functionality which requires less resources of the application-processing unit and provides a performance increase of the application. It provides a file operation management device for...

20060036899 - Method and apparatus for managing faults in storage system having job management function: A computer system identifies jobs affected by a fault which occurs in any device or mechanism in a storage system to control the execution of such jobs. The computer system includes a DBMS server device, a virtualization switch device, and storage device. Each of these devices holds part of data...

20060036900 - Communication system that reduces the amount of time required to switch over from an active access card to a standby access card: An input memory circuit, which has a plurality of addresses that have an associated plurality of keys, forwarding information, and enable/disable flags, receives a plurality of input cells, extracts key information from each input cell, compares the key information from each input cell with the keys, and outputs forwarding information...

20060036901 - Data replication method over a limited bandwidth network by mirroring parities: A method dramatically reduces the amount of data to be stored and transferred in a networked storage system. Preferably, the network storage system provides continued data protection through mirroring/replication, disk-to-disk backup, data archiving for future retrieval, and Information Lifecycle management (ILM). The idea is to leverage the parity computation that...

20060036902 - Method for operating a data storage medium: A method for operating a data storage medium when changing from an operating mode to a directly subsequent power-saving quiescent mode, where the operating mode effects a transmission delay for the last item of information which is to be transmitted, so that immediately after the last item of information which...

20060036904 - Data replication method over a limited bandwidth network by mirroring parities: A storage architecture provides efficient remote mirroring of data in RAID storage or like to a remote storage through a network connection. The storage architecture mirrors only a delta_parity. A parity cache keeps the delta_parity of each data block until the block is mirrored to the remote site. Whenever network...

20060036903 - Managing access to spare data storage devices: A dynamic storage system allows storage servers to access spare data storage devices should an associated data storage device fail or become inaccessible. A sparing server receives requests for spare data storage devices from storage servers and allocates spare data storage devices, establishing and maintaining a communication channel between the...

20060036905 - Method and related apparatus for verifying array of disks: When receiving a verification command for verifying a part of the disk array, each of the disks of the disk array are simultaneously verified such that a part of the disk array practically verified is larger than the part assigned to be verified in the verification command, and verification results...

20060036906 - System and method for detecting errors in a network: A system and method for efficiently and accurately detecting errors in a network is provided. Devices coupled to a network are configured to determine their local network status and transmit their local network status to a centralized location. The centralized location is configured to receive the local network status from...

20060036907 - Area-and product-independent test automation system and method for automatically synchronizing tests of multiple devices: An area- and product-independent test automation system and a method for synchronizing testing of multiple devices are disclosed. The test automation system may include a test sequence being written in a script language common to different products or test areas in an electronic component manufacturing or testing facility. Executable test...

20060036908 - System for backup storage device selection: A method and system for backing up computer data uses a network device to select a storage device in a manner that enhances at least one parameter associated with the backup process....

20060036909 - Soft error detection and recovery: A logic circuit is provided that implements soft error detection and recovery for protecting the logic circuit from the negative effects of soft errors caused by single event upsets. The logic circuit may include a configurable processing module, an input buffer, an output buffer, a configuration and scrub control module...

20060036910 - Automated testing framework for event-driven systems: Techniques for programmatically coordinating, and synchronizing execution of, automated testing in event-driven systems. One or more user-provided test system event listeners listen for generated events and updates test system status accordingly. A user-provided test suite definition invokes a test framework interface, thereby defining the structure of a test suite. This...

20060036911 - Method of verifying integrity of control module arithmetic logic unit (alu): A method of verifying the integrity of an arithmetic logic unit (ALU) of a control module includes inputting a first test value into one of a plurality of registers of the ALU and inputting a second test value into remaining registers of the plurality of registers. A first set of...

20060036912 - Functional device, function maintaining method and function maintaining program: This invention relates to a functional device such as an FPGA carrying out a necessary function by programming, and provides a functional device, a function maintaining method and a function maintaining program which can maintain a function continuously. A plurality of function parts (FPGAs) is provided, and a function is...

20060036913 - Method to reduce soft error rate in semiconductor memory: A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and...

20060036914 - Hazard mitigation in medical device: Delivery of energy by a defibrillator or other medical device is inhibited when the processor or software that controls a module of the medical device operates abnormally. A windowed watchdog timer (WWDT) incorporated into one module of the medical device is used to control the operation of other modules of...

20060036915 - Deskew circuit and disk array control device using the deskew circuit, and deskew method: A deskew circuit includes, for clock and every bit of data, a variable delay circuit between a receiver that receives data and a flip-flop that first latches the data, in which a detecting pattern to detect a stable region for receiving data is repeatedly sent before implementing a data transfer,...

20060036916 - Memory with test mode output: Apparatus and methods of forming and operating the apparatus provide a means for a memory to generate a test mode signal to trigger a test in response to the memory detecting a predetermined command from a system bus. In an embodiment, a mode register in the memory includes an indicator...

20060036917 - Method for testing a memory device and memory device for carrying out the method: The invention provides a memory device for data storage having a memory module (100) having at least one memory bank (101a-101n) in which data to be stored are stored and from which the stored data are read out, and a logic unit (106) for controlling a writing and a reading...

20060036918 - Method and apparatus to compare pointers associated with asynchronous clock domains: A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are not synchronized. One or...

20060036919 - Embedded logic analyzer: A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation...

20060036920 - Built-in self-test (bist) for high performance circuits: Test patterns for testing electrical circuits are generated by a MUX having its output operatively coupled to a Scan-In shift register and inputs receiving seed pattern signals, response signal from a response shift register, positive and negative signals from the Scan-In register. A control logic circuit provides control signals that...

20060036921 - Apparatus and method for dynamically repairing a semiconductor memory: An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed...

20060036922 - Apparatus and method for changing signal mapping rule in a hybrid automatic repeat request system: An apparatus and method for changing a signal mapping rule in an hybrid automatic repeat request (HARQ) system are provided. In a transmitter in an automatic repeat request (ARQ) system according to the present invention, a memory stores different signal constellations for a predetermined modulation scheme according to retransmission numbers...

20060036923 - Systems and methods for decreasing latency in a digital transmission system: Disclosed herein are various embodiments of methods, systems, and apparatus for encoding OFDM packets in a digital communication system. In one exemplary method embodiment, LDPC codewords in an IEEE 802.11 wireless transmission are shortened, decreasing the iterations necessary to insure accurate communications. The codewords are shortened by adding known bits...

20060036924 - Interleaving and parsing for mimo-ofdm systems: An apparatus (150) (170)-180), system (300) and method (200) (250) (270) (280) are provided for a wireless bit-interleaved coded OFDM (BI-COFDM) multiple-in-multiple-out (MIMO) system that improves the diversity seen by a convolutional decoder. In one embodiment, the bit stream is interleaved (202) first, then bits are mapped (203) into symbols...

20060036925 - Apparatus and method for coding/decoding block low density parity check code with variable block length: Disclosed is a device and procedure for coding a block low density parity check (LDPC) code having a variable length. The a device and procedure includes receiving an information word; and coding the information word into a block LDPC code according to a first parity check matrix or a second...

20060036927 - Apparatus and method for encoding and decoding a block low density parity check code: Apparatus and method for coding a block low density parity check (LDPC) code. Upon receiving an information word vector, an encoder codes the information word vector into a block LDPC code according to a predetermined generation matrix. A modulator modulates the block LDPC code into a modulation symbol using a...

20060036928 - Code design and implementation improvements for low density parity check codes for multiple-input multiple-output channels: Methods and systems for designing LDPC codes are disclosed. A method in accordance with the present invention comprises configuring a plurality of parallel accumulation engines, a number of the plurality of parallel accumulation engines equal to M, accumulating a first information bit at a first set of specific parity bit...

20060036926 - Simplified ldpc encoding for digital communications: Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all...

20060036929 - Method of configuring transmission in mobile communication system: Method for configuring a transmission chain in a 3GPP2 system for supporting a flexible or variable data rate of an information bitstream in a process for mapping an information bitstream of a data rate on a physical layer, including the steps of (1) channel coding the information bitstreams with bit...

20060036930 - Method and apparatus for fast encoding of data symbols according to half-weight codes: Efficient methods for encoding and decoding Half-Weight codes are disclosed and similar high density codes are disclosed. The efficient methods require at most 3·(k−1)+h/2+1 XORs of symbols to calculate h Half-Weight symbols from k source symbols, where h is of the order of log(k)....

20060036931 - System and method for refreshing metric values: The disclosed embodiments relate to a system and method of refreshing metrics. The method may comprise obtaining a plurality of data elements that comprise information about a process and computing a plurality of metrics from a plurality of mappings, each of the plurality of mappings relating to an operation on...

20060036932 - Method and apparatus for encoding and decoding data: A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f, i, j)} for a code...

20060036933 - Method and apparatus for encoding and decoding data: A base model matrix is defined for the largest code length of each code rate. The set of shifts {p(i,j)} in the base model matrix are used to determine the shift sizes for all other code lengths of the same code rate. Shift sizes {p(f; i, j)} for a code...

20060031706 - Architecture for high availability using system management mode driven monitoring and communications: A computer system and method for providing high availability. The computer system includes an application level, an operating system level supporting the application level, and a firmware level supporting the operating system level. The firmware level includes a microprocessor having a system management mode that functions independently from the operating...

20060031707 - Notification method and apparatus in a data processing system: A method of, apparatus for, or storage device medium having instructions for publishing a first notification within a data processing system where the data processing system comprises a first source generating the first notification, a first destination device, and a second destination device. The source may be a storage unit,...

20060031709 - Failure monitoring for storage systems constituting multiple stages: To provide a computer system capable of detecting a failure at an early stage while keeping down an increase in I/O load due to failure monitoring. The computer system includes plural storage systems connected in stages between a first computer and a second computer. The first computer sends control I/O...

20060031710 - Flash memory device for performing bad block management and method of performing bad block management of flash memory device: A flash memory device for performing a bad block management and a method of performing bad block management are implemented in hardware level. During a booting procedure of a flash memory device, a bad block-mapping table stored in a predetermined block of memory cell array unit or other nonvolatile memory...

20060031711 - Information processing apparatus and information notification method therefor, and control program: To enable the host server side to be aware of the recovery of an error when the error is recovered by the user's power off/on operation, the most recent state regarding occurrences of errors at printer 16 (steps S61 and S62) is stored in the backup RAM 12a each time...

20060031708 - Method and apparatus for correcting errors in a cache array: A system and method is provided for correcting errors in a cache array. Embodiments may include a lower level cache tag array to store a plurality of lower level tags to identify a location in a lower level cache of a requested data, an error detection element to detect that...

20060031712 - Method and system for calculating single and dual parity for networked storaged elements: A method of calculating single and dual parity for a networked array of storage elements is presented. The method includes deriving a first set of n relationships where each of the first set of n relationships consists of an XOR statement equaling zero. Each of the first set of n...

20060031713 - System and method for validating channel transmission: A system for validating communications between a plurality of processors is disclosed. The system includes a plurality of loop back paths, and each of the loop back paths is coupled to a corresponding one of the plurality of processors. In addition, each loop back path is configured to attenuate one...

20060031714 - Apparatus and method to preserve data integrity during a power loss: A method is disclosed to preserve data integrity during loss of power to an information storage and retrieval system. Applicants' method converts a plurality of sectors having a first sector format to a plurality of sectors having a second sector format. If a power failure warning is received during the...

20060031715 - Manual start learning process and manual start process for use with an automated system: A method and apparatus for use with a system including a processor that controls a resource configuration to perform a sequence including a plurality of cells, the method for programming the processor to help a system operator restart the sequence after the sequence is halted, the method comprising the steps...

20060031716 - Method of providing a real time solution to error occurred when computer is turned on: The present invention relates to a method of providing a real time solution to an error occurred when a computer is turned on, which enables a BIOS installed in the computer to test all hardware equipment of the computer and record any detected error, and also enables the BIOS to...

20060031717 - Bootable post crash analysis environment: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for...

20060031718 - System and method for generating production-quality data to support software testing: Providing data as part of a testing regime for computer software. Random data values can be automatically generated to support the testing of any type of computer software that operates on data as part of its function. This random generation of data values can provide a breadth of data needed...

20060031719 - Identifying temporal ambiguity in a aggregated log stream: A method and system for ordering and aggregating log streams. Log streams for events from different sources are received. If different sources have different recording cycles, or time epochs, that lead to different temporal granularities, then all of the log streams are combined into a single time epoch that is...

20060031720 - Host apparatus for sensing failure of external device connected through communication table and a method thereof: A host apparatus capable of sensing failure in an external device connected thereto through communication cable, comprises an external signal detector for sensing failure in the external device by detecting signals of the external device through the communication cable; a display for outputting a predetermined message; and a controller for...

20060031721 - Method and apparatus for system monitoring with reduced function cores: A method, apparatus, and computer instructions for monitoring a device in a data processing system. A register associated the device is accessed from a reduced function processor core through a connection between the register for the device and the reduced function processor core. The device is monitored using the value...

20060031722 - Apparatus, system, and method for active data verification in a storage system: An apparatus, system and method of verifying data are provided. Active data are identified among data on a storage device, records the location of the active data, and the integrity of the active data are verified. In one embodiment, data in segments adjacent to the active data segments are also...

20060031723 - Method and apparatus for a low-level console: A method, apparatus and computer instructions for interfacing with an operating system on a data processing system. Registers in a processor are allocated for use in providing a low-level console interface to a remote data processing system, wherein the registers are accessed by the remote data processing system using the...

20060031724 - Interleaving method and apparatus, de-interleaving method and apparatus, and interleaving/de-interleaving system and apparatus: An interleaving apparatus comprises a first storing unit for storing data to be transmitted and a first control unit for controlling the first storing unit so that the data to be transmitted is outputted from the first storing unit with the data to be transmitted arranged in a matrix and...

20060031725 - Algorithm pattern generator for testing a memory device and memory tester using the same: Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component...

20060031726 - Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address...

20060031728 - Method and apparatus for measuring digital timing paths by setting a scan mode of sequential storage elements: A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage elements, e.g., flip/flops, are coupled to combinational logic and are configured to have an additional port for receiving a scan mode signal....

20060031727 - Segmented algorithmic pattern generator: A segmented algorithmic pattern generator engine producing a test signal pattern made of vectors divided into fully definable segments. The engine allows defining processing controls to allow offsets of individual vectors relative to one another and defining additional pattern control formats. Also provided are reducing the pattern format depths in...

20060031729 - Apparatus with self-test circuit: An apparatus is adapted for self-test. The apparatus includes a microcontroller and a number of relay drivers having outputs electrically connected to form a single input for self-test monitoring. The microcontroller is electrically connected to each of the relay drivers and is adapted to energize each of the relay drivers...

20060031730 - Decision selection and associated learning for computing all solutions in automatic test pattern generation (atpg) and satisfiability: An all solutions automatic test pattern generation (ATPG) engine method uses a decision selection heuristic that makes use of the “connectivity of gates” in the circuit in order to obtain a compact solution-set. The “symmetry in search-states” is analyzed using a “Success-Driven Learning” technique which is extended to prune conflict...

20060031731 - Generating test patterns used in testing semiconductor integrated circuit: A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur...

20060031732 - Generating test patterns used in testing semiconductor integrated circuit: A test pattern sequence which is used to test a delay fault or an open fault which accompanies a delay occurring in an IC is easily and rapidly generated. A list of locations such as logic gates and signal lines within the circuit where a fault is likely to occur...

20060031733 - Power-saving retention mode: Embodiments of the invention are disclosed wherein methods and systems are provided for implementing a power-saving retention mode in an integrated circuit having both logic elements and memory elements. The methods of the invention include steps for scanning at least some of the logic elements of the integrated circuit and...

20060031734 - Irregularly structured, low density parity check codes: An error correction codeword. In one embodiment, an irregularly structured LDPC code ensemble possessing strong overall error performance and attractive storage requirements for a large set of codeword lengths. Embodiments of the invention can offer communication systems with better performance and lower terminal costs due to possible reductions in mandatory...

20060031735 - Method and circuit for correcting power amplifier distortion: An equalizing and error correcting section includes an equalizing section, an error processing sections, and a select section. The equalizing section outputs the received data subjected only to channel compensation and phase rotation compensation and the received data subjected not only to those compensations but also to power amplifier distortion...

20060031736 - Actuation circuit for a switch in a switch-mode converter for improving the response to sudden changes: The invention relates to an actuation circuit for a switch (SW) controlling the power consumption in a switch-mode converter which has input terminals (K1, K2) for applying an input voltage (Vin) and output terminals (K3, K4) for providing an output voltage. The actuation circuit (100) comprises a first input (K11)...

20060031737 - Method and apparatus for communications using improved turbo like codes: Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to...

20060031738 - Adaptative forward error control scheme: The invention applies to packet transmission networks. It proposes an adaptive forward error control scheme implemented at the application level, allowing to respect a maximum tolerated packet error rate. According to the invention, the amount of redundancy is adapted so as to offer a correction capability allowing to respect said...

20060031739 - Converting circuitforpreventing wrong errorcorrection codes from occurring due to an error correction rule duringdata reading operation: A converting circuit, for preventing wrong error correction code from occurring due to an error correction rule during data reading operation is provided. When the flash memory controller writes all 0×FF data into the flash memory, the byte error correction rule generates a set of correct error correction codes and...

20060031740 - Packet detection system and method: A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of the average correlation signal scaled by...

20060031741 - Error-correcting circuit for high density memory: This invention relates to a circuit technique for rapidly and efficiently correcting for read and write data errors in a digital semiconductor memory. More generally, this can also be in any type of digital memory or digital communication channel. As semiconductor memories get smaller and smaller, the memory cells are...

20060031742 - Decoding device and decoding method: Improper correction is avoided in decoding of an extended Reed-Solomon code. The decoding device includes: a syndrome computation section for computing input data syndromes from input data and corrected data syndromes from first corrected data obtained from the input data; an evaluator/locator polynomial deriving section for outputting coefficients at each...

20060031743 - Method and apparatus for a modified parity check: A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity...

20060031744 - Method and apparatus for encoding and decoding data: A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part...

20060031745 - Methods and apparatus for constructing low-density parity check (ldpc) matrix: Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix,...

20060026452 - Data duplication method in a disaster recovery system: A recovery of a secondary DB is executed by a log including a update difference of a primary DB, and a command is executed by adding the command to the log and analyzing the log by a secondary site. An operation command execution in the secondary site is applied to...

20060026451 - Managing a fault tolerant system: Systems and methods for managing a fault tolerant system are disclosed. In one implementation a system for managing a fault tolerant system comprises a configuration manager that receives configuration events from the fault tolerant system, a fault normalizer that receives fault events from the fault tolerant system; and a fault...

20060026453 - Method and system for managing electronic systems: The system and method of the present invention apply information filters (83A) hierarchically to information (14) such as, for example, alerts/events generated by an operational electronic system (10). Further, the system and method can display the results of the application of the information filters (83A) to information (14)....

20060026454 - Cache memory, processor, and production methods for cache memory and processor: A cache memory built in a processor comprising a plurality of independent memory blocks, pass/fail information memory unit memorizing a presence/absence of a failure occurring in each of the memory blocks, and a screening control function substituting a sound memory block for a failed memory block based on a memory...

20060026456 - Data storage apparatus and data storage method thereof: A data storage apparatus and data storage method thereof which enable reduction of the number of maintenance sessions to replace malfunctioning storage means are provided. The data storage apparatus has a plurality of data HDDs; a plurality of error correction HDDs; a data distribution and error code generation device, which...

20060026455 - Information storage medium, recording/reproducing apparatus and recording/reproducing method: A write once information storage medium having original data, replacement data, updated data and management information recorded thereon and an apparatus for and a method of recording and managing the data and the management information. The management information includes a defect address, a replacement address and state information for distinguishing...

20060026457 - Error correcting logic system: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the...

20060026459 - Method and apparatus for storing data: An apparatus for storing data received from other apparatus includes a first storage unit that stores the data received from the other apparatus; a second storage unit that stores the data stored in the first storage unit; a history storage unit that stores information on a storage history of the...

20060026458 - Storage device identification replication: A system and method implemented on a storage device comprising a controller. In one embodiment, a controller identifier of the storage device's controller is combined with a logical unit number (“LUN”) associated with data stored on the storage device to produce a first value. The embodiment further comprises receiving a...

20060026460 - Bit map write logging with write order preservation in support of asynchronous update of secondary storage: A method for maintaining a bit map of data writes, the method including associating each of a plurality of bit groups in a bit map with a different one of a plurality of segments of a data storage device, where each of the bit groups includes a plurality of bits,...

20060026461 - Information processing apparatus having command-retry verification function, and command retry method: A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops...

20060026462 - Apparatus for recovering bios in computer system: A basic input-output system (BIOS) online burning system comprises a burning machine (100), a BIOS online burning card (200), a motherboard (300) and a corrupted BIOS (380) attached on the motherboard. The BIOS online burning card is connected between the burning machine and the corrupted BIOS. The BIOS online burning...

20060026463 - Methods and systems for validating a system environment: Methods, systems, and machine-readable mediums are disclosed for validating a system environment for a software application. In one embodiment, an input file having a plurality of validation tests identifiers identifying validation tests to validate a system environment for an application is read. At least a portion of the validation tests...

20060026467 - Method and apparatus for automatically discovering of application errors as a predictive metric for the functional health of enterprise applications: A method and apparatus that uses application errors as a predictive metric for overall measuring of applications functional health are disclosed. The automated system intercepts messages exchanged between inter-services of enterprise applications, analyzes the context of those messages, and automatically derives application errors embedded in the message. Thereafter, it is...

20060026464 - Method and apparatus for testing software: A method, apparatus, and computer instructions for testing software. A set of questions regarding the application is presented, wherein the set of questions are selected from a database. In response to receiving a user input to the set of questions, the application is tested to form identified testing. In response...

20060026466 - Support methodology for diagnostic patterns: A method of providing diagnostic patterns for customer support, comprising identifying a recurring problem type, obtaining a diagnostic pattern to diagnose the recurring problem type where a solution of the recurring problem type is converted into a series of one or more steps taken in solving the recurring problem type,...

20060026465 - Test harness benchmark file: A test harness that comprises one or more tests for a program in one example is executed. An output from the test harness is received. The output comprises one or more respective test results for the one or more tests. A verification that the one or more respective test results...

20060026468 - Crossbar switch debugging: A crossbar switch having a plurality of ports that allows a debug process to be performed on the switch using one of the plurality of ports to output chip status information. The switch uses a debug block to store chip status information....

20060026469 - Branch prediction device, control method thereof and information processing device: The present invention is a branch prediction device comprising a branch history storage device for storing branch history information in order to predict branch behavior, an error detection mechanism for detecting the reading error of the branch history information, and an erasure mechanism for erasing the storage region of the...

20060026471 - Loop status monitoring apparatus: A loop status monitoring apparatus monitors a status of an arbitration loop that includes a plurality of devices and a switch that controls connections between the devices, has at least one of loop status detection data, primitive detection data, and frame count data, and includes a failure detecting unit that...

20060026470 - Processor debugging apparatus and processor debugging method: A processor debugging apparatus that scans and reads a latch in a processor includes a register that stores a value of a predetermined signal in the processor for a plurality of clocks; and a signal reading unit that scans and reads out a signal value stored in the register....

20060026472 - Designing scan chains with specific parameter sensitivities to identify process defects: A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process...

20060026473 - Inversion of scan clock for scan cells: In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A...

20060026474 - System and program product for displaying error handling information: When an emission pattern of LEDs of an operation panel of a printer is merely pseudo-displayed on display portions of a local computer and a server computer, a piece of error handling information corresponding to a pseudo pattern of the emission pattern can be acquired. Accordingly, a user can easily...

20060026476 - Integrated circuit device and testing device: An integrated circuit device performs a delay test using scan path technique, including a pulse generator circuit generating a delay test clock pulse of a number according to an input pulse number control signal; and a scan path test circuit tested with the delay test clock pulse....

20060026475 - Semiconductor circuit device and a system for testing a semiconductor apparatus: Methods and apparatus for testing a semiconductor device. A testing interface is configured to interface with an external test apparatus and a device under test (DUT). In one embodiment, the testing interface receives test data and a test clock signal from the external test apparatus. The test data is clocked...

20060026477 - Test clock generating apparatus: A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the...

20060026478 - Built-in self-test emulator: Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST...

20060026480 - Method and apparatus for generating test signals: s

20060026479 - Verification vector creating method, and electronic circuit verifying method using the former method: To realize an equivalence verification between an analog circuit and its function model unit. From a circuit topology and a functional description, there is extracted contained in the circuit. A test circuit capable of inputting a verification vector according to the extracted circuit function is created, and a verification is...

20060026481 - System and method for testing electronic device performance: A system for testing electronic device performance includes a test device and at least one target device coupled to the test. The test device determines when at least one test command is incompatible with the at least one target device and modifies the at least one incompatible test command such...

20060026482 - Test apparatus: An inventive test apparatus has a pattern generator for generating an address signal and a test signal to be fed to a device-under-test and an expected value signal to be outputted from the device-under-test to which the test signal has been fed, a logical comparator for comparing an output value...

20060026483 - Error correction compensating ones or zeros string suppression: An error correction compensating ones or zeros string suppression system and method for use in a digital transmission system is herein disclosed. In digital transmission systems utilizing error control coding (ECC)/forward error correction (FEC) to reduce the number of bit errors in a bit stream, long strings of ones and...

20060026484 - System and method for interleaving data in a communication device: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. In addition to the memory, the system includes a write module and a read module, each of which is coupled to the memory. The...

20060026485 - Turbo decoder, turbo decoding method, and turbo decoding program: A sliding window turbo decoder is provided which is capable of reducing large amounts of arithmetic calculations required for decoding and of achieving decoding processing that can reduce power consumption. An input code block is divided into a plurality of windows on which forward and backward processing is performed to...

20060026488 - Apparatus and method for channel coding in mobile communication system: Disclosed are an apparatus and a method for reducing the coding complexity in an LDPC code used in a digital communication system. In the method, parameters required for coding are determined according to a coding rate and a code length, a seed matrix is generated according to values of the...

20060026486 - Memory efficient ldpc decoding methods and apparatus: Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to...

20060026487 - Transport stream processing apparatus: A transport stream processing apparatus according to the present invention is a transport stream processing apparatus including a plurality of processing steps for separating desired data from a transport stream, and comprises a hardware transport stream separating device, a software transport stream separating device, and a processing switching device for...

20060026489 - Nonvolatile memory and nonvolatile memory apparatus: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile...

20060026490 - Outer loop power control with transport block diversity transmission: The invention proposes a method for controlling a variable of transmission between a mobile network element and a fixed network element, wherein the transmission is effected by repeatedly sending of data units, and a control of the variable of the transmission based on a target data unit error rate is...

20060026491 - Rate control for packet-based wireless communication: The present invention provides a method and system for controlling the data rate in packet based wireless communications. Then, using the probability of error, the invention calculates the throughput and drop probability for two or more data rates and selects the data rate with highest throughput. In one embodiment of...

20060026492 - Method and apparatus for managing a deinterleaving buffer in a mobile communication system using block interleaving: A method and apparatus are provided for managing a buffer that can reduce a buffer size and a number of buffers required for a receiving stage of a mobile communication system using block interleaving. In a deinterleaving buffer configured as a plurality of sub-buffers in a receiving stage of a...

20060026493 - Method and apparatus for reliable resynchronization of sequential decoders: A system and method for the resynchronization of a sequential decoder that decodes received signal samples stored within an input buffer is disclosed. The system comprises two auxiliary decoders coupled to the sequential decoder for running a simplified MAP decoding process when the input buffer reaches a threshold saturation level....

20060026494 - Modified soft output viterbi algorithm for truncated trellis: A method, system and computer program product for obtaining the reliability values for the hard decisions obtained by a Viterbi equalizer in a wireless communication system. A difference parameter is obtained for each Viterbi state at a stage while advancing the Viterbi trellis by the stage. The difference parameter for...