Error detection/correction and fault detection/recovery inventions 01/06

20060020846 - Mechanism for enabling enhanced fibre channel error recovery across redundant paths using scsi level commands: Systems and methods for performing error recovery in a system utilizing redundant communication links. In one embodiment, a host device is coupled to a sequential device such as a tape drive by a pair of Fibre Channel links. The host is configured to associate an identifier with each command. Upon...

20060020844 - Recovery of custom bios settings: Embodiments of the invention are directed to recovering custom BIOS settings in a computer having a system ROM, a first non-volatile memory and a second non-volatile memory, comprising: storing custom default BIOS settings in the first memory, wherein custom default BIOS settings comprise at least the custom BIOS settings; and...

20060020845 - Unattended bios recovery: In accordance with one embodiment of the present invention, a method for recovering a BIOS in a computer is described, comprising: unattendingly loading a BIOS recovery code image into system ROM stored on a bootable device; and unattendingly rebooting the computer....

20060020847 - Method for performing services in a telecommunication network, and telecommunication network and network nodes for this: The invention relates to a method for performing a service or application in a network environment with network elements, which network environment contains a telecommunication network that has at least two network nodes for performing services or applications, all these nodes being equipped with a common layer for service support,...

20060020848 - Systems and methods for out-of-band booting of a computer: The present invention is directed to systems and methods for remotely booting a server computer system. A boot request is received from the server computer. An access request is transmitted to a boot management system via a secondary communication channel in response to the received boot request. An access response...

20060020849 - Method of restoring source data of hard disk drive and method of reading system information thereof: A method of restoring source data if the source data written in a system region of a hard disk drive and mirror data, which is a copy of the source data, are both damaged, in which the source data is read on a sector basis and error-free sectors and error-generated...

20060020851 - Information processing apparatus and error detecting method: An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error...

20060020850 - Latent error detection: In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is compared to detect a latent processing error in a first...

20060020852 - Method and system of servicing asynchronous interrupts in multiple processors executing a user program: A method and system of servicing asynchronous interrupts in multiple processors executing a user program. Some of the exemplary embodiments may be a method comprising executing a user program on a first processor and a duplicate copy of the user program on a second processor, receiving an asynchronous interrupt by...

20060020854 - Method and apparatus for high-speed network adapter failover: A method, apparatus, and computer instructions for facilitating failover between network adapters. A failure of a first network adapter is detected in a device driver layer. In response to detecting the failure, the transmission of data is changed by the device driver layer to a second network adapter....

20060020853 - Switchover facilitation apparatus and method: Upon detecting (62) a degraded operational state, an active service unit can transmit a message (63) to a stand-by service unit. The latter can then prepare to replace (64) the active service unit and indicate its readiness with a corresponding message (65) to the active service unit. The latter can...

20060020855 - Storage device and storage device power consumption control method: According to the present invention, in cases where a CHA function and a DKA function are mounted within a single package, a battery power supply that is used during the occurrence of power supply trouble is effectively utilized so that the supply of power can be separately controlled for each...

20060020856 - Computer diagnostic interface: According to one aspect of the present invention, there is provided a method for providing diagnostic indications representing detected failure conditions in a computer system, comprising: generating at least one indicator light waveform to present a predetermined quantity of one or more sequential illuminations of at least one indicator light;...

20060020857 - Disable/enable control for laser driver eye safety: A circuit for disabling an energy-generating component. The circuit comprises an input operable to receive a disable signal and a disable circuit operable to disable the component in response to the disable signal for a predetermined duration of time sufficient to maintain an average power generated by the component at...

20060020858 - Method and system for minimizing loss in a computer application: During the execution of a software application, a user will often create significant data representing the work they are trying to accomplish. Additionally, the act of using the application will create states within that program reflecting the operations performed during use. In many scenarios, this data can be lost through...

20060020859 - Method and apparatus for providing intelligent error messaging: A method and apparatus for providing intelligent error messaging is disclosed wherein a user of a mobile communications device is provided with descriptive error messaging information to assist the user in overcoming errors associated with the processing of electronic messages and data. For example, when the mobile device is being...

20060020860 - Digital signature generation for hardware functional test: A Multiple Input Shift Register (MISR) is used to generate signatures, based on data from a device under test, in order to validate the proper sequence and content of the data over a defined period of time. The MISR described herein includes the ability to “tag” the signatures for each...

20060020861 - Method, system, and apparatus for loopback entry and exit: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback...

20060020862 - Apparatus for generating deterministic test pattern using phase shifter: An apparatus for generating a deterministic test pattern is provided for a BIST having a scan chain, comprising the control bits storing devise for storing the number of a deterministic test pattern that is covered by a tap configuration; pattern counter devise for receiving the values stored in the control...

20060020864 - Method and system for blocking data in scan registers from being shifted out of a device: Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said...

20060020863 - Scanning latches using selecting array: A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By...

20060020865 - Automatic analog test & compensation with built-in pattern generator & analyzer: A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone...

20060020866 - System and method for monitoring performance of network infrastructure and applications by automatically identifying system variables or components constructed from such variables that dominate variance of performance: Systems, methods and computer program products for monitoring performance of network infrastructure and applications by automatically identifying system variables or combinations constructed from such variables that dominate variance of system performance. A method, system and computer program monitors performance of executing software applications and execution infrastructure components to detect deviations...

20060020867 - Method for automated at-speed testing of high serial pin count multiple gigabit per second devices: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path...

20060020869 - Decoding block codes: This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder (910) receiving a length n soft input vector, creating a binary vector...

20060020870 - Layered decoding of low density parity check (pdpc) codes: A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix....

20060020868 - Ldpc decoding methods and apparatus: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code...

20060020871 - Communications device and wireless communications system: A turbo coding device and turbo decoding device that allow for the presence of interleaving in the error correction coding process improves error correction capability even when the decoding device does not employ a scheme whereby extrinsic information is circulated as in a turbo decoding device. A turbo decoding device...

20060020872 - Ldpc encoding methods and apparatus: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure...

20060020873 - Error correction code generation method and apparatus: A method and apparatus for generating an error correction code used in communicating over a channel, includes generating a set of candidate circulant blocks corresponding to a parity check matrix and a Hamming code wherein the Hamming code is initially unable to detect a predetermined error pattern without ambiguity due...

20060020874 - Decoder performance for block product codes: This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. A method of improving block turbo decoder performance that comprises receiving soft input information corresponding to a first set of constituent codes of a block product code (900), scaling soft...

20060020875 - Multi-rate viterbi decoder: A method and system for decoding a data symbol sequence that has been previously encoded using one or more unique code word polynomials in which at least one unique code word polynomial is used more than once. A set of 2d-1 unique branch metrics is computed, using the unique code...

20060020876 - Method for simplifying a viterbi decoder and a simplified viterbi decoder using the same: A method for simplifying a Viterbi decoder includes receiving a partial response, and determining an amount of redundant selector modules according to a tap number of the partial response; analyzing an output signal of the redundant selector modules for determining an initial input signal; and taking Viterbi decoding process to...

20060020877 - Method and apparatus for pipelined joint equalization and decoding for gigabit communications: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions...

20060015765 - Method for synchronizing a distributed system: The invention relates to a method for synchronizing components of a distributed system. The system status is represented by at least one object which is provided in all components. A change of the status of the object in one of the components is signalled to all other components by means...

20060015763 - Real-time web sharing system: The customer presses the Connect button (2240) on the customer terminal (1230). By this, a connection request to an operator terminal is notified to an operator terminal (1210) via the push sharing server (2100). On receiving this notification, the operator terminal (1210) changes the Respond button (2310) to the Incoming...

20060015764 - Transparent service provider: A service appliance is installed between production servers running service applications and service users. The production servers and their service applications provide services to the service users. The service appliance replicates the service data of service applications and monitors the service application. If the service appliance detects that the service...

20060015766 - Method and device for managing defective storage units on a record carrier: The present invention relates to a method and a corresponding device for managing defective storage units on a record carrier, in particular on a rewritable optical record carrier. To avoid synchronization errors of a drive when accessing storage units located before or after a defective storage unit, it is proposed...

20060015770 - Method and system for a failover procedure with a storage system: A method includes receiving a first command for accessing a tape storage system, the first command containing an indicator that the first command was issued as a result of a failover from a first path to the storage system to a second path to the tape storage system. The method...

20060015768 - Method, system, and apparatus for tracking defective cache lines: To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information regarding defective cache lines....

20060015769 - Program, method and apparatus for disk array control: When receiving a notification of an error detected by patrol processing of the device adaptor for a secondary disk apparatus, a first recovery processing unit reads out data corresponding to the error location from a normal primary disk apparatus and writes the data into the error disk apparatus to eliminate...

20060015767 - Reducing data loss and unavailability by integrating multiple levels of a storage hierarchy: A method for reducing data loss and unavailability by integrating multiple levels of a storage hierarchy is provided. The method includes receiving a read request. In addition, the method includes recognizing a data failure in response to the read request. The method further includes locating an alternate source of the...

20060015771 - Management method for spare disk drives a raid system: A RAID system employs a storage controller, a primary storage array having a plurality of primary storage units, and a spare storage pool having one or more spare storage units. A method of operating the storage controller in managing the primary storage array and the spare storage pool involves a...

20060015772 - Reconfigurable memory system: A reconfigurable memory system includes processors and memory modules. A reconfiguration system is operable to reconfigure the memory system into multiple configurations. In each configuration, one or more memory modules are provisioned for each processor....

20060015773 - System and method for failure recovery and load balancing in a cluster network: A system and method for failure recovery in a cluster network is disclosed in which each application of each node of the cluster network is assigned a preferred failover node. The dynamic selection of a preferred failover node for each application is made on the basis of the processor and...

20060015774 - System and method for transmitting data in storage controllers: A method and system for transferring frames from a storage device to a host system via a controller is provided. The method includes transferring frames from a transport module to a link module; and sending an acknowledgment to the transport module, wherein the link module sends the acknowledgement to the...

20060015776 - Built-in computer power-on memory test method: A built-in computer power-on memory test method, wherein a memory test program is built into the BIOS unit of the motherboard, immediately displays a menu on the screen at computer power-on, with the menu showing at least the commands of “Press DEL to enter SETUP” and “Press CTRL to Memory...

20060015775 - System and method for observing the behavior of an integrated circuit (ic): A system and method for observing the functional behavior of a target circuit. In one embodiment, a first interface, which is external with respect to the target circuit, is provided for generating behavioral definitions relative to the target circuit. A programmer module is used, responsive to the behavioral definitions, for...

20060015777 - System and method for fault code driven maintenance system: A system, program instructions or method for maintaining a deployed product having at least one component, as well as training of the maintenance workers, is provided. The system has a microserver, a sensor and an electronic device. The microserver is integral with the deployed product. The sensor is in communication...

20060015778 - Emission-monitoring system and method for transferring data: A system and a method for transferring data in an emission-monitoring system from a first computer to a second computer are provided. The method includes generating a first message containing a first software variable having a first site-specific value that is transmitted from the first computer to the second computer....

20060015779 - Involving a secondary storage system in a data transfer decision: Provides methods, systems and apparatus for data storage including running an asynchronous replication process to copy successive sets of stored data from a primary storage system to a secondary storage system, and receiving at the primary storage system from the secondary storage system an indication of space available for receipt...

20060015780 - Specifying data timeliness requirement and trap enabling on instruction operands of a processor: A computer has its programs in instructions and operand descriptors to specify the operands of the instructions. Apparatus for specifying data timeliness requirements of individual pieces of data pointed by the instruction operands is described hereby. The data timeliness requirements range from the local memory (the memory in the computing...

20060015781 - Share resources and increase reliability in a server environment: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The...

20060015782 - System and method for transparent electronic data transfer using error correction to facilitate bandwidth-efficient data recovery: The invention disclosed herein includes a system and method for electronically transferring data through a communications connection in a transparent manner such that the data transfer does not interfere with other traffic sharing the connection. The invention transfers data using bandwidth of the connection that other traffic are not using....

20060015783 - Data transmission apparatus and method: A data transmission apparatus comprises an estimation device to estimate a transmission condition of the transmission channel in the transmitter based on at least Jitter information or a packet loss rate obtained from the receiver, and a controller to change at least one of a bit rate of transmission data...

20060015784 - System and method for write-enable bypass testing in an electronic circuit: A system and method for write-enable bypass testing in an electronic circuit. According to one embodiment, the integrated circuit that includes a memory block having at least one input and at least one output. At least one input is associated with a block of input logic and at least one...

20060015786 - System and shadow bistable circuits coupled to output joining circuit: In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable...

20060015785 - Test apparatus for mixed-signal semiconductor device: A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture including a connection means, an option circuit for...

20060015787 - Externally-loaded weighted random test pattern compression: The present invention is directed to a logic testing architecture with an improved decompression engine and a method of decompressing scan chains for testing logic circuits....

20060015788 - Semiconductor device: A logic chip and a memory chip to be accessed by the logic chip are mounted in a single package. A pattern generator of the logic chip operates during a first test mode to generate internal test pattern(s) for the memory chip. A pattern selector selects, during the first test...

20060015789 - Apparatus and method for encoding/decoding using concatenated zigzag code in mobile communication system: Disclosed is a method for channel coding in a mobile communication system, which includes dividing information bits of length N into M sub-information bits according to a preset value; interleaving the M sub-information bits through corresponding interleavers corresponding to the M sub-information bits, respectively; and coding the interleaved sub-information bits...

20060015790 - Low overhead coding techniques: A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a first value of a first symbol in the encoded...

20060015791 - Decoding method, decoding device, program, recording/reproduction device and method, and reproduction device and method: The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing,...

20060015792 - Method for encoding signals, related system and program product: A system for encoding digital signals for transmission over a channel by allocating redundant channel encoding bits, includes at least one encoder configured for: subjecting the digital signals to multiple description coding to produce therefrom multiple description encoded signals, and allocating at least part of the redundant channel encoding bits...

20060015793 - Method of combining multilevel memory cells for an error correction scheme: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain...

20060015794 - Error correction method in digital data storage device: A data error-detecting method for detecting errors before C1 decoding procedure is provided. First, a bit modulation is performed for modulating data channel bits obtained from an optical disk into 8-bit data. When the data channel bits is determined to introduce a legal mapping, an erasure bit having a first...

20060015795 - Audio data processor: An audio data processor includes a packet receiver for receiving audio data packets and a coded data extractor for extracting coded data from the received packets. When an error detector detects a receiving error of a packet in the packet receiver, a data interpolator generates interpolation coded data on the...

20060015796 - Method and device for building a variable-length error code:

20060015797 - Information reproducing method and information recording reproducing apparatus with maximum likelihood decoding: To provide a regenerative signal evaluation method in which the transition of polarity of a regenerative signal, or the change of polarity in a record mark sequence, is dealt with employing an index in correlation with an error ratio of binarization result by a maximum likelihood decoding. The method comprises...

20060015800 - Method for determining output signals of a viterbi decoder: A method for determining output signals of a Viterbi decoder. The method includes: (a) receiving a plurality of digital signals through a path memory module of the Viterbi decoder with decoding an input signal; (b) comparing the received digital signals in step (a) with a default number; and (c) determining...

20060015799 - Proxy-based error tracking for real-time video transmission in mobile environments: This invention provides an efficient method of error tracking which quickly recovers the error packet of data. A side information is sent along with a normal video stream that can be used by an intermediate network node in order to improve the quality of the video transmission. The intermediate node...

20060015798 - Viterbi bit detection method and device: The present invention relates to a Viterbi bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier along an N-dimensional channel tube, N being at least two, of at least two bit rows one-dimensionally evolving along a first direction and...

20060015801 - Method for encoding and decoding error correction block: The present invention relates to a method for encoding and decoding an error correction block, and more particularly to a method for encoding and decoding an error correction block useful for a high-density optical disc. When an error correction block is encoded, a user data block is generated and parity...

20060015802 - Layered decoding approach for low density parity check (ldpc) codes: A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups...

20060010335 - Method and apparatus for reconfigurable memory: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical...

20060010338 - Cascading failover of a data management application for shared disk file systems in loosely coupled node clusters: Disclosed is a mechanism for handling failover of a data management application for a shared disk file system in a distributed computing environment having a cluster of loosely coupled nodes which provide services. According to the mechanism, certain nodes of the cluster are defined as failover candidate nodes. Configuration information...

20060010336 - Connection apparatus and method for network testers and analysers: Connection apparatus for a network tester or analyser comprises at least two network connection devices for connecting the apparatus to a network and at least two solid state switches. Each connection device is constructed and arranged to output serial electrical signals corresponding to signals received from a network to which...

20060010337 - Management system and management method: A management system comprises an event monitoring unit configured to detect an event, a dependency extracting unit configured to extract a dependency regarding the event, a storage unit in which the event and the dependency are stored, an updating unit configured to update the event and the dependency stored in...

20060010339 - Memory system and method having selective ecc during low power refresh: A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching the DRAM to the low...

20060010340 - Protection of non-volatile memory component against data corruption due to physical shock: This invention provides a method to operate a terminal (100), as well as a terminal that operates in accordance with the method. The method includes, in response to initiating a data write operation with a non-volatile memory device (132), activating a sensor (190) that is capable of detecting that the...

20060010341 - Method and apparatus for disk array based i/o routing and multi-layered external storage linkage: A system and method for linking external storage systems that includes creating a virtual volume mapping at one or more storage systems. Each virtual volume mapping at each storage system associating a virtual storage volume with a physical storage volume and/or one second virtual storage volume at one or more...

20060010343 - Data reconstruction method and system wherein timing of data of data reconstruction is controlled in accordance with conditions when a failure occurs: A data storage system connectable to a host unit which issues data read/write requests to the data storage system, and which includes a plurality of disc units, and a controller connected to the disc units. A fault can occur in any of the disc units. The disc units store data...

20060010342 - Information processing method capable of detecting redundant circuits and displaying redundant circuits in the circuit design process: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information...

20060010344 - System and method for predictive processor failure recovery: A system, method, and computer program product for reporting and recovering from an internal processor error in a multiprocessor system supporting system management mode. In accordance with the method of the present invention one or more replacement agents are allocated such as during system startup within the multiprocessor system. Machine...

20060010345 - System and method for providing installation support to a user: A system and method are disclosed for providing installation support to a user of a computer system. A method incorporating teachings of the present disclosure may include launching an installation tool in connection with installation of a peripheral driver. The tool may have capabilities that include, for example, capturing an...

20060010346 - Detection mechanism: According to one embodiment an apparatus is disclosed. The computer apparatus includes a first integrated circuit (IC) and a second IC. The second IC includes a soft error rate (SER) immune component and a SER component to detect radiation that could result in soft errors at logic at the first...

20060010347 - Hard disk recording apparatus: A hard disk recording apparatus including: a receiving unit for receiving programs; a reservation data receiving unit for accepting input of reservation recording data including reservation recording starting time; a reservation data storing unit for storing the reservation recording data; a recording unit for recording the programs on a hard...

20060010348 - Method and apparatus for capture and formalization of system requirements and their transformation to test instructions: A method for capturing requirements on a system and subsequently transforming the requirements into a test instruction for the system is disclosed. In a exemplary embodiment, a set of flows that captures the requirements of the system are created by repeatedly combining predefined templates of natural language text and populating...

20060010349 - Systems and methods for analyzing bus data: A protocol analyzer monitors a bus while a software module causes a trace packet to be generated and sent out on the bus to an invalid address. The trace packet triggers the protocol analyzer and permits the bus data flowing on the bus when the software module detected a problem...

20060010350 - Memory having variable refresh control and method therefor: A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining...

20060010351 - Controller capable of self-monitoring, redundant storage system having the same, and method thereof: A controller capable of self-monitoring, a redundant storage system having the same, and its method are proposed. Each controller is arranged with a self-monitoring operating circuit and a watchdog unit. The self-monitoring operating circuit can periodically issue a confirmation signal to the watchdog unit. The watchdog unit comprises a counter...

20060010352 - System and method to detect errors and predict potential failures: A system is disclosed that includes a component, a fault table configured to receive fault information associated with the component, and a diagnosis processor configured to read the fault information from the fault table and initiate corrective action as a function of the fault information. A method for handling faults...

20060010353 - Systems, methods, and media for controlling temperature in a computer system: Systems, methods and media for controlling temperature of a system are disclosed. More particularly, hardware, software and/or firmware for controlling the temperature of a computer system are disclosed. Embodiments may include receiving component temperatures for a group of components and selecting a component to perform an activity based at least...

20060010354 - Self-healing cache system: A method, apparatus and program storage device for performing a self-healing cache process is described. At least one error affecting a cache is detected. The cache may have a matching address tag for a fetching operation. Based on the type of error, a self-healing cache process is performed based....

20060010356 - Event-driven portable data bus message logger: A event-driven portable data bus message logger includes an event message receiver for receiving an event message including an event field, an event message storage operably connected to the event message receiver for storing the event message, a data bus message receiver for receiving data bus messages including a data...

20060010355 - Isolation of input/output adapter error domains: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data...

20060010357 - Method for monitoring data processing system availability: A method for monitoring the availability of a data processing system is proposed. For example, the system runs a management application (205,240), which involves the periodic transmission of blocks of data from multiple local computers (105) to a central computer (110). In the method of the invention, whenever a block...

20060010358 - Method and apparatus for calibrating and/or deskewing communications channels: A series of pulses may be driven down each drive channel, which creates a series of composite pulses at the output of the buffer. Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted until...

20060010359 - Method for testing electronic circuit units and test apparatus: The invention provides a test apparatus for testing an electronic circuit unit to be tested. The test apparatus comprises a read-only memory for buffer-storing a test data stream read from the circuit unit to be tested in a manner dependent on a clock signal. The test apparatus further comprises a...

20060010360 - Semiconductor testing apparatus and method of testing semiconductor: A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test...

20060010361 - Method and apparatus of compensating for signal receiving error at receiver in packet-based communication system: A method and an apparatus of compensating for a signal receiving error at a receiver in a packet-based communication system. In the invention, frequency offset estimation and DC offset estimation obtained in a current packet are re-used in a next packet if the receiver is an intended recipient of the...

20060010362 - Method of finding a last state in tail-biting for turbo encoder and apparatus using the same: Encoding inputs corresponding to a set of powers of state matrix is added. Powers of state matrix have period T. The set of the powers of the state matrix has an identical state matrix value. One of the powers of the state matrix is multiplied by input matrix and the...

20060010364 - Information recording medium on which sector data generated from ecc block is recorded, information recording apparatus for recording sector data, and information reproduction apparatus for reproducing sector data: An information recording medium includes a management area where management information is recorded and a plurality of physical sector areas used to record a plurality of physical sector data blocks, which are generated by combining some data contained in a plurality of ECC blocks....

20060010363 - Method and system for correcting low latency errors in read and write non volatile memories, particularly of the flash type: A method for correcting errors in multilevel memories, both of the NAND and of the NOR type provides the use of a BCH correction code made parallel by means of a coding and decoding architecture allowing the latency limits of prior art sequential solutions to be overcome. The method provides...

20060005062 - Buffer and method of diagnosing buffer failure: A buffer includes an input unit that inputs data; an output unit that outputs the data; a plurality of registers that stores the data while sequentially shifting the data from the input unit to the output unit; an output-data selecting unit that selects desired data from among the data stored...

20060005061 - Data protection system: A method according to one embodiment may include assigning a tag to at least one transactions in which at least one data frame is at least one of transmitted or received by at least one functional block. The method may also include discovering, by a functional block, if an error...

20060005063 - Error handling for a service oriented architecture: A system, method and media for a service oriented architecture. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects and objects of the invention can be obtained from a review of the specification, the figures and the claims....

20060005064 - Systems and methods for facilitating computer system recovery: In one embodiment, a system and a method for facilitating computer system recovery includes identifying a desired delivery mechanism for performing a recovery, adapting a disk image for use with a particular type of recovery medium if a user communicated a desire to use that recovery medium, and writing the...

20060005066 - Mechanism for improving accessibility of jmx monitoring information in web content: System, method and computer program product for monitoring the status of components in a data processing system that improves the accessibility of JMX monitoring information in web content. The system includes a mechanism for acquiring a text representation of component status for display as ALT and TITLE content associated with...

20060005065 - Network analyzer, network analyzing method, automatic corrector, correcting method, program, and recording medium: The error of a measurement system can be corrected even if the frequency of an input signal of a device under test is different from that of the output signal. A signal output acquiring section acquires the power of the input signal by means of a power meter not shown...

20060005067 - Systems, devices, and methods for generating and processing application test data: Certain exemplary embodiments comprise a data generator system and method that comprises generating an executable procedure from a template comprising a structure. The system and method comprises processing the executable procedure to generate a plurality of data items. The system and method comprises automatically outputting the plurality of data items...

20060005071 - Automatic storage unit in smart home: A method, system, and device for computer control of access to a storage unit. The computer monitors the physical environment inside the storage unit, assists in placing and retrieving desired articles of clothing, and provides a method of visualizing possible ensembles without the need to physically pull out the individual...

20060005073 - Data integrity checking in data storage devices: A method for operating a data storage device having a data storage medium partitioned into blocks comprises. A binary value is assigned to each block, with the initial setting of each binary value to a first level. Subsequently the binary value assigned to each block into which data is written...

20060005068 - Error correction extending over multiple sectors of data storage: A method and an apparatus for storing a superblock of data codewords. The method includes providing sectorwise error correction codes in the data codewords. The method also includes generating superblock error correction codes as functions of the data codewords. The method includes storing the data codewords and the superblock error...

20060005070 - Method and apparatus for performing disk diagnostics and repairs on remote clients: Method and apparatus for performing disk diagnostics and repairs on remote clients. The method employs an embedded LAN microcontroller at a client to submit diagnostic commands to disk drives hosted by the client. Corresponding diagnostic data is returned from the disk to the LAN microcontroller, and an XML file containing...

20060005069 - Method and system for increasing data storage reliability and efficiency via compression: A method and a system is provided for increasing reliability of data stored in storage segments by increasing redundancy data and by permitting user data to fit around defective locations in the storage segment. User data is compressed and reserved for a portion of a storage segment having a data...

20060005072 - Method and system of verifying proper execution of a secure mode entry sequence: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode...

20060005074 - Remote data mirroring: Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary...

20060005075 - Fault tolerance system and method for multiple failed disks in a disk array: A fault tolerance system for multiple failed disks in a disk array includes: a disk array (3), a processor (1), and an exclusive-or (XOR) unit (2). The disk array includes a plurality of disks (30), each of which is logically divided into multiple blocks. The blocks includes: a plurality of...

20060005076 - Methods and systems for implementing shared disk array management functions: Multiple Array Management Functions (AMFs) are connected to multiple redundancy groups over a storage area network (SAN), such as a fiber-channel based SAN. The multiple AMFs share management responsibility of the redundancy groups, each of which typically includes multiple resources spread over multiple disks. The AMFs provide concurrent access to...

20060005077 - Simulating a sensing system: A simulator for simulating a sensing system includes modules operable to simulate sensors sensing a scene. The modules include: a path modeling module operable to model a path for each sensor; a radiative transfer module operable to model a transfer of radiance from the scene to each sensor; and instrument...

20060005080 - Event logging and analysis in a software system: Method and apparatus for logging and analyzing event flows associated with execution of a service request in a software system, such as a computer-based system comprising a multi-disc data storage array. Execution of the service request results in a plurality of events carried out by multiple layers of the software...

20060005079 - Methods and apparatus for translating application tests for execution with simulation software tools: A method for assessing computer system conformance with at least one requirement is provided. A first encoding of software commands is translated into a second encoding of software commands for use with a test-automation tool. The second encoding of software commands is processed to simulate at least one user interaction...

20060005078 - System and method of identifying the source of a failure: The present invention is generally directed to improving the stability of computing devices by identifying plug-in modules and other programs that cause failures. More specifically, the present invention provides a method that traces program execution from an instruction that ultimately generated a failure to a code library that caused the...

20060005081 - System and method for fault detection and recovery in a medical imaging system: A system and method for fault detection and recovery in a medical imaging system are provided. The method includes monitoring operations of a plurality of subsystems of the medical imaging system and determining if an error has occurred in a subsystem based on the monitoring. The method further includes identifying...

20060005082 - Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by...

20060005083 - Performance count tracing: The present invention provides for the hardware on-chip capturing and storage of performance count data about software programs running on the chip. Counters generate performance data about the programs, and the values of the counters are stored in a trace array. In an embodiment, instruction addresses and other data can...

20060005085 - Platform for computer process monitoring: Monitoring components that provide monitors for computer processes are disclosed, including a monitoring component that provides multiple monitors that may be selectively activated for a particular process where each monitor is responsive to a different type of event that signifies a defect. The monitoring component provides monitors including a debugger...

20060005084 - Support for nested faults in a virtual machine environment: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with...

20060005086 - Systems and methods for providing for degradation of a computer application: A method for providing for the graceful degradation of the performance and functionality of a distributed computer application. A plurality of sensors monitor the performance and availability of various external resources and/or services required by the application, as well as the performance of various components of the application, and report...

20060005087 - System and method for built-in testing of a gps receiver: Built-in test equipment (BITE) incorporated in a GPS receiver for providing a loop forward test. The loop forward test capability may be combined with a loop backward capability to provide a comprehensive built-in test (BIT) capability for the signal path in a GPS receiver. A code generator generates deterministic test...

20060005089 - Device and a process for the calibration of a semiconductor component test system, in particular of a probe card and/or of a semiconductor component test apparatus: A device and a process for the calibration of a semi-conductor component test system The invention relates to a process and a device for the calibration of a probe card and/or of a semi-conductor component test apparatus, including a first connection, at which a corresponding signal, in particular a calibration...

20060005088 - System and method for testing artificial memory: A system for testing an artificial memory includes a monitor (10), a driver (20), and an executing means (30). The monitor includes a command line interface (101) for inputting commands and parameters. The driver includes a command line editor (201), which is adapted to be activated before the command line...

20060005090 - Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods: A programmable logic device (PLD) includes a compare-select circuitry. The compare-select circuitry includes logic elements 1 through N. Each logic element comprises a compare circuitry and a selector circuitry. The compare circuitry compares two inputs of the logic element and generates a compare output signal of the logic element. The...

20060005091 - Error detecting circuit: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal...

20060005092 - Cache based physical layer self test: A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine...

20060005093 - Comparator for circuit testing: There is provided a test circuit comprising a test signal input for receiving a test signal, a hysteretic comparator having first and second comparison inputs and an output indicating the result of the comparison, and a delay circuit. The first comparison input is connected to the test signal input and...

20060005095 - Semiconductor integrated circuit and memory test method: The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the...

20060005094 - Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus: A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured...

20060005096 - Scan stream sequencing for testing integrated circuits: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan...

20060005097 - Information processing apparatus, information processing method, and computer program: An information processing apparatus includes a first information processor, a plurality of second information processor, and a plurality of temperature detecting units detecting temperature in the vicinity of each of the plurality of second information processors. The first information processor includes an application program execution control unit controlling execution of...

20060005098 - Interface workbench for high volume data buffering and connectivity: The application is directed to the accurate transfer of data. In various methods, systems, and devices of the present invention, a connectivity workbench may be employed to correct errors in data records transmitted between two systems. This workbench may enable real-time manual fixes as well as previously selected automatic fixes....

20060005099 - Method and system for program based redundancy: A system that includes: (ii) at least one input port adapted to receive multiple addressable packets that include media content that belong to multiple media streams and to at least one duplicating media stream; (ii) at least one processor adapted to process the multiple addressable packets to determine media stream...

20060005100 - Wireless transmit/receive unit having a turbo decoder with circular redundancy code signature comparison and method: An iterative turbo decoder for a wireless transmit receive unit (WTRU) of a wireless communication system and method for error correcting received communication signal data are provided. The decoder implements a stopping rule through use of signature codes to determine whether successive iterations of decoder data are the same....

20060005105 - Decoder and decoding method for decoding low-density parity-check codes with parity check matrix: In an LDPC-code decoder, bit-processing units are provided, respectively, for the 1st to Mth rows of the parity-check matrix that is formed of (r×s) permuted matrices having respective arrays of (m×m) Each of bit-processing units sequentially updates bit information corresponding to column positions included in the respective rows of the...

20060005104 - Decoding apparatus and method for decoding the data encoded with an ldpc code: A channel condition detecting unit detects a condition of a channel between a transmitting apparatus and a receiving apparatus, in accordance with a pilot signal. A reference check matrix employed for LDPC coding in the transmitting apparatus is stored in the check matrix reconstructing unit. The check matrix reconstructing unit...

20060005102 - Finding duplex mismatches in copper based networks: In an embodiment, a method for finding duplex mismatches in a copper based network, includes: detecting late collisions and cyclic redundancy check (CRC) errors; if a port is in auto-negotiation and up in half-duplex and over threshold late collisions have been detected, then informing the user of a duplex mismatch...

20060005106 - Mulitmedia transmission using variable error coding rate based on data importance: A broadcast multimedia data stream is partitioned into two or more parts based on importance, e.g., a first part might represent more significant bits in groups of bits representing pixel colors in a video frame, while a second part might represent the less significant bits in the groups. The more...

20060005101 - System and method for providing error recovery for streaming fgs encoded video over an ip network: A system and method provides a realistic architecture and specifies the protocols that are necessary for carrying out adaptive and efficient protection, thereby allowing applications to dynamically switch between different protection strategies. Protection is uniquely achieved by providing the protection track (206, 208, 210) as a separate stream from the...

20060005103 - System and scanout circuits with error resilience circuit: In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a...

20060005107 - Error correction in rom embedded dram: Error correction through the use of on memory encoded error correction circuitry or parity checking circuitry allow for error correction in a read only memory (ROM) embedded dynamic random access memory (DRAM)....

20060005108 - Intelligent error checking method and mechanism: An intelligent streaming media error check detection method and apparatus. The claimed embodiment discloses an apparatus and method where all streaming media are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The parameter W is not constant and conceptually represents a state of the...

20060005109 - Method and system for correcting errors in electronic memory devices: A method and system for correcting errors in multilevel memories is based upon using a combination of a BCH correction code and a Hamming correction code. The BCH correction code is used for correcting multiple errors, and the Hamming correction code is used for correcting single errors. The Hamming correction...

20060005110 - Data processing apparatus and method: A data processing apparatus may include a memory unit which stores information including sync frame data, a preceding calculation system circuit which makes a syndrome calculation from the information including sync frame data, a retry calculation system circuit which makes a syndrome calculation from information stored in the memory unit,...

20060005111 - Pipeline architecture for maximum a posteriori (map) decoders: The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are...