| Error correction apparatus for performing consecutive reading of multiple code words -> Monitor Keywords |
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Error correction apparatus for performing consecutive reading of multiple code wordsRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Data Processing System Error Or Fault Handling, Reliability And Availability, Fault Recovery, By Masking Or Reconfiguration, Of NetworkError correction apparatus for performing consecutive reading of multiple code words description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070050663, Error correction apparatus for performing consecutive reading of multiple code words. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation and claims the benefit of priority under 35 USC .sctn. 120 of U.S. application Ser. No. 10/105,010, filed Mar. 22, 2002, which claims the benefit of a foreign priority application filed in Japan, serial number 2001-082298, filed Mar. 22, 2001. The disclosure of the the prior applications are considered part of (and are incorporated by reference in) the disclosure of this application. BACKGROUND OF THE INVENTION [0002] The present invention related to an error correction apparatus, and more particularly, to an error correction apparatus for calculating the syndrome of the data stored in a buffer memory, which includes a random access memory, to correct errors. [0003] FIGS. 1(a) to 1(d) illustrate the data format of a compact disc ROM (CD-ROM). As shown in FIG. 1(a), CD-ROM data is formed from multiple sectors, each of which has 2352 bytes. Each sector includes 12 bytes of synchronizing data, 4 bytes of a header, 2048 bytes of user data, 4 bytes of error detection code (EDC) data, 8 bytes of ZERO data, and 276 bytes of error correction code (ECC) data. [0004] The data excluding the 12 bytes of synchronizing data undergoes error correction with an ECC. When the error correction is performed, the 2340 bytes of data, which do not include the synchronizing data, are alternately divided into LS bytes and MS bytes. This generates data including 1170 LS bytes (FIG. 1(c) and 1170 LS bytes (FIG. 1(d). Further, referring to FIG. 2, the 1170 LS bytes and 1170 MS bytes are coded in two directions, a P sequence (P group) direction and a Q sequence (Q group) direction. [0005] For the first 1032 bytes of data, a P parity, which consists of 2 bytes of data, is added to every 24 bytes of data in the P sequence direction. Further, 43 code words (P codes), which are coded in the P sequence direction, are configured. As apparent from FIG. 2, the position of the j.sup.th symbol for the i.sup.th code word of the P codes is represented by "i+43j (i=0, 1, . . . 42: j=0, 1, . . . 25). [0006] For the first 1032 bytes of data and the 86 bytes of P parities (2 bytes.times.43), a Q-parity, which consists of 2 bytes of data, is added to every 43 bytes of data. Further, 26 code words (Q words) which are coded in the Q sequence direction, are configured. The position of the j.sup.th symbol for the i.sup.th code word of the Q codes is represented by "43i+44j mod (remainder) 1118 (i=0, 1, . . . 25: J=0, 1, . . . 42). [0007] The symbols configuring the P codes and the Q codes are read from a memory to calculate a syndrome and determine whether the data includes errors. The detection of errors using the code words is performed as described below. [0008] A compact disc (CD) signal processing circuit performs a decoding process, such as error correction, on the data read from a CD-ROM in the same manner as CD audio. The processed data is stored as the CD-ROM data of FIG. 1(a) in a dynamic random access memory (DRAM), which is a buffer memory. FIG. 3 illustrates the CD-ROM data stored in the DRAM. [0009] More specifically, with regard to the CD-ROM sector data of FIG. 1(a), the 1176 bytes of data (6 bytes of data in the 12 bytes of synchronizing data and the 1170 LS bytes or MS bytes) are written along with the addresses of the DRAM. FIG. 3 shows an example in which column addresses have 256 bytes. A row address is incremented in cycles of 256 bytes. The MS bytes and LS bytes are actually written along each address in units of two bytes in the DRAM. The memory cells of the same row are connected to the same word line in the DRAM. [0010] The writing of data is basically performed in accordance with the order of a data stream when the CD-ROM data is transferred (i.e., the data stream of the CD-ROM data of FIG. 1(a). However, the data is actually divided into 1170 LS bytes and 1170 MS bytes. Thus, the 6 bytes of synchronizing data and the data of FIGS. 1(c) and 1(d) are written to the memory cells starting from lower addresses. For example, referring to FIG. 3, in row 0 of sector 1, the synchronizing data is written in column 1 to column 5. Data 0 of FIGS. 1(c) and 1(d) is written to row 0 column 6. Data 1 of FIGS. 1(c) and 1(d) is written to row 0 column 7. [0011] The CD-ROM data of each sector is read from the DRAM in units of code words. As an example, the reading order of the P codes will now the discussed. As shown in FIG. 4, the CD-ROM data is read in code word units of 26 bytes. The symbols forming the read code words are used to calculate the syndrome. The syndrome is set to that it has a predetermined value when each piece of data (code word) does not include an error. Thus, the calculation of the syndrome enables determination of whether a code word includes an error. [0012] When it is determined that the code word includes an error, the value of the error and the location of the error are obtained based on the syndrome. Then, data is read again from the location including an error. An exclusive OR operation is performed with the read data and the value of the error to generate correct data. The erroneous data is then rewritten by the correct data. [0013] After the error correction, the EDC data of FIG. 1(a) is used to check whether the error correction was performed properly. The data that has undergone the error correction process and the check for erroneous corrections is transferred from the DRAM to the host computer. [0014] In this manner, the code words are used to perform error correction. However, the symbols are stored in the memory cell of the DRAM at non-consecutive addresses. Thus, the time for accessing the memory cell becomes long when reading the code words. More specifically, to read a symbol from the DRAM, three operations, which include precharge, row address designation, and column address designation, are necessary. Thus, three clock signals must be provided each time a symbol is read. This hinders with increasing the speed of the error correction process. Such problem occurs in an error correction apparatus that stores data temporarily in a buffer memory and then sequentially reads symbols which performing error detection or error correction. SUMMARY OF THE INVENTION [0015] A perspective of the present invention is an error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The apparatus includes a memory access circuit for controlling reading and writing of the code words to the buffer memory. A plurality of operational circuits perform a syndrome calculation with each of the multiple code words read from the buffer memory. The memory access circuit consecutively reads the multiple code words from the buffer memory and distributes the code words to the plurality of operational circuits. [0016] A further perspective of the present invention is an error correction apparatus for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The apparatus includes a memory access circuit connected to the buffer memory for reading and writing the code words to the buffer memory in accordance with an address signal. An address generation circuit generates the address signal to designate an address of the code words read from and written to the buffer memory and to provide the address signal to the memory access circuit. A timing generation circuit is connected to the address generation circuit for generating a timing signal to control the address generation circuit so that the address signal is generated to read the code words from the buffer memory. A syndrome generation circuit generates multiple syndromes in parallel in correspondence with the multiple code words by processing the code words of the digital data read from the buffer memory. [0017] A further perspective of the present invention is a method for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The method includes consecutively reading the code words of the digital data from the buffer memory, generating multiple syndromes in parallel by processing the code words of the digital data read from the buffer memory, and performing the error correction process on the digital data using the multiple syndromes. [0018] A further perspective of the present invention is a method for performing an error correction process on digital data that is stored in a buffer memory and includes multiple code words. The method includes generating an address signal to consecutively read the code words from the buffer memory, consecutively reading the code words of the digital data from the buffer memory in accordance with the address signal, generating multiple syndromes in parallel by processing the code words read from the buffer memory, and performing the error correction process on the digital data using the multiple syndromes. [0019] Other perspectives and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0020] The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: [0021] FIGS. 1(a) to 1(d) are diagrams illustrating the data format of a prior are CD-ROM; Continue reading about Error correction apparatus for performing consecutive reading of multiple code words... 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