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Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistorsRelated Patent Categories: Semiconductor Device Manufacturing: Process, Formation Of Electrically Isolated Lateral Semiconductive Structure, Implanting To Form InsulatorEnhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070190740, Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to enhanced silicon-on-insulator transistors and a method for implementing enhanced silicon-on-insulator transistors. DESCRIPTION OF THE RELATED ART [0002] Silicon-on-insulator (SOI) transistors provide better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. Superior performance of SOI transistors at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. A buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, reducing junction capacitance. [0003] Various SOI transistor arrangements are known. For example, Wei et al., U.S. patent application Publication No. US 2003/0223258 published Dec. 4, 2003, and assigned to the present assignee, discloses a method comprising forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In other embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode. [0004] U.S. Pat. No. 6,287,901 to Christensen et al., issued Sep. 11, 2001, and assigned to the present assignee, discloses a method and semiconductor structure which are provided for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors. A bulk silicon substrate is provided. A deep ion implant layer is implanted to reside below an oxide insulator. An oxygen implant layer is implanted while applying a mask to block the oxygen implant layer in selected regions. The selected regions provide for body contact for the SOI transistors. Holes are formed extending into the deep ion implant layer and the bulk silicon substrate. The holes are filled with an electrically conductive material to create stud contacts to the deep ion implant layer and the bulk silicon substrate. [0005] While the above disclosed methods and SOI structures provide improvements over prior art arrangements, a need exists for enhanced silicon-on-insulator (SOI) transistors and methods for manufacturing thereof. It is desirable to provide such enhanced silicon-on-insulator transistors having both negligible voltage threshold change with body potential changes and negligible diffusion area capacitance during nominal operation conditions, and thus improved performance. SUMMARY OF THE INVENTION [0006] Principal aspects of the present invention are to provide enhanced silicon-on-insulator transistors and methods for implementing enhanced silicon-on-insulator transistors. Other important objects of the present invention are to provide such enhanced silicon-on-insulator transistors and methods for implementing enhanced silicon-on-insulator transistors substantially without negative effect and that overcome some of the disadvantages of prior art arrangements. [0007] In brief, enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. Selective strain is generated in the source/drain regions for enhanced carrier mobility for both P-channel and N-channel devices. [0008] A selective epitaxial (epi) growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously. A selective epi silicon germanium (SiGe) growth for PFETs or a selective epi silicon carbide (SiC) growth for NFETs is provided to form the source/drain regions. Oxygen implants below SOI source/drain regions are provided to form the thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. [0009] In accordance with features of one embodiment of the invention, a process step etches a silicon layer in the source/drain regions, leaving a seed layer. The oxygen implant step is performed through the seed layer before the source/drain regions are grown, so that the energy level of the oxygen implant step is minimized. Then a process step regrows a silicon containing material for the source/drain regions on the seed layer, while enabling the integration of appropriate strained silicon for both PFET and NFET devices. [0010] In accordance with features of other embodiments of the invention, a damascene gate process is implemented with a gate electrode and a gate oxide formed after an oxygen implant step is performed for avoiding any damage to the gate dielectric. Advantages are that one can create a weak gate, i.e., a gate with slightly lower drive currents, and that one can decouple the source/drain from the gate stack process. This weak gate also is called a wimpy gate. These advantages can integrate both standard polysilicon gates with conventional gate dielectrics such as silicon dioxide and silicon oxynitride, and with metal gates with high-dielectric constant (high-K) materials such as hafnium oxide, hafnium oxynitrde, and the like, on, the same substrate with low junction capacitance and an effective back gate. [0011] In accordance with features of other embodiments of the invention, a new dual-gate structure is provided with a front gate comprising of a high K dielectric and metal gate stack, and a back gate comprising of SiO.sub.2 and silicon gate stack. The differentiating and novel features of this structure are that it is a planar double gate device with significantly different gate oxide and gate material on each side of the channel. These two different gate stacks give the device the ability to operate with either the front or the back channel functioning, or both, depending on the thickness of the silicon layer, the bias conditions, and the materials used. This dual-gate device also provides an enhanced reliability device when the back gate is used to enhance how the device progresses through the burn-in process. By optimizing back gate properties to withstand elevated voltages, the device burn-in can be accelerated in a way that most conventional fails are detected, for example, metal defects, mobile ions, wiring dielectric issues, negative temperature bias instability, and the like. [0012] In accordance with features of one embodiment of the invention, a damascene gate is used to self-align the thick BOX region to the SOI source/drain diffusion areas. [0013] In accordance with features of one embodiment of the invention, a thick shallow trench isolation (STI) region is formed over a thin BOX layer. The oxygen implant step is performed using a damascene gate to self-align the thick BOX region to the SOI source/drain diffusion areas. The thick STI regions are used to mask the BOX implants at device edges of the SOI source/drain diffusion areas. [0014] In accordance with features of one embodiment of the invention, a polysilicon region and a pad oxide are provided for defining a damascene gate region. After the thick BOX regions are formed and the source/drain are formed, the sacrificial polysilicon region is covered by a molding material, such as, silicon nitride and is chemical-mechanically polished to exposed the top of the sacrificial polysilicon. Then the polysilicon and a pad oxide are stripped. A gate dielectric and a gate electrode are deposited. This manufacturing process enables the use of a gate dielectric having a high dielectric constant, such as 3.1<K.ltoreq.30, deposited when no further high temperature processes are required. BRIEF DESCRIPTION OF THE DRAWINGS [0015] The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: [0016] FIGS. 1-4 are diagrams not to scale illustrating exemplary steps for implementing enhanced silicon-on-insulator (SOI) transistors in accordance with one preferred embodiment; [0017] FIGS. 5-7A and 7B, 8-12A and 12B are diagrams not to scale illustrating exemplary steps for implementing enhanced silicon-on-insulator (SOI) transistors in accordance with another preferred embodiment; and [0018] FIGS. 13-20A and 20B are diagrams not to scale illustrating exemplary steps for implementing enhanced silicon-on-insulator (SOI) transistors in accordance with still another preferred embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0019] In accordance with features of a preferred embodiment, enhanced silicon-on-insulator (SOI) transistors include a thick self-aligned buried oxide (BOX) region under SOI source/drain (S/D) diffusions while maintaining a thin BOX under the silicon body for good backside coupling. A self-aligned epitaxial (epi) growth is utilized in the S/D regions with appropriate strain to enhance PFET and NFET devices simultaneously. Simultaneous enhancement of SOI devices is provided through selective strain and also by reducing diffusion area capacitance Cja while maintaining good backgate coupling. Continue reading about Enhanced silicon-on-insulator (soi) transistors and methods of making enhanced soi transistors... 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