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  Encoding/decoding circuitUSPTO Application #: 20070014396Title: Encoding/decoding circuit Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding/decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout. (end of abstract) Agent: Buchanan, Ingersoll & Rooney PC - Alexandria, VA, US Inventors: Shigenori Miyauchi, Atsuo Yamaguchi USPTO Applicaton #: 20070014396 - Class: 380028000 (USPTO) Related Patent Categories: Cryptography, Particular Algorithmic Function Encoding The Patent Description & Claims data below is from USPTO Patent Application 20070014396. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an encoding/decoding circuit which ensures the safety of data requiring concealment. [0003] 2. Description of the Background Art [0004] Patent Document 1, Japanese Patent Application Laid Open Gazette No. 2004-88505, discloses an encoding/decoding circuit which can avoid complication of key selection for stream data inputted in parallel. In this circuit, to a plurality of input interfaces, stream data of TV broadcast, stream data recorded in a DVD, stream data of CATV line or the like are inputted in parallel (see Paragraph 0015), and its arbitration portion outputs a decoding key and input data in accordance with an input channel to an encoding/decoding operation portion (see Paragraph 0038). Then, the encoding/decoding operation portion decodes the encoded data which is inputted by using the decoding key inputted from the arbitration portion and outputs the decoded data (see Paragraph 0039). [0005] In Patent Document 1, the construction to set the content of key data in registers 131 to 134 shown in its FIG. 1 is only described as "keys 131 to 134 are each formed of a register and a decoding key of a program in accordance with channel selection of a viewer is set by a control portion of a TV receiving device" (see Paragraph 0025), but no specific description is made on a specific circuit configuration to set the content of the key data. Therefore, in view of this description, it is thought that a plurality of wires are simply provided to supply key data from an input interface or an input stream processing portion to the respective registers 131 to 134. Providing the wires from the input interface or the input stream processing portion to the respective registers 131 to 134, however, causes an increase in the number of wires and complication of circuit layout. [0006] Further, in Patent Document 1, a key storage portion of its FIG. 1 only includes one register (each of 131 to 134) for a channel of data to be encoded or decoded. In order to generate a new key from stream data by using a key stored in the register, it is necessary to obtain the second key through decoding by using the first key stored in the register and then write the second key over the register. After that, in order to obtain a key other than the second key through decoding by using the first key, it is necessary to write the first key over the register again. Such an encoding/decoding operation disadvantageously causes a decrease in throughput of data processing. [0007] Furthermore, Patent Document 1 has a problem that information of a key which requires concealment and output stream data which requires concealment are easily acquired from the outside in an illegal manner and easily interpolated. [0008] If a block encoding/decoding system, such as a CBC (Cipher Block Chaining) system or a CFB (Cipher FeedBack) system, is adopted, it is necessary to give an IV (Initialization Vector) for generation of the first key. A key generated from this IV may be stored inside a chip in which an encoding/decoding circuit is formed or in a nonvolatile memory or the like, which is provided outside. [0009] If a refined process is adopted to reduce the chip cost, however, it becomes difficult to integrate the nonvolatile memory for storing a key and an encoding/decoding program in one chip in which the encoding/decoding circuit is formed. This is because it is difficult to refine a nonvolatile memory and if such a leading-edge process as realizes a gate length of 90 nm is adopted, an encoding/decoding circuit can be formed while it is difficult to form a nonvolatile memory in the same chip through the same process. [0010] It is a matter of course that the safety of key should increase if a nonvolatile memory is integrated in a chip in which an encoding/decoding circuit is formed. The reason is that if a nonvolatile memory is provided outside and the nonvolatile memory which is a general-purpose product is made removable, it becomes easy to remove the nonvolatile memory and interpolate the content of a key stored therein. [0011] In other words, the background-art encoding/decoding circuit of Patent Document 1 gives no consideration to the security of information of a key which requires concealment. SUMMARY OF THE INVENTION [0012] It is an object of the present invention to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit the content of key data to a data storage portion and does not cause complication of circuit layout. It is another object of the present invention to realize an encoding/decoding circuit which allows an increase in throughput of an encoding/decoding operation. It is still another object of the present invention to realize an encoding/decoding circuit which ensures the safety of data requiring concealment. [0013] The present invention is intended for an encoding/decoding circuit. According to a first aspect of the present invention, the encoding/decoding circuit comprises an input portion, an encoding/decoding operation portion, an output portion and a data storage portion. The encoding/decoding operation portion includes an encoding/decoding operation circuit for encoding or decoding data inputted through the input portion, an avoiding path for causing the data inputted through the input portion to detour the encoding/decoding operation circuit, and a selector for selectively outputting an output of the encoding/decoding operation circuit and an output of the avoiding path. An output of the selector is given to the output portion and the data storage portion. The data storage portion gives data stored therein to the encoding/decoding operation portion. [0014] According to a second aspect of the present invention, the encoding/decoding circuit comprises an encoding/decoding operation portion and a key storage portion. The key storage portion includes a plurality of memory portions for one channel of input data which is to be subject to encoding or decoding in the encoding/decoding operation portion. One of the plurality of memory portions stores a first key for the encoding or the decoding. The encoding/decoding operation portion decodes the input data into a second key for the encoding or the decoding by using the first key stored in the one of the plurality of memory portions and stores the second key into another one of the plurality of memory portions. [0015] According to a third aspect of the present invention, the encoding/decoding circuit comprises an encoding/decoding operation portion and a key storage portion. The key storage portion includes a first memory portion and a plurality of second memory portions corresponding to a plurality of channels of input data which is to be subject to encoding or decoding in the encoding/decoding operation portion, respectively. The first memory portion stores a first key for the encoding or the decoding, which is common to the plurality of channels. The encoding/decoding operation portion decodes the input data into a second key for the encoding or the decoding by using the first key stored in the first memory portion and stores the second key into one of the plurality of second memory portions. [0016] According to a fourth aspect of the present invention, the encoding/decoding circuit comprises a key storage portion, a decoding operation portion for decoding input data which is to be subject to decoding to obtain a second key for the decoding by using a given first key and stores the second key into the key storage portion, and a key validity judgment circuit. The key validity judgment circuit activates a key valid signal indicating the second key is valid if the decoding operation portion obtains the second key through decoding by using the first key, and inactivates the key valid signal if the second key is obtained through decoding by using a key other than the first key. [0017] According to a fifth aspect of the present invention, the encoding/decoding circuit comprises a key storage portion, an encoding/decoding operation portion which uses a given encoding key, for generating a decoding key to decode input data which is encoded by the encoding key, and storing the decoding key into the key storage portion, and a decoding key validity judgment circuit. The decoding key validity judgment circuit activates a decoding key valid signal indicating the decoding key is valid if the encoding/decoding operation portion generates the decoding key by using the encoding key, and inactivates the decoding key valid signal if the decoding key is generated by using a key other than the encoding key. [0018] According to a sixth aspect of the present invention, the encoding/decoding circuit comprises a key storage portion in which a first generation encoding key is stored, an encoding/decoding operation portion, and an encoding key/decoding key generation coincidence judgment circuit. The encoding/decoding operation portion uses the first generation encoding key to generate a second generation encoding key for encoding input data, and updates the first generation encoding key and stores the second generation encoding key into the key storage portion. The encoding/decoding operation portion sequentially uses an n-th (n: natural number) generation encoding key to generate an (n+1)th generation encoding key for encoding the input data, and updates the n-th generation encoding key and stores the (n+1)th generation encoding key into the key storage portion. The encoding/decoding operation portion uses the first generation encoding key to generate a first generation decoding key for decoding the input data which is encoded by the first generation encoding key and stores the first generation decoding key into the key storage portion. The encoding/decoding operation portion sequentially uses encoding keys until the (n+1)th generation to generate decoding keys until the (n+1)th generation for decoding the input data, respectively, and updates an n-th generation decoding key and stores the (n+1)th generation decoding key into the key storage portion. The encoding key/decoding key generation coincidence judgment circuit activates an encoding key/decoding key generation coincidence signal indicating the n-th generation decoding key is valid if the encoding/decoding operation portion generates the n-th generation decoding key by using the corresponding n-th generation encoding key, and inactivates the encoding key/decoding key generation coincidence signal if the n-th generation decoding key is generated by using a key other than the corresponding n-th generation encoding key. [0019] According to a seventh aspect of the present invention, the encoding/decoding circuit comprises a key storage portion in which a first generation encoding key is stored, an encoding/decoding operation portion, and an encoding key/decoding key generation permission circuit. The encoding/decoding operation portion uses the first generation encoding key to generate a second generation encoding key for encoding input data, and updates the first generation encoding key and stores the second generation encoding key into the key storage portion. The encoding/decoding operation portion sequentially uses an n-th (n: natural number) generation encoding key to generate an (n+1)th generation encoding key for encoding the input data, and updates the n-th generation encoding key and stores the (n+1)th generation encoding key into the key storage portion. The encoding/decoding operation portion uses the first generation encoding key to generate a first generation decoding key for decoding the input data which is encoded by the first generation encoding key and stores the first generation decoding key into the key storage portion. The encoding/decoding operation portion sequentially uses encoding keys until the (n+1)th generation to generate decoding keys until the (n+1)th generation for decoding the input data, respectively, and updates an n-th generation decoding key and stores the (n+1)th generation decoding key into the key storage portion. The encoding key/decoding key generation permission circuit generates an encoding key/decoding key n-th generation permission signal indicating the decoding keys until the n-th generation are generated every time when the n-th generation decoding key is generated if the encoding/decoding operation portion generates the n-th generation decoding key to be valid by using the corresponding n-th generation encoding key. [0020] According to an eighth aspect of the present invention, the encoding/decoding circuit comprises an encoding/decoding operation portion, a key storage portion and a start key output circuit including a combination of a plurality of logic gate circuits, for generating a predetermined signal by using the combination and outputting the predetermined signal as a start key. The encoding/decoding operation portion encodes a given first key for encoding or decoding input data by using the start key and stores the first key into the key storage portion. [0021] According to a first aspect of the present invention, the encoding/decoding operation portion includes the encoding/decoding operation circuit, the avoiding path and the selector, and the output of the selector is connected to the output portion and the data storage portion and the data storage portion gives data stored therein to the encoding/decoding operation portion. Therefore, it is possible both to encode or decode the data inputted through the input portion in the encoding/decoding operation circuit to output it to the output portion and the data storage portion and to detour the encoding/decoding operation circuit to output the data without change to the output portion and the data storage portion. If a construction where wires are provided from the input portion to the data storage portion is adopted, like in the background-art technique, when the block encoding/decoding system such as CBC or CFB is adopted in the encoding/decoding operation circuit, a wire from the encoding/decoding operation circuit to the data storage portion is also needed and the connection wiring to the data storage portion is doubly needed. On the other hand, in the present invention, only one wire from the selector to the data storage portion has to be provided, and it is therefore possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit the content of key data to the data storage portion and does not cause complication of circuit layout. [0022] According to a second aspect of the present invention, the key storage portion includes a plurality of memory portions for one channel of input data which is to be subject to encoding or decoding in the encoding/decoding operation portion, and the encoding/decoding operation portion decodes the input data into the second key for encoding or decoding by using the first key for encoding or decoding which is stored in one of a plurality of memory portions and stores the second key into another one of a plurality of memory portions. If the key storage portion includes only one memory portion for a channel of input data to be encoded or decoded, like in the background-art technique, it is necessary to decode the input data into the second key by using the first key stored in one memory portion and write the second key over the memory portion. After that, in order to obtain a key other than the second key through decoding by using the first key, it is necessary to write the first key over the memory portion again. On the other hand, in the present invention, the key storage portion includes a plurality of memory portions for a channel of input data and the first key can be kept in one of the memory portions without overwriting. It is therefore possible to increase the throughput of an encoding/decoding operation. Continue reading... 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