| Encoders for block-circulant ldpc codes -> Monitor Keywords |
|
|
 
Encoders for block-circulant ldpc codesRelated Patent Categories: Pulse Or Digital Communications, Pulse Code ModulationEncoders for block-circulant ldpc codes description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060291571, Encoders for block-circulant ldpc codes. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is filed on the same day of U.S. patent application Ser. No. ______ Attorney Docket No. 622663-8, for "ARA Type Protograph Codes", incorporated herein by reference in its entirety. BACKGROUND [0003] 1. Field [0004] The present disclosure relates to encoders and encoding methods for block-circulant low-density parity-check (LDPC) codes. In particular, a first encoder and iterative encoding method are based on the erasure decoding algorithm. The computations required are well organized due to the block-circulant structure of the parity check matrix. A second encoder and method use block-circulant generator matrices. Some encoders of the second type have been implemented in a small Field Programmable Gate Array (FPGA) and can operate at 100 Msymbols/second. [0005] 2. Related Art [0006] Recently, block-circulant LDPC codes have been found that provide both excellent error correction performance and well structured decoder architectures. Constructions have been presented in the following papers:. [0007] Y. Kou, H. Tang, S. Lin, and K. Abdel-Ghaffar, "On Circulant Low Density Parity Check Codes," IEEE International Symposium on Information Theory, p. 200, June 2002; [0008] S. Lin, "Quasi-Cyclic LDPC Codes." CCSDS working group white paper, Oct. 2003; [0009] R. M. Tanner, "On Graph Constructions for LDPC Codes by Quasi- Cyclic Extension," in Information, Coding and Mathematics (M. Blaum, P. Farrell, and H. van Tilborg, eds.), pp. 209-220, Kluwer, June 2002; [0010] A. Sridharan, D. Costello, and R. M. Tanner, "A Construction for Low Density Parity Check Convolutional Codes Based on Quasi-Cyclic Block Codes," in IEEE International Symposium on Information Theory, p. 481, June 2002; [0011] O. Milenkovic, I. Djordjevic, and B. Vasic, "Block-Circulant Low-Density Parity-Check Codes for Optical Communication Systems," IEEE Journal of Selected Topics in Quantum Electronics, pp. 294-299, March 2004; [0012] J. Thorpe, K. Andrews, and S. Dolinar, "Methodologies for Designing LDPC Codes Using Protographs and Circulants," in IEEE International Symposium on Information Theory, p. 238, June 2004), and others. All of the above papers are incorporated herein by reference in their entirety. [0013] Error correcting codes are used to transmit information reliably over an unreliable channel, such as a radio communications link or a magnetic recording system. One class of error correcting codes are binary block codes, where K information bits are encoded into a codeword of N symbols (N>K), the codeword is transmitted over the channel, and a decoder then attempts to decode the received (and potentially corrupted) symbols into the original K information bits. If the channel symbols are also binary, an encoder that uses the K information bits as K of the. N channel symbols is known as a systematic encoder. These K channel symbols are called the systematic symbols, and the remaining N-K symbols are called parity symbols. Sometimes one uses an encoder that generates N+P symbols, and then P of them are discarded while the remaining N are transmitted over the channel. The discarded symbols are known as punctured symbols. [0014] Many different mathematical models are used to describe physical communications channels. One model is the Binary Erasure Channel (BEC). The input alphabet is binary (either 0 or 1), and the output alphabet is ternary (0, 1, or e for erasure). When a 0 is transmitted over the BEC, the received symbol may be either 0 or e; similarly, a transmitted 1 is received either as a 1 or e. An erasure correcting decoder is used with a BEC, and its task is to reconstruct the binary values that were transmitted and corrupted to the value e by the channel. In particular, puncturing a codeword is equivalent to transmitting it over a BEC, where each punctured symbol is corrupted to the value e. [0015] Erasure correcting decoders for LDPC codes have been studied at length [see, for example, M. Luby, M. Mitzenmacher, A. Shokrollahi, D. Spielman, and V. Stemann, "Practical loss-resilient codes," in Proc. 29th Annual ACM Symp. Theory of Computing, 1997, pp. 150-159], and the decoding method described in that paper has become the standard erasure correcting algorithm. This erasure correcting algorithm succeeds if and only if the erased symbol positions do not contain a stopping set [see T. Richardson and R. Urbanke, "Efficient Encoding of Low-Density Parity-Check Codes, IEE Trans. on Information Theory, February 2001, pp. 638-656]. [0016] U.S. Pub. App. No. 20040153934 discloses a method and apparatus for encoding LDPC codes. SUMMARY [0017] In accordance with the present disclosure, novel encoders, encoding methods and a hardware encoder implementation for block-circulant LDPC codes will be presented. [0018] According to a first aspect, an encoding apparatus to encode message input symbols in accordance with an accumulate-repeat-accumulate code with repetition four is disclosed, the apparatus comprising: a first multiplier to multiply a first portion of the input symbols with a first matrix, forming first intermediate symbols; a second multiplier to multiply a second portion of the input symbols with a second matrix, forming second intermediate symbols; a first adder to sum the first intermediate symbols with the second intermediate symbols, forming third intermediate symbols; a third multiplier to multiply the third intermediate symbols with a third matrix, forming fourth intermediate symbols; a fourth multiplier to multiply the third intermediate symbols with a fourth matrix, forming a first set of output symbols; a second adder to sum the fourth intermediate symbols with the second portion of the input symbols, forming fifth intermediate symbols; a permuter to permute the fifth intermediate symbols, forming permuted symbols; and an accumulator to accumulate the permuted symbols, forming a second set of output symbols. [0019] According to a second aspect, a method for encoding message input symbols in accordance with an accumulate-repeat-accumulate code with repetition four is disclosed, comprising: multiplying a first portion of the input symbols with a first matrix, forming first intermediate symbols; multiplying a second portion of the input symbols with a second matrix, forming second intermediate symbols; adding the first intermediate symbols to the second intermediate symbols, forming third intermediate symbols; multiplying the third intermediate symbols with a third matrix, forming fourth intermediate symbols; multiplying the third intermediate symbols with a fourth matrix, forming a first set of output symbols; adding the fourth intermediate symbols with the input symbols, forming fifth intermediate symbols; permuting the fifth intermediate symbols, forming permuted symbols; and accumulating the permuted symbols, forming a second set of output symbols. [0020] According to a third aspect, an encoding apparatus to encode message input symbols in accordance with an accumulate-repeat-accumulate code with repetition three is disclosed, the apparatus comprising: a puncturing device, puncturing k input symbols and outputting k/2 input symbols, forming a first set of output symbols; a first multiplier to multiply the k input symbols with a first matrix, forming first intermediate symbols; a second multiplier to multiply the k input symbols with a second matrix, forming a second set of output symbols; a permuter to permute the first intermediate symbols, forming permuted symbols; and an accumulator to accumulate the permuted symbols, forming a third set of output symbols. [0021] According to a fourth aspect, a method for encoding message input symbols in accordance with an accumulate-repeat-accumulate code with repetition three is disclosed, comprising: puncturing k input symbols and outputting k/2 input symbols, forming a first set of output symbols; multiplying the k input symbols with a first matrix, forming first intermediate symbols; multiplying the k input symbols with a second matrix, forming a second set of output symbols; permuting the first intermediate symbols, forming permuted symbols; and accumulating the permuted symbols, forming a third set of output symbols. [0022] According to a fifth aspect, an encoding apparatus to encode input symbols in accordance with a block-circulant LDPC code is disclosed, the apparatus comprising: a plurality of recursive convolutional encoders, each recursive convolutional encoder comprising storage units, multipliers and adders to encode the input symbols; and a plurality of circulant patterns to be fed to the recursive convolutional encoders, one set of patterns for each recursive convolutional encoder. [0023] According to a sixth aspect, a method for encoding input symbols in accordance with a block-circulant LDPC code is disclosed, comprising: providing a plurality of recursive convolutional encoders, each recursive convolutional encoder comprising storage units, multipliers and adders; setting the storage units to a first binary value; repeating the following operations: i) computing a set of circulant patterns, ii) providing each recursive convolutional encoder with a binary sequence of T message bits, each message bit sent to the output as a codeword symbol, and each message bit being multiplied with a circulant pattern, summed to the result of a previous multiplication, stored in a storage unit and shifted, until the T message bits have been encoded, until kT message bits have been encoded; and generating an output codeword by reading the contents of the storage units of the recursive convolutional encoders. BRIEF DESCRIPTION OF THE DRAWINGS [0024] FIG. 1 shows a protograph for an AR3A code. [0025] FIG. 2 shows a protograph for an AR4A code. [0026] FIG. 3 shows a parity check matrix for an AR4A code. [0027] FIG. 4 shows a block diagram of an AR4A encoder. Continue reading about Encoders for block-circulant ldpc codes... Full patent description for Encoders for block-circulant ldpc codes Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Encoders for block-circulant ldpc codes patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Encoders for block-circulant ldpc codes or other areas of interest. ### Previous Patent Application: Information processing apparatus, information processing method and recording medium Next Patent Application: Communication channel calibration for drift conditions Industry Class: Pulse or digital communications ### FreshPatents.com Support Thank you for viewing the Encoders for block-circulant ldpc codes patent info. IP-related news and info Results in 0.28423 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
