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Embossing processes for substrate imprinting, structures made thereby, and polymers used thereforRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead, Bump LeadsEmbossing processes for substrate imprinting, structures made thereby, and polymers used therefor description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070182010, Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] Disclosed embodiments relate to mounting a microelectronic device on a substrate. BACKGROUND INFORMATION Description of Related Art [0002] Various techniques have been tried to prepare imprinted substrates such as printed wiring boards (PWBs). As thermal management becomes more challenging due to miniaturization, dielectric particulates in the underfill material have become more important to lower the coefficient of thermal expansion (CTE) of the underfill composite. As the percentage of low CTE filler particles has increased, capillary flow of the underfill composite has become more difficult. [0003] As the circuitry of the semiconductor devices grows smaller, lower dielectric constant insulators are needed to maintain good electrical performance. As the dielectric constant of the insulator lowers, these materials lose some of their mechanical robustness. The underfill material therefore protects the die from mechanical stress. The low CTE filler assists in this function. To assist in lowering the mechanical stress, the low CTE filler is selected to have a CTE that is close to that of the die. The advent of these highly filled underfills necessitated a closer look at the no-flow underfill process. The no-flow underfill process includes dispensing the underfill material on the substrate before attaching the die. The no-flow process experiences the entrapment of some filler particles between the solder bump and the bond pad. Consequently, the particulates decreased the quality of the electrical contact between the bond pad and the bump. BRIEF DESCRIPTION OF THE DRAWINGS [0004] In order to understand the manner in which embodiments are obtained, a more particular description of various embodiments briefly described above will be rendered by reference to the appended drawings. These drawings depict embodiments that are not necessarily drawn to scale and are not to be considered to be limiting in scope. Some embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings in which: [0005] FIG. 1A is a cross-section of a structure during processing according to an embodiment; [0006] FIG. 1B is a cross-section of the structure depicted in FIG. 1A during processing according to an embodiment; [0007] FIG. 1C is a cross-section of the structure depicted in FIG. 1B after further processing; [0008] FIG. 1D is a cross-section of the structure depicted in FIG. 1C after further processing; [0009] FIG. 1E is a cross-section of the structure depicted in FIG. 1D after further processing; [0010] FIG. 1F is a cross-section of the structure depicted in FIG. 1E after further processing; [0011] FIG. 1G is a cross-section of the structure depicted in FIG. 1F after further processing; [0012] FIG. 2 is an elevation taken from a section in FIG. 1B according to an embodiment; [0013] FIG. 3 is an elevation taken from a section in FIG. 1D according to an embodiment; [0014] FIG. 4A is a cross-section of a structure during processing according to an embodiment; [0015] FIG. 4B is a cross-section of the structure depicted in FIG. 4A during processing according to an embodiment; [0016] FIG. 4C is a cross-section of the structure depicted in FIG. 4B after further processing; [0017] FIG. 4D is a cross-section of the structure depicted in FIG. 4C after further processing; [0018] FIG. 4E is a cross-section of the structure depicted in FIG. 4D after further processing; [0019] FIG. 4F is a cross-section of the structure depicted in FIG. 4E after further processing; [0020] FIG. 5 is an elevation taken from a section in FIG. 4B according to an embodiment; Continue reading about Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor... Full patent description for Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor or other areas of interest. ### Previous Patent Application: Wiring board and method for manufacturing the same and semiconductor device and method for manufacturing the same Next Patent Application: Method for forming a redistribution layer in a wafer structure Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Embossing processes for substrate imprinting, structures made thereby, and polymers used therefor patent info. IP-related news and info Results in 0.16042 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , 174 |
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