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Embedded waveguide detectorsEmbedded waveguide detectors description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20090269878, Embedded waveguide detectors. Brief Patent Description - Full Patent Description - Patent Application Claims This application is a continuation of U.S. patent application Ser. No. 11/484,009, filed Jul. 10, 2006, which is a divisional of U.S. patent application Ser. No. 10/856,750, filed May 28, 2004, (now U.S. Pat. No. 7,075,165), which claims the benefit of U.S. Provisional Application No. 60/474,145, filed May 29, 2003. The invention generally relates to optical detectors and methods of fabricating such detectors. To build an optical signal distribution network within a semiconductor substrate, one needs to make good optical waveguides to distribute the optical signals, and one needs to fabricate elements that convert the optical signals to electrical signals in order to interface with other circuitry. Extracting the optical signals can be accomplished in two ways. Either the optical signal itself is extracted out of the waveguide and delivered to other circuitry that can convert it to the required form. Or the optical signal is converted into electrical form in the waveguide and the electrical signal is delivered to the other circuitry. Extracting the optical signal as an optical signal involves the use of mirrors, gratings or couplers within the waveguides, or other elements that function like these devices. The scientific literature has an increasing number of examples of technologies that can be used to construct such devices. Extracting the optical signal as an electrical signal involves the use of detectors within the waveguide, i.e., circuit elements that convert the optical signal to an electrical form. The scientific literature also has an increasing number of examples of detector designs that can be used to accomplish this. The challenge in finding the combination of elements that produces an acceptable optical distribution network becomes greater, however, when one limits the frame of reference to particular optical signal distribution network designs and takes into account the practical reality that any such designs should be relatively easy to fabricate and financially economical. The combination of silicon and SiGe alloys (e.g. SixGe1-x) has attracted attention as useful combination of materials from which one might be able to easily and economically fabricate optical signal distribution networks. With SiGe alloys it is possible to fabricate waveguides in the silicon substrates. The index of refraction of a SiGe alloy is slightly higher than that of silicon. For example, a SiGe alloy with 5% Ge (i.e., Si0.95Ge0.05) has an index of refraction of about 3.52 while crystalline silicon has an index of refraction that is less than that, e.g. about 3.50. So, if a SiGe alloy core is formed in a silicon substrate, the difference in the indices of refraction is sufficient to enable the SiGe alloy core to contain an optical signal through internal reflections. Moreover, this particular combination of materials lends itself to the use of conventional silicon based semiconductor fabrication technologies to fabricate the optical circuitry. Of course, for such a system to work as an optical signal distribution network, the optical signal must have a wavelength to which both the Si and the SiGe alloy are transparent. Since the bandgap energy of these materials is approximately 1.1 eV, they appear transparent to optical wavelengths having a wavelength greater than 1150 nm. A further reduction in bandgap energy caused by use of a SiGe alloy rather than pure Silicon, and higher temperature operation as high as 125° C. may further require the wavelength be longer than 1200 nm or even 1250 nm for very low absorption loss (approximately 1 db/cm or less). But, the transparency of these materials to optical signals having those wavelengths brings with it another problem. These materials are generally not suitable for building detectors that can convert the optical signals to electrical form. To be a good detector, the materials must be able to absorb the light in a manner so as to create useful charge that can be detected electrically. That is, the optical signal must be capable of generating electron transitions from the valence band to the conduction band within the detector to produce an electrical output signal. But the wavelengths greater than 1150 nm are too long to produce useful absorption by electron transitions in silicon, or in Si0.95Ge0.05 alloys at room temperature. At a wavelength of 1300 nm, the corresponding photon energy is about 0.95 eV, well below the room temperature bandgap of silicon and Si0.95Ge0.05 and consequently well below the amount necessary to cause transitions from the valence band into the conductor band. In general, in one aspect, the invention features a method of fabricating a detector. The method involves: forming a trench in a substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer. Other embodiments include one or more of the following features. Forming the first and second doped semiconductor layers on the substrate involves depositing silicon. Forming the second semiconductor layer on the first doped semiconductor layer involves depositing a SiGe alloy. Depositing the first, second, and third layers involves epitaxially depositing. Removing involves removing by chemical mechanical polishing. In general, in another aspect, the invention features another method of fabricating a detector. The method involves: forming a trench in a substrate having an upper surface; forming a first semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench; forming a third semiconductor layer on the second semiconductor layer and extending into the trench, wherein the second semiconductor layer absorbs light of wavelength λ and the first and third semiconductor layers transmits light of wavelength λ; removing deposited materials that are above a plane defined by the surface of the substrate and thereby forming an upper, substantially planar surface and exposing an upper end of the first doped layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer. Other embodiments include one or more of the following features. Forming the second semiconductor layer involves selecting a semiconductor material for the second semiconductor layer for which second bandgap is smaller than the bandgaps of both the first and third semiconductor layers. Alternatively, forming the second semiconductor layer involves introducing a dopant that produces deep level energy states in the bandgap between the conduction and valence bands. In general, in still another aspect, the invention features a detector including: a substrate having a top surface and a first trench formed therein; a first semiconductor layer conforming to an inside contour of the first trench and having an upper surface defining a second trench within the first trench, the first semiconductor layer having a first end that is substantially coplanar with the top surface of the substrate; a second semiconductor layer conforming to an inside contour of the second trench and having an upper surface defining a third trench within the second and first trenches; a third semiconductor layer filling the third trench and having a top side that is substantially coplanar with the top surface if the substrate; a first conductive material making an electrical contact to the first layer at the first end; and a second conductive material making electrical contact to the third layer on the top side of the third layer. Other embodiments include one or more of the following features. The first and third semiconductor layers are made of a doped silicon. The second semiconductor layer is made of a SiGe alloy. The SiGe alloy is characterized by a conduction band located above and separated from a valence band by a bandgap, and the SiGe alloy contains an impurity that introduces deep level energy states in the bandgap between the conduction and valence bands. Alternatively, the second semiconductor layer absorbs light of wavelength λ and the first and third semiconductor layers transmit light of wavelength λ. The second semiconductor layer has a bandgap that is less that than bandgap of both the first and third semiconductor layers. Other features and advantages of the invention will be apparent from the following detailed description and from the claims. Continue reading about Embedded waveguide detectors... Full patent description for Embedded waveguide detectors Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Embedded waveguide detectors patent application. Patent Applications in related categories: 20090286349 - Solar cell spin-on based process for simultaneous diffusion and passivation - A thin silicon solar cell having a high quality spin-on dielectric layer is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A first dielectric layer is applied to the rear surface of the silicon wafer using a ... ### 1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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