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Embedded rom device using substrate leakageRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active RegionsEmbedded rom device using substrate leakage description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060094167, Embedded rom device using substrate leakage. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This is a continuation application of U.S. patent application Ser. No. 10/924,416 filed Aug. 24, 2004, which is a continuation of U.S. patent application Ser. No. 10/194,549, filed Jul. 11, 2002 (now U.S. Pat. No. 6,781,867) and commonly titled "EMBEDDED ROM DEVICE USING SUBSTRATE LEAKAGE," which applications are commonly assigned to the assignee of the present invention and the entire contents of which are incorporated herein by reference. TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to memory devices and in particular the present invention relates to read only memory (ROM) embedded in a dynamic random access memory (DRAM). BACKGROUND OF THE INVENTION [0003] Semiconductor memory systems are comprised of two basic elements: memory storage areas and memory control areas. DRAM, for example, includes a memory cell array, which stores information, and peripheral circuitry, which controls the operation of the memory cell array. [0004] DRAM arrays are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor. The capacitor holds the value of each cell, namely a "1" or a "0," as a charge on the capacitor. Because the charge on a capacitor gradually leaks away, DRAM capacitors must be refreshed on a regular basis. A memory device incorporating a DRAM memory includes logic to refresh (recharge) the capacitors of the cells periodically or the information will be lost. Reading the stored data in a cell and then writing the data back into the cell at a predefined voltage level refreshes a cell. The required refreshing operation is what makes DRAM memory dynamic rather than static. [0005] The transistor of a DRAM cell is a switch to let control circuitry for the RAM either read the capacitor value or to change its state. The transistor is controlled by a row line coupled to its gate connection. In a read operation, the transistor is activated and sense amplifiers coupled to bit lines (column) determine the level of charge stored in the memory cell capacitor, and reads the charge out as either a "1" or a "0" depending upon the level of charge in the capacitor. In a write operation, the sense amplifier is over-powered and the memory cell capacitor is charged to an appropriate level. [0006] Frequently, as in the case of microprocessors, microcontrollers, and other application specific integrated circuitry (ASICs), it is desired to incorporate read only memory (ROM) together with or in addition to RAM on a single semiconductor wafer. This typically requires the formation of separate additional peripheral circuitry and interconnects for the ROM. The ROM cells and additional circuitry require additional semiconductor wafer space and fabrication process steps that increase the overall costs of device fabrication. [0007] A read only memory (ROM) consists of an array of semiconductor devices (diodes, bipolar or field-effect transistors), which interconnect to store an array of binary data (ones or zeros). A ROM basically consists of a memory array of programmed data and a decoder to select the data located at a desired address in the memory array. [0008] Three basic types of ROMs are mask-programmable ROMs, erasable programmable ROMs (EPROMs) and field-programmable ROMs (PROMs). The data array is permanently stored in a mask-programmable ROM, at the time of manufacture, by selectively including or omitting the switching elements at the row-column intersections in the memory array. This requires a special mask used during fabrication of the integrated circuit, which is expensive and feasible only when a large quantity of the same data array is required. EPROMs use a special charge-storage mechanism to enable or disable the switching elements in the memory array. In this case, appropriate voltage pulses to store electrical charges at the memory array locations are provided. The data stored in this manner is generally permanent until it is erased using ultraviolet light allowing it to once again be programmed. PROMs are typically manufactured with all switching elements present in the array, with the connection at each row-column intersection being made by means of either a fuse element or an anti-fuse element. In order to store data in the PROM, these elements (either the fuse or the anti-fuse, whichever are used in the design) are selectively programmed using appropriate voltage pulses supplied by a PROM programmer. Once the elements are programmed, the data is permanently stored in the memory array. [0009] Programmable links have been used extensively in programmable read only memory (PROM) devices. Probably the most common form of programmable link is a fusible link. When a user receives a PROM device from a manufacturer, it usually consists of an X-Y matrix or lattice of conductors or semiconductors. At each cross-over point of the lattice a conducting link, call a fusible link, connects a transistor or other electronic node to this lattice network. The PROM is programmed by blowing the fusible links to selected nodes and creating an open circuit. The combination of blown and unblown links represents a digital bit pattern of ones and zeros signifying data that the user wishes to store in the PROM. By providing an address the data stored on a node may be retrieved during a read operation. [0010] In recent years, a second type of programmable link, call an anti-fuse link, has been developed for use in integrated circuit applications. Instead of the programming mechanism causing an open circuit as in the case with fusible links, the programming mechanism in an anti-fuse circuit creates a short circuit or relatively low resistance link. Thus the anti-fuse link presents an open circuit prior to programming and a low resistance connection after programming. Anti-fuse links consist of two electrodes comprised of conductive and/or semiconductive materials and having some kind of a dielectric or insulating material between them. During programming, the dielectric in between the conductive materials is broken down by predetermined applied voltages, thereby electrically connecting the conducting and/or semiconducting materials together. [0011] Like RAM cells, ROM cells need to store either a data 1 or a data 0. Processing factors, however, may limit the ROM cell to only one program state. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a ROM-embedded-DRAM which can be fabricated with single state ROM cells. SUMMARY OF THE INVENTION [0012] The above-mentioned problems with ROM-embedded-DRAM and other problems are addressed by the present invention and will be understood by reading and studying the following specification. [0013] In one embodiment, a memory device comprises an array of dynamic memory cells and an array of read only memory (ROM) cells. Each dynamic memory cell comprises a storage capacitor having a first plate to store an electrical charge. Each ROM cell comprises a storage capacitor having a first plate coupled to discharge an electrical charge such that the dynamic memory cells retain a charge substantially longer than the ROM cells. [0014] In another embodiment, an integrated circuit ROM embedded DRAM comprises an array of dynamic memory cells and an array of read only memory (ROM) cells. Each dynamic memory cell comprises a storage capacitor having a storage plate coupled to first active area regions of a substrate. The first active area regions and the substrate have opposite electrical doping such that a first substrate leakage current from the first active area regions to the substrate is small to retain a charge on the storage plate. Each ROM cell comprises a storage capacitor having a storage plate coupled to second active area regions of a substrate. The second active area regions are doped such that a second substrate leakage current from the second active area regions to the substrate is greater than the first substrate leakage current to discharge the second storage places substantially faster than the first storage plates. [0015] A method of programming an integrated circuit read only memory (ROM) cell is provided and comprises implanting N+material into a P-substrate to form an active area, implanting a P-type material into the active area to enhance a leakage current from the active area to the substrate, and forming a cell capacitor having a storage plate electrically coupled to the active area. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 is a simplified block diagram of a ROM embedded DRAM of an embodiment of the present invention; [0017] FIG. 2 is a cross-section of a fabrication of a ROM-embedded-DRAM of an embodiment of the present invention; [0018] FIG. 3 is another cross-section of the ROM-embedded-DRAM of FIG. 2; [0019] FIG. 4 illustrates a pair of complementary digit lines of the memory of FIG. 1; Continue reading about Embedded rom device using substrate leakage... Full patent description for Embedded rom device using substrate leakage Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Embedded rom device using substrate leakage patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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