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  Electrostatic discharge protection device and method of fabricating sameRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), With Overvoltage Protective Means, For Protecting Against Gate Insulator Breakdown, In Complementary Field Effect Transistor Integrated CircuitThe Patent Description & Claims data below is from USPTO Patent Application 20070170512. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to the field of integrated circuits; more specifically, it relates to an electrostatic discharge (ESD) protection device for use in integrated circuits fabricated on silicon-on-insulator (SOI) substrates and a method of fabricating the ESD protection device. BACKGROUND OF THE INVENTION [0002] In order to meet increasing performance targets, advanced complimentary metal-oxide-silicon (CMOS) technologies are being scaled down in size to the point that sensitivity to ESD is becoming a significant reliability problem. The use of silicon control rectifiers (SCRs) to protect CMOS technologies built with bulk silicon substrates is known in the industry. However, current SCR-based ESD protection devices suffer from high junction capacitance and current crowding making them unsuitable for CMOS technologies built with SOI substrates. Therefore, there is an ongoing need for an SCR device for electrostatic discharge (ESD) protection in integrated circuits fabricated on silicon-on-insulator (SOI) substrates SUMMARY OF THE INVENTION [0003] A first aspect of the present invention is a silicon control rectifier, comprising: silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane. [0004] A second aspect of the present invention is a silicon control rectifier, comprising: a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; a first doped region in the silicon layer, the first doped region having a first net peak doping concentration, a second doped region having a second net peak doping concentration and a third doped region having a third net peak doping concentration, the second and third net peak doping concentrations being a same doping concentration, the first doped region between and abutting the second and third doped regions, the second and third doped regions not abutting; a fourth doped region in the silicon layer in the silicon layer, the fourth doped region having a fourth net peak doping concentration in the silicon layer, the fourth doped region abutting only the second doped region; a fifth doped region in the silicon layer, the fifth doped region having a fifth net peak doping concentration in the silicon layer, the fifth doped region abutting only the third doped region; wherein a path of current flow from the fourth doped region, through the second doped region, the first doped region and the third doped region to the fifth doped region, is in a single horizontal direction parallel to the horizontal plane. [0005] A third aspect of the present invention is a method of fabricating a silicon control rectifier, comprising: forming a blanket doped region having a net peak doping concentration in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; forming a first doped region in the silicon layer, the first doped region having a first net peak doping concentration, the first doped region dividing the blanket doped region into a second doped region having a second net peak doping concentration and a third doped region having a third net peak doping concentration, the second and third net peak doping concentrations being a same doping concentration, the first doped region between and abutting the second and third doped regions, the second and third doped regions not abutting; forming a fourth doped region in the silicon layer, the fourth doped region having a fourth net peak doping concentration in the silicon layer, the fourth doped region abutting only the second doped region; forming a fifth doped region in the silicon layer, the fifth doped region having a fifth net peak doping concentration in the silicon layer, the fifth doped region abutting only the third doped region; wherein a path of current flow from the fourth doped region, through the second doped region, the first doped region and the third doped region to the fifth doped region, is in a single horizontal direction parallel to the horizontal plane. BRIEF DESCRIPTION OF DRAWINGS [0006] The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: [0007] FIG. 1A is a plan view and 1B is a cross-section through line 1B-1B of FIG. 1A illustrating a first step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; [0008] FIG. 2A is a plan view and 2B is a cross-section through line 2B-2B of FIG. 2A illustrating a second step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; [0009] FIG. 3A is a plan view and 3B is a cross-section through line 3B-3B of FIG. 3A illustrating a third step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; [0010] FIG. 4A is a plan view and 4B is a cross-section through line 4B-4B of FIG. 4A illustrating a fourth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; [0011] FIG. 5A is a plan view and 5B is a cross-section through line 5B-5B of FIG. 5A illustrating a fifth step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention; [0012] FIG. 6 is a schematic diagram of an ESD protection circuit according to an embodiment of the present invention; [0013] FIG. 7A is a plan view and 7B is a cross-section through line 7B-7B of FIG. 7A illustrating the ESD protection circuit of FIG. 5 superimposed over the SCR ESD protection device illustrated in FIGS. 5A and 5B, and [0014] FIG. 8 is a simulated lateral profile of an SCR ESD protection device according to the embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0015] CMOS devices comprise N-channel field effect transistors (NFETs) and P-channel field effect transistors (PFETs). NFETs are fabricated in a P-well with region of the P-well under a gate electrode comprising the channel of the NFET and N-doped source/drains formed in the P-well on either side of gate. PFETs are fabricated in an N-well with region of the N-well under a gate electrode comprising the channel of the PFET and P-doped source/drains formed in the N-well on either side of gate. [0016] FIG. 1A is a plan view and 1B is a cross-section through line 1B-1B of FIG. 1A illustrating a first step in the fabrication of an SCR ESD protection device according to an embodiment of the present invention. In FIG. 1A, a region of shallow trench isolation (STI) 100 having a perimeter 105 surrounds a P-well 110. [0017] In FIG. 1B, it can be seen P-well 110 and STI 100 are formed in a single crystal silicon layer 115. Silicon layer 115 is formed in over a buried oxide layer (BOX) 120. BOX 120 is formed over a bulk silicon substrate 125. Silicon layer 115, BOX 120 and substrate 125 comprise an SOI substrate 130. [0018] BOX 110 may be formed by forming a patterned mask over silicon layer 115, etching away regions of the silicon layer not protected by the patterned mask down to BOX 120, depositing an oxide to back fill the regions of silicon layer etched away and performing a chemical-mechanical polish (CMP) so that a top surface of P-well 110 is coplanar with a top surface of STI 100. The patterned mask, may be a hard-mask, for example, a patterned layer of silicon nitride (Si.sub.3N.sub.4) that itself was patterned using a photolithographic process. Silicon layer 115 may be etched, for example, by reactive ion etching (RIE). [0019] P-well 110 may be formed by ion-implantation of a boron species, in one example, implantation of BF.sub.2. The boron ion-implantation may be performed through a thin oxide layer (not shown in FIG. 1B). In one example, P-well 110 has a peak boron concentration between about 2E18 atoms/cm.sup.3 and about 7E18 atoms/cm.sup.3. A peak dopant concentration is the highest concentration of a dopant within a given region. Continue reading... Full patent description for Electrostatic discharge protection device and method of fabricating same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Electrostatic discharge protection device and method of fabricating same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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