Electronic digital logic circuitry inventions

20080100335 - Apparatus and method for determining on die termination modes in memory device: For determining an on die termination (ODT) mode in a semiconductor memory device, a first mode determining unit determines whether or not a normal ODT mode is enabled from performing a logic operation on a first set of signals. A second mode determining unit determines whether or not a dynamic... Agent: Law Office Of Monica H Choi

20080100334 - Impedance matching circuit and semiconductor memory device with the same: An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance... Agent: Mcdermott Will & Emery LLP

20080100333 - Impedance matching circuit of semiconductor memory device: An impedance matching circuit reduces current consumption during ZQ calibration in the present invention. The impedance matching circuit includes a reference voltage generator, a code generator, a first pull-up resistance unit, a second pull-up resistance unit and a pull-down resistance unit. The reference voltage generator generates a reference voltage. The... Agent: Mcdermott Will & Emery LLP

20080100337 - Memory circuit, semiconductor device and read control method of memory circuit: A memory circuit of the invention comprises N look-up tables for implementing a desired logic function of L inputs/M outputs by partitioning a memory cell array including a plurality of memory cells into portions each corresponding to at least a predetermined number of input/output paths; a decode circuit for selecting... Agent: Mcginn Intellectual Property Law Group, PLLC

20080100340 - Low voltage complementary metal oxide semiconductor process tri-state buffer: A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second control signal. The biasing device receives the first... Agent: Rabin & Berdo, PC

20080100341 - Level shifter having single voltage source: Embodiments relate to a level shifter which uses a single voltage source, has an excellent operation characteristic even when a difference between a low voltage and a high voltage is large, and can be easily designed. Embodiments relate to a level shifter for shifting a voltage level between an input... Agent: Sherr & Nourse, PLLC

20080100342 - Circuit arrangement comprising a level shifter and method: A circuit arrangement includes a first level shifter, an output stage, and a feedback circuit. The first level shifter is coupled to receive an input signal having a first voltage level from an input terminal, and is configured to provide a level-shifted signal having a second voltage level higher than... Agent: Maginot, Moore & Beck Chase Tower

20080100343 - Source driver and level shifting apparatus thereof: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus comprises a level shifter and an asynchronous dynamic control circuit. The level shifter has a first switch and connected to a high power supply voltage source via the first switch, wherein the level... Agent: Lowe Hauptman Ham & Berner, LLP

20080100344 - Scannable dynamic logic latch circuit: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to... Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C.

20080100336 - Hybrid logic/interconnect circuit in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic... Agent: Adeli & Tollen, LLP

20080100338 - Logic circuit apparatus: A logic circuit apparatus includes a plurality of programmable logic circuits, a circuit data memory, a control unit. The plurality of programmable logic circuits are each configured to have a changeable circuit component based on circuit data. Each programmable logic circuit has a different processing performance. The circuit data memory... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080100339 - Configurable ic with routing circuits with offset connections: Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a... Agent: Adeli & Tollen, LLP

20080100345 - Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays: Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so... Agent: Hewlett Packard Company

20080094099 - Differential line compensation apparatus, method and system: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition... Agent: Slater & Matsil LLP

20080094102 - Reprogrammable instruction dsp: A software programmable DSP with a field programmable instruction set is described where customized instructions can be created, or certain existing instructions can be modified, at the user's location after taking delivery of the processor. The FPGA fabric used to implement the reprogrammable instructions is restricted to supporting the software-programmable... Agent: Schwabe, Williamson & Wyatt, P.C. Pacwest Center, Suite 1900

20080094103 - Programmable multiplexer: An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer... Agent: Silicon Valley Patent Group LLP Attn: Bryan H. Wyman

20080094105 - Programmable multiple supply regions with switched pass gate level converters: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage... Agent: Martine Penilla & Gencarella, LLP

20080094106 - Apparatus for configuring i/o signal levels of interfacing logic circuits: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage... Agent: Hewlett Packard Company

20080094100 - Adjustable transistor body bias generation circuitry with latch-up prevention: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe... Agent: G. Victor Treyz

20080094101 - Programmable system on a chip for power-supply voltage and current monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring,... Agent: Sierra Patent Group, Ltd.

20080094104 - High speed double data rate jtag interface: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal... Agent: Texas Instruments Incorporated

20080088339 - Hard macro with configurable side input/output terminals, for a subsystem: A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical output terminal (COT)... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080088340 - Miller capacitance tolerant buffer element: A buffer includes a source follower module and a pull-up/pull-down module that is connected to the source follower module. An output signal at the output terminal of the source follower module follows an input signal at the input terminal with a predetermined delay, independent of the Miller capacitance. The pull-up/pull-down... Agent: Freescale Semiconductor, Inc. Law Department

20080088341 - Level shifter circuit: A level shifter circuit for ensuring a high impedance state even in a transitional period such as when activating an external power supply while reducing power consumption. A latch circuit is set to a low level by a set circuit when a high potential power supply voltage increases. When the... Agent: Freescale Semiconductor, Inc. Law Department

20080088338 - Semiconductor memory device for adjusting impedance of data output driver: A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the... Agent: Mcdermott Will & Emery LLP

20080088342 - Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications: A digital data transmitting device is disclosed having differential signaling circuitry, a current source controller and a pair of transistor-implemented current sources is disclosed. The current source controller generates a current source control signal based on a detected mode of operation of the differential signaling circuitry. The pair of transistor-implemented... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20080088343 - Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability: Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability, is provided and described. In one embodiment, switches are set to a first switch position to operate the repeater circuit in the high performance repeater mode. In another embodiment, switches... Agent: Murabito, Hao & Barnes LLP

20080088344 - Automatic extension of clock gating technique to fine-grained power gating: A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The... Agent: Macpherson Kwok Chen & Heid LLP

20080088345 - Quad state logic design methods, circuits, and systems: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.... Agent: Texas Instruments Incorporated

20080084231 - Method for implementing level shifter circuits and low power level shifter circuits for integrated circuits: A low power level shifter circuit for integrated circuits, and a design structure on which the subject circuit resides are provided. The low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a... Agent: Ibm Corporation Rochester Ip Law Dept 917

20080084230 - Interconnect structure enabling indirect routing in programmable logic: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in... Agent: Gardere Wynne Sewell LLP Intellectual Property Section