|Electronic digital logic circuitry patents - Monitor Patents|
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Electronic digital logic circuitryBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 08/07/2014 > 4 patent applications in 4 patent subcategories.
20140218067 - Grouping of physically unclonable functions: A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits... Agent: Intel Corporation
20140218068 - Hardened programmable devices: Hardened programmable logic devices are provided with programmable circuitry. The programmable circuitry may be hardwired to implement a custom logic circuit. Generic fabrication masks may be used to form the programmable circuitry and may be used in manufacturing a product family of hardened programmable logic devices, each of which may... Agent: Altera Corporation
20140218069 - Multi-supply sequential logic unit: Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate... Agent:
20140218070 - Voltage translator: A voltage translator translates an input voltage signal in a low voltage domain into a output voltage signal in a high voltage domain using a latch that includes a pair of cross-coupled inverters. The bottom rail voltages for the cross-coupled inverters are varied dynamically to speed switching time for the... Agent: Qualcomm Incorporated07/31/2014 > 4 patent applications in 4 patent subcategories.
07/24/2014 > 4 patent applications in 4 patent subcategories.
20140203838 - Quantum processor: One embodiment of the invention includes a quantum processor system. The quantum processor system includes a first resonator having a first characteristic frequency and a second resonator having a second characteristic frequency greater than the first characteristic frequency. A qubit cell is coupled to each of the first resonator and... Agent: Northrop Grumman Systems Corporation
20140203839 - Dynamic adaptation of continuous time linear equalization circuits: An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited... Agent:
20140203840 - Circuit and method of driving the same: In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140203841 - Systems and methods for reduced coupling between digital signal lines: Methods and systems are disclosed for reduced coupling between digital signal lines. For disclosed embodiments, return-to-zero signaling is dynamically blocked so that high logic levels remain high through entire clock cycles where the next data to be output is also at high logic levels. The dynamically blocked return-to-zero signaling reduces... Agent:07/17/2014 > 2 patent applications in 2 patent subcategories.
20140197863 - Placement of storage cells on an integrated circuit: A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the... Agent: International Business Machines Corporation
20140197864 - Non-volatile latch structures with small area for fpga: A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch... Agent:Previous industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
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