|Electronic digital logic circuitry patents - Monitor Patents|
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Electronic digital logic circuitryBelow are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 11/13/2014 > 2 patent applications in 2 patent subcategories.
20140333344 - Adaptive interface for coupling fpga modules: A method for implementing an adaptive interface between at least one FPGA with at least one FPGA application and at least one I/O module, which are designed as the corresponding sender side or receiver side, for connection to the FPGA, whereby a serial interface is formed between the at least... Agent: Dspace Digital Signal Processing And Control Engineering Gmbh
20140333345 - Configurable storage elements: Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably... Agent: Tabula, Inc.11/06/2014 > 4 patent applications in 3 patent subcategories.
20140327468 - Physical unclonable function generation and management: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In preferred systems, differentials of PUFs are employed to minimize sensitivity to temperature variations as well as other factors that affect the reliability of PUF states. In particular, a PUF system can include... Agent: International Business Machines Corporation
20140327469 - Physical unclonable function generation and management: Methods, systems and devices related to authentication of chips using physical physical unclonable functions (PUFs) are disclosed. In accordance one such method, a test voltage is applied to a PUF system including a first subset of PUF elements that are arranged in series and a second subset of PUF elements... Agent: International Business Machines Corporation
20140327470 - Field programmable gate array utilizing two-terminal non-volatile memory: A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first... Agent:
20140327471 - Standard cells for predetermined function having different types of layout: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.10/30/2014 > 7 patent applications in 6 patent subcategories.
20140320164 - Fast dynamic register with transparent latch: A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first... Agent: Via Technologies, Inc.
20140320165 - Runtime loading of configuration data in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While... Agent: Tabula, Inc.
20140320166 - Field programmable gate array utilizing two-terminal non-volatile memory: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections... Agent: Crossbar, Inc.
20140320167 - Level conversion circuit and level-conversion-function-equipped logic circuit: A level conversion circuit (10) includes an EFET (11), a diode (12) and resistors (13, 14). The drain of the EFET (11) is connected to an output terminal of the level conversion circuit (10). The drain and the gate of the EFET (11) are in conductive contact with each other.... Agent:
20140320168 - Level shifter circuit and operation method thereof: A level shifter transfers a first voltage signal to a second voltage signal. The level shifter comprises a comparison circuit, a delay circuit, and a selection circuit. The comparison circuit generates a first signal according to the comparison result between the first voltage signal and the reverse-phase signal of the... Agent: Industrial Technology Research Institute
20140320169 - Circuit for reducing negative bias temperature instability: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output... Agent:
20140320170 - Glitch free clock multiplexer: Apparatus for glitch-free switching between two clock sources on an integrated circuit. Clock gaters provide a clock from a single source that can be turned on and off without causing partial pulses to be created. Control circuitry going to the individual clock gaters provides the ability to shut all clocks... Agent:10/23/2014 > 6 patent applications in 5 patent subcategories.
20140312927 - Terminating resistance generation device for differential input mode communication and differential input mode communication device: Disclosed are a terminating resistance generation device for differential input mode communication and a differential input mode communication device. The terminating resistance generation device for differential input mode communication according to the present invention includes: a first circuit unit including a first ground terminal and operating only when the first... Agent:
20140312928 - High-speed current steering logic output buffer: A current steering logic buffer for generating an output clock signal, comprises: a buffer for receiving an input clock signal; a current source; switches controlled by the buffer, wherein the switches connect the current source to outputs for generating the output clock signal; and a feedback loop for controlling the... Agent: Kool Chip, Inc.
20140312929 - Self-recovering bus signal detector: A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a... Agent: Atmel Corporation
20140312930 - Semiconductor device, semiconductor system including the semiconductor device, and method for driving the semiconductor system: A semiconductor device includes a plurality of pads, a plurality of data input/output units connected with the plurality of pads and enabled in response to a plurality of enable signals, and a group programming unit suitable for grouping the plurality of pads into a number of pad groups in response... Agent: Sk Hynix Inc.
20140312932 - Storage device and semiconductor device: A low-power storage device is provided. The storage device includes a first transistor, a second transistor, a logic element, and a semiconductor element. The second transistor controls supply of a first signal to a gate of the first transistor. When the potential of a second signal to be input is... Agent: Semiconductor Energy Laboratory Co., Ltd.
20140312931 - System and method for stationary finite impulse response filters in programmable microelectronic circuits: A Field Programmable Gate Array (FPGA) to implement channel equalization to mitigate group velocity dispersion in an optical system. In one embodiment, a mapping is loaded into the FPGA whereby the in-phase and quadrature components of the baseband sequence to be filtered are routed to accumulators to form various sums,... Agent: Ciena CorporationPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
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