Electronic digital logic circuitry inventions

20090267635 - Method and apparatus for high density superconductor circuit: The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical... Agent: Snell & Wilmer L.L.P. (grumman)

20090267636 - Security circuit having an electrical fuse rom: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.... Agent: Mills & Onello LLP

20090267637 - Device and method for testing a resistance value of on-die-termination device and semiconductor device having the same: A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference... Agent: Ladas & Parry LLP

20090267638 - Apparatus, system and method of power state control: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has... Agent: Texas Instruments Incorporated

20090267641 - I/o driver for integrated circuit with output impedance control: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for... Agent: Thorne & Halajian, LLP

20090267639 - Input cancellation circuit: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein... Agent: Kenyon & Kenyon LLP

20090267642 - Method and apparatus for output driver calibration, and memory devices and system embodying same: A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average... Agent: Trask Britt, P.C./ Micron Technology

20090267640 - System including preemphasis driver circuit and method: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal... Agent: Dicke, Billig & Czaja

20090267643 - Flexible adder circuits with fast carry chain circuitry: Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal... Agent: Treyz Law Group

20090267644 - Semiconductor integrated circuit: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal... Agent: Turocy & Watson, LLP

20090267645 - Passgate structures for use in low-voltage applications: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the... Agent: Ropes & Gray LLP

20090267646 - Nano-electron fluidic logic (nfl) device: A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals at which the SPWs... Agent: John Alumit

20090267647 - Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube... Agent: Harness, Dickey & Pierce, P.L.C

20090267648 - Apparatus for configuring i/o signal levels of interfacing logic circuits: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage... Agent: Hewlett-packard Company Intellectual Property Administration

20090267649 - Clock gating system and method: A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that... Agent: Qualcomm Incorporated

20090261856 - Circuit and method for controlling termination impedance: A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an... Agent: Mannava & Kang, P.C.

20090261858 - Programmable interconnect network for logic array: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect... Agent: Buchanan, Ingersoll & Rooney PC

20090261857 - Universal non-volatile support device for supporting reconfigurable processing systems: A universal support device for supporting a reconfigurable electronics device is disclosed. The universal support device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines... Agent: Bae Systems

20090261859 - Receiver circuitry for receiving reduced swing signals from a channel: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20090261860 - Electronic circuit: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS)... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090256585 - Data line termination circuit: A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal.... Agent: Ladas & Parry LLP

20090256586 - Semiconductor device and impedance adjustment method of the same: A 4-bit counter outputs a 4-bit counted value CNTp based on an up-and-down signal Sp supplied from a comparator. A weighting selection circuit performs weighting based on a deviation from an average value of the DC characteristic of each PMOS transistor, and assigns a transistor having the smallest deviation to... Agent: Nec Corporation Of America

20090256587 - Semiconductor memory device: In a semiconductor memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the... Agent: Young & Thompson

20090256588 - Programmable array logic circuit employing non-volatile ferromagnetic memory cells: A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no... Agent: Morgan Lewis & Bockius LLP

20090256589 - Programmable device, electronic device, and method for controlling programmable device: A programmable device connected to a storage unit which stores logic circuit configuration information to form a logic circuit and control circuit configuration information to form a control circuit includes a first programmable logic device and a second programmable logic device, and a configuration unit which forms the control circuit... Agent: Nec Corporation Of America

20090256590 - Storage element for controlling a logic circuit, and a logic device having an array of such storage elements: The present invention is a storage element for controlling a logic circuit and a logic device having a plurality of storage elements. The storage element has a first and a second non-volatile memory cells connected in series at an output node Each of the first and second non-volatile memory cells... Agent: Dla Piper LLP (us )

20090256591 - Structure for systems and methods of managing a set of programmable fuses on an integrated circuit: Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.... Agent: Jerome D. Jackson (jackson Patent Law Office)

20090256592 - Signal driver circuit having adjustable output voltage for a high logic level output signal: A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20090256593 - Programmable sample clock for empirical setup time selection: A system and method for efficient improvement of timing analysis for faster processor designs with negligible impact on die-area. Rather than provide a single clock to flip-flop circuits on a semiconductor chip, split clocks are used. A flip-flop receives a master clock signal for a master latch and receives a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090256594 - Nanoelectromechanical digital inverter: A digital inverter formed by three carbon nanotubes (CNTs) extending vertically from a substrate, one CNT functioning as first source (S1) and having a first logic signal applied to it, another CNT functioning as second source (S2) and having a second logic signal applied to it, a third CNT functioning... Agent: International Business Machines Corporation Dept. 18g

20090251168 - Device for protecting an integrated circuit against a laser attack: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20090251169 - Integration of lbist into array bisr flow: A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090251170 - Semiconductor device with its test time reduced and a test method therefor: In a semiconductor device, when a voltage regulator is halted from operating and a test supply voltage is supplied to second logics, the device is initialized by a reset signal. A register included in the device is then reset by an input signal via first logics. The voltage regulator is... Agent: Studebaker & Brackett PC

20090251171 - Methods and apparatus for monitoring power gating circuitry and for controlling circuit operations in dependence on monitored power gating conditions: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency.... Agent: Harrington & Smith, PC

20090251172 - Single electron based flexible multi-functional logic circuit and the transistor thereof: The present invention relates to a flexible multi-functional logic circuit which switches a current direction to a serial or parallel direction using at least two single electron transistors (SETs) having the same pattern and as many field effect transistors (FETs) as the number of the single electron transistors and performs... Agent: Hiscock & Barclay, LLP

20090251173 - Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains: A circuit comprises first, second, third, and fourth transistors. The first transistor has a first current electrode, a control electrode for receiving an input signal, and a second current electrode. The second transistor has a first current electrode coupled to the second current electrode of the first transistor for providing... Agent: Freescale Semiconductor, Inc. Law Department