Electronic digital logic circuitry inventions

20090278564 - Reconfigurable integrated circuit and method for increasing performance of a reconfigurable integrated circuit: Methods are disclosed to increase yielded performance of a reconfigurable integrated circuit; improve performance of an application running on a reconfigurable integrated circuit; reduce degradation of an integrated circuit over time; and maintain performance of an integrated circuit time.... Agent: Steinfl & Bruno

20090278565 - Calibration methods and circuits to calibrate drive current and termination impedance: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing... Agent: Silicon Edge Law Group, LLP

20090278566 - Configurable time borrowing flip-flops: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second... Agent: Treyz Law Group

20090278567 - Semiconductor digital circuit, fifo buffer circuit, and data transferring method: A FIFO buffer circuit is provided which, in data transmission between two circuit areas having different combinations of a power supply voltage and an operation clock frequency, can perform a voltage level conversion and a clock rate conversion at the same place at the same time. In an input side... Agent: Young & Thompson

20090278568 - Method and system to reduce electromagnetic radiation from semiconductor devices: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal... Agent: Texas Instruments Incorporated

20090278569 - Semiconductor device and its manufacturing method, semiconductor manufacturing mask, and optical proximity processing method: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined... Agent: Mcdermott Will & Emery LLP

20090278570 - Circuit configurations having four terminal jfet devices: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.... Agent: Haverstock & Owens LLP

20090273361 - Localized calibration of programmable digital logic cells: An integrated circuit (IC) includes self-calibrating programmable digital logic circuitry. The IC includes at least one programmable digital logic cell, wherein the first programmable digital logic cell provides (i) a plurality of different accessible circuit configurations or (ii) a voltage level controller. A self-calibration system is provided that includes at... Agent: Texas Instruments Incorporated

20090273362 - Booster circuits for reducing latency: A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored... Agent: Dorsey & Whitney LLP On Behalf Of Sun Microsystems, Inc.

20090273363 - Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device: Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate... Agent: Mannava & Kang, P.C.

20090273364 - Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit: Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit configured to count a clock and allow the calibration unit to be enabled during a... Agent: Mannava & Kang, P.C.

20090273365 - Data input/output multiplexer of semiconductor device: There is provided an input/output multiplexer capable of reducing a layout area in designing a device by disposing first and second multiplexers at either side of a specific data input/output (I/O) pad. An apparatus for multiplexing data inputted or outputted to a global input/output (I/O) line includes a first multiplexer... Agent: Mannava & Kang, P.C.

20090273367 - Ic having programmable digital logic cells: An integrated circuit (IC) includes at least one programmable digital logic cell that includes first dedicated digital logic cell having a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor configured to perform at least one digital logical function. The first dedicated digital logic... Agent: Texas Instruments Incorporated

20090273366 - Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system: A semiconductor integrated circuit 1 judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit 1, when the power unit is performing the charge operation, the semiconductor integrated circuit 1 determines... Agent: Wenderoth, Lind & Ponack L.L.P.

20090273368 - Scalable non-blocking switching network for programmable logic: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications,... Agent: Daniel E. Ovanezian Blakely, Sokoloff, Taylor & Zafman LLP

20090273369 - Gtl backplane bus with improved reliability: Isolation components such as p-n junction or Schottky diodes are provided at pull-up resistors of each signal line of a Gunning Transceiver Logic (GTL) backplane bus in an electronic system for improved reliability, specifically to prevent momentary termination of the bus to ground when a circuit card incorporating the pull-up... Agent: Kramer & Amado, P.C.

20090273370 - Muller-c element: The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans-conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090267635 - Method and apparatus for high density superconductor circuit: The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (Ic1) and the second Josephson junction having a second critical... Agent: Snell & Wilmer L.L.P. (grumman)

20090267636 - Security circuit having an electrical fuse rom: A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed.... Agent: Mills & Onello LLP

20090267637 - Device and method for testing a resistance value of on-die-termination device and semiconductor device having the same: A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference... Agent: Ladas & Parry LLP

20090267638 - Apparatus, system and method of power state control: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has... Agent: Texas Instruments Incorporated

20090267641 - I/o driver for integrated circuit with output impedance control: An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for... Agent: Thorne & Halajian, LLP

20090267639 - Input cancellation circuit: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein... Agent: Kenyon & Kenyon LLP

20090267642 - Method and apparatus for output driver calibration, and memory devices and system embodying same: A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average... Agent: Trask Britt, P.C./ Micron Technology

20090267640 - System including preemphasis driver circuit and method: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal... Agent: Dicke, Billig & Czaja

20090267643 - Flexible adder circuits with fast carry chain circuitry: Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal... Agent: Treyz Law Group

20090267644 - Semiconductor integrated circuit: A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal... Agent: Turocy & Watson, LLP

20090267645 - Passgate structures for use in low-voltage applications: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the... Agent: Ropes & Gray LLP

20090267646 - Nano-electron fluidic logic (nfl) device: A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals at which the SPWs... Agent: John Alumit

20090267647 - Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics: A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube... Agent: Harness, Dickey & Pierce, P.L.C

20090267648 - Apparatus for configuring i/o signal levels of interfacing logic circuits: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage... Agent: Hewlett-packard Company Intellectual Property Administration

20090267649 - Clock gating system and method: A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that... Agent: Qualcomm Incorporated

20090261856 - Circuit and method for controlling termination impedance: A calibration circuit that can prevent a calibration operation from being delayed by a dummy capacitor when the calibration circuit starts to operate includes a switch unit configured to connect a calibration node to a precharge node in response to an enable signal. The calibration node is connected to an... Agent: Mannava & Kang, P.C.

20090261858 - Programmable interconnect network for logic array: A programmable interconnect network for an array of logic cells. Said interconnect network has a plurality of switch boxes being connected in a tree structure and providing connections to its logic cells, switch boxes located at the lowest level of the tree structure are connected to logic cells; said interconnect... Agent: Buchanan, Ingersoll & Rooney PC

20090261857 - Universal non-volatile support device for supporting reconfigurable processing systems: A universal support device for supporting a reconfigurable electronics device is disclosed. The universal support device includes an application specific integrated circuit (ASIC) module coupled to multiple non-volatile memory devices. The ASIC module is capable of interfacing with an external reconfigurable electronics device via a set of load/read-back interface lines... Agent: Bae Systems

20090261859 - Receiver circuitry for receiving reduced swing signals from a channel: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20090261860 - Electronic circuit: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS)... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing