Electronic digital logic circuitry patents - Monitor Patents
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents



USPTO Class 326  |  Browse by Industry: Previous - Next | All     monitor keywords
Recent  |  14:  | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 13: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan |  | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn |  | 2008 | 2007 |

Electronic digital logic circuitry

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
10/02/2014 > 8 patent applications in 7 patent subcategories.

20140292367 - Protecting quantum entanglement from amplitude damping in a two qubit system: Preservation of quantum entanglement in a two-qubit system is achieved by use of the disclosed systems. Three different example two-qubit systems are shown: (1) a system employing a weak measurement, (2) a system in which a generalized amplitude dampening occurs without use of a weak measurement, and (3) an extended... Agent: Texas A&m University System

20140292368 - Field programmable gate array utilizing two-terminal non-volatile memory: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections... Agent:

20140292369 - Field-programmable gate array: An FPGA has a number of CLBs, each CLB having a number of CABs (10, 110, 210, 310, 410). Each CAB (10, 110, 210, 310, 410) comprises: a number of configurable transistors (20, 120, 220, 320, 420) each comprising one or more useable transistors M and a number of switching... Agent:

20140292370 - Synchronous input signal capture system: A synchronous digital signal capture system includes a first flip-flop and a synchronization module. The first flip-flop receives a logic control signal and a first clock signal having a first frequency. The first flip-flop is configured to output a synchronized data signal based on the logic control, and generate a... Agent: Hamilton Sundstrand Corporation

20140292372 - Low power clock gating circuit: A clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal includes: a first plurality of transistors for receiving at least the logic enable signal and generating a first output; a second plurality of transistor for receiving at least... Agent: Mediatek Singapore Pte. Ltd.

20140292371 - Multi-threshold dual-spacer dual-rail delay-insensitive logic (mtd3l) circuit design: A Multi-Threshold Dual-spacer Dual-rail Delay-insensitive Logic (MTD3L) circuit architecture. The architecture includes a first th22 circuit, a second th22 circuit, and an XNOR gate. The first th22 circuit is configured to receive a first rail input, a completion detection signal, and a reset signal, and to produce a first rail... Agent:

20140292373 - Ternary t arithmetic circuit: A ternary T arithmetic circuit, including: a logic 0 gate circuit, a logic 1 gate circuit, and a logic 2 gate circuit. The logic 0 gate circuit includes: a first PMOS, a second PMOS, a third PMOS, a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and... Agent: Ningbo University

20140292374 - Method for controlling an integrated circuit: A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and fourth FETs, which are pMOS and nMOS respectively. The clock-tree cell provides a clock signal to the... Agent:

  
09/25/2014 > 7 patent applications in 4 patent subcategories.

20140285232 - Methods and systems for reducing supply and termination noise: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes... Agent: Rambus Inc.

20140285231 - Semiconductor device and trimming method for the same: According to one embodiment, a semiconductor device includes a termination circuit and a controller. The termination circuit includes a first resistor connected to an external connection terminal, a plurality of first transistors of a first conductive type connected in parallel between the first resistor and a voltage source, a second... Agent: Kabushiki Kaisha Toshiba

20140285233 - Efficient reconfigurable logic tile: An application specific integrated circuit (ASIC) that includes a digital signal processing (DSP) core and a configurable logic block coupled to the DSP core. The configurable logic block including a plurality of interconnected logic modules to apply a pre-configured logic function to an input. Each of the plurality of logic... Agent: Texas Instrument Incorporated

20140285234 - Semiconductor device: To provide a charge pump circuit to manufacture a low-power-consumption PLD. A semiconductor device includes a first circuit and a second circuit electrically connected to the first circuit. A charge pump circuit formed of a transistor including an oxide semiconductor and a boosting control circuit controlling the charge pump circuit... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140285235 - Programmable logic device and semiconductor device: A programmable logic device that includes a storage device having smaller area and lower power consumption is provided. The programmable logic device includes a logic block including a storage device. The storage device includes a plurality of groups each including at least a first switch, a transistor that is turned... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140285236 - Flip-flop circuit with resistive poly routing: A latch circuit has a tri-state gate and a reverse tri-state gate that share the same complementary controls. The reverse tri-state gate locks an output of the tri-state gate when the tri-state gate is shut-off. The complementary control signals include a first undoped polysilicon strip. The output of the reverse... Agent:

20140285237 - Tri-state driver circuits having automatic high-impedance enabling: Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The... Agent:

  
09/18/2014 > 10 patent applications in 9 patent subcategories.

20140266296 - Reconfigurable multi-port physical unclonable functions circuit: A reconfigurable multi-port physical unclonable functions (RM-PUFs) circuit, including: an input signal interface, a first control circuit module, at least two RM-PUFs circuit units, and an output signal interface. Each RM-PUFs circuit unit includes a second control circuit module, an input module, an output module, and a deviation generation module.... Agent: Ningbo University

20140266297 - Hardware-embedded key based on random variations of a stress-hardened inegrated circuit: An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a... Agent:

20140266299 - Circuit and method for on-die termination, and semiconductor memory device including the same: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code,... Agent: Samsung Electronics Co., Ltd.

20140266298 - Termination circuits capable of receiving data signals in different formats for performing impedance matching: A termination circuit is provided. The termination circuit includes a first receiving terminal, a second receiving terminal, a first resistive device, a second resistive device, a third resistive device, a fourth resistive device and a first switch. The first receiving terminal receives a first data signal. The second receiving terminal... Agent: Mediatek Inc.

20140266300 - Phase-change material reconfigurable circuits: One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first... Agent: Northrop Grumman Systems Corporation

20140266301 - Programmable logic device: A programmable logic device that verifies whether configuration data is stored correctly is provided. The programmable logic device includes a configuration memory storing configuration data input to a first wiring and a switch controlling conduction or non-conduction between a second wiring and a third wiring in accordance with the configuration... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140266302 - Elements to counter transmitter circuit performance limitations: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver,... Agent:

20140266303 - Pipelining of clock guided logic using latches: This application discloses the technique to pipeline the Clock Guided Logic. Latch based storage elements are used in CGL based design such that when first stage CGL elements are in precharge phase the second stage CGL elements are in evaluate phase and vice-versa resulting into higher design throughput.... Agent:

20140266304 - Shift register circuit: A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140266305 - Semiconductor device: A semiconductor device having a power-saving circuit. The semiconductor device includes an input-output terminal and a holding circuit. When the input-output terminal is used, an inverter loop of the holding circuit is made not to operate by controlling a switch, and when the input-output terminal is not used, the inverter... Agent: Semiconductor Energy Laboratory Co., Ltd.

  
09/11/2014 > 6 patent applications in 3 patent subcategories.

20140253173 - Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the... Agent: Qualcomm Incorporated

20140253174 - Logic circuit: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND... Agent: Semiconductor Energy Laboratory Co., Ltd.

20140253175 - System, method, and computer program product for automatic two-phase clocking: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and... Agent: Nvidia Corporation

Previous industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems


######

RSS FEED for 20141002: xml
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.

######

Thank you for viewing Electronic digital logic circuitry patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electronic digital logic circuitry patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electronic digital logic circuitry patents we recommend signing up for free keyword monitoring by email.



Results in 0.12829 seconds

PATENT INFO