Electronic digital logic circuitry patents - Monitor Patents
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Electronic digital logic circuitry

Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application.
  
04/16/2015 > 4 patent applications in 3 patent subcategories.

20150102836 - Pld editor and method for editing pld code: A PLD editor and method for editing PLD code to be programmed into a PLD are provided. The PLD editor includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block... Agent: Rockwell Automation Technologies, Inc.

20150102837 - Semiconductor device including an arbiter cell: A semiconductor device is implemented with a technology for removing a command bubbling generated when performing a rank-to-rank switching on chips that are stacked and interconnected through a through silicon via (TSV). The semiconductor device includes a first memory, a second memory stacked over the first memory to input/output data... Agent: Sk Hynix Inc.

20150102838 - Semiconductor device and method for detecting state of input signal of semiconductor device: A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission unit suitable for selectively transmitting the input signal in response to the detection signal, wherein the signal detection unit... Agent: Sk Hynix Inc.

20150102839 - Low power inverter circuit: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and... Agent: Freescale Semiconductor, Inc.

  
04/09/2015 > 1 patent applications in 1 patent subcategories.

20150097595 - Logic circuit and semiconductor device: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per... Agent:

  
04/02/2015 > 10 patent applications in 9 patent subcategories.

20150091607 - Sequential logic circuit and method of providing setup timing violation tolerance therefor: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged... Agent: Freescale Semiconductor, Inc.

20150091608 - Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces: An input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a supply detector cell that detects a core supply voltage and generates a supply detect signal. A driver circuit is connected to a PAD and the driver circuit receives the supply detect signal. A failsafe... Agent:

20150091609 - Integrated circuit with signal assist circuitry and method of operating the circuit: An integrated circuit has signal assist circuitry for assisting with pulling a signal on the signal line towards the logical low or high signal level. The signal assist circuitry comprises first and second assist circuits. The first assist circuit couples the signal line to the logical high signal level following... Agent: Arm Limited

20150091610 - Self-leveling logic receiver: Various implementations include circuits, devices and/or methods that provide closed-loop feedback crowbar current limiting for logic level-shifting between circuits with different voltage supplies. Some implementations include a level-shift circuit assembly including an input buffer and a current limiter. The input buffer is configured to receive an incoming logic signal that... Agent:

20150091611 - Impedance calibration circuits: Impedance calibration circuits are provided. The impedance calibration circuit includes an operation control signal generator and an impedance calibrator. The operation control signal generator receives temperature code signals to generate an operation control signal enabled when an internal temperature is changed from a first temperature to a second temperature. The... Agent: Sk Hynix Inc.

20150091612 - Noise elimination circuit of semiconductor apparatus: A semiconductor apparatus includes a pulse generation unit configured to detect a transition of an input signal and generate a preliminary pulse signal, and an error elimination unit configured to determine error of the preliminary pulse signal and output a signal as a pulse signal.... Agent: Sk Hynix Inc.

20150091613 - Flexible logic unit: A flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a bit... Agent: Scaleo Chip

20150091614 - Robust flexible logic unit: A robust flexible logic unit (FLU) is targeted to be primarily, but not exclusively, used as an embedded field programmable gate array (EFPGA). The unit is comprised of a plurality of programmable building block tiles arranged in an array of columns and rows of tiles, and programmed by downloading a... Agent:

20150091615 - Embedded non-volatile memory circuit for implementing logic functions across periods of power disruption: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML... Agent: Radiant Technologies, Inc.

20150091616 - Technique to realize high voltage io driver in a low voltage bicmos process: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and... Agent: Texas Instruments Incorporated

  
03/26/2015 > 4 patent applications in 4 patent subcategories.

20150084670 - Sonos fpga architecture having fast data erase and disable feature: A method for fast data erasing an FPGA including a programmable logic core controlled by a plurality of SONOS configuration memory cells, each SONOS configuration memory cell including a p-channel SONOS memory transistor in series with an n-channel SONOS memory transistor, which includes detecting tampering with the FPGA, disconnecting power... Agent:

20150084671 - Reprogrammable logic device resistant to radiations: The invention relates to a reprogrammable logic device comprising a plurality of elementary patches, each patch comprising: at least one logic block configurable by one or more volatile memory cells storing configuration data; and a memory comprising: a plurality of non-volatile memory cells storing refresh data, each non-volatile memory cell... Agent:

20150084672 - Command-triggered on-die termination: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response... Agent:

20150084673 - Margin improvement for configurable local clock buffer: A timing margin circuit of a local clock buffer circuit may include an inverter logic gate having an inverter input and an inverter output, whereby the inverter input receives an input clock signal. A NAND logic gate includes a first NAND input coupled to the inverter output, a second NAND... Agent: International Business Machines Corporation

Previous industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems


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