SEARCH:      Monitor Keywords |  Custom RSS

Electronic digital logic circuitry May archived by USPTO category 05/11

20110121856 - System and method for detecting soft-fails: A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only... Agent: Taiwan Semiconductor Manufacturing Company, Ltd.

20110121857 - Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks: Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and one data output. A mutual exclusion element is used to select the first-arriving data request from one of the two inputs to the output. A asynchronous... Agent: The Trustees Of Columbia University In The City Of New York

20110121858 - Buffer apparatus, integrated circuit and method of reducing a portion of an oscillation of an output signal: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein... Agent:

20110121859 - Method and system for improved phase noise in a bicmos clock driver: System and method for a clock driver. An input taking circuit is used for receiving small-signal logic inputs. A voltage follower circuit is coupled to the input taking circuit and used to generate a set of voltage follower outputs. An output circuit is coupled to the voltage follower circuit to... Agent: Linear Technology Corporation

20110121860 - Semiconductor device: A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than... Agent:

20110121861 - Multivalued logic circuit: In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected... Agent:

20110121862 - Circuit with stacked structure and use thereof: An NAND circuit has a stacked structure having at least one symmetric NFET at a bottom of the stack. More particularly, the circuit has a stacked structure which includes an asymmetric FET and a symmetric FET. The symmetric FET is placed at the bottom of the stacked structure closer to... Agent: International Business Machines Corporation

20110115521 - Deactivation of integrated circuits: Integrated circuits and methods of permanently disabling integrated circuits are disclosed. An integrated circuit having an erasable non-volatile memory adapted to store an activation code and logic to disable the integrated circuit when the code in the erasable non-volatile memory has been altered or erased after it has been separated... Agent:

20110115522 - Magnetic device for performing a logic function: A device for performing a “logic function” consisting of a magnetic structure including at least a first magnetoresistive stack including a first ferromagnetic layer and a second ferromagnetic layer separated by a non-ferromagnetic interlayer and at least one first line of current situated in the vicinity of the first magnetoresistive... Agent: Centre National De La Recherche Scienifique

20110115523 - Storage elements for a configurable ic and method and apparatus for accessing data stored in the storage elements: Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the... Agent:

20110115524 - Logic cell having reduced spurious toggling: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in... Agent: Ati Technologies Ulc

20110109344 - Semiconductor devices having on-die termination structures for reducing current consumption and termination methods performed in the semiconductor devices: Example embodiments disclose a semiconductor device having an on-die termination (ODT) structure that reduces current consumption, and a termination method performed in the semiconductor device. The semiconductor device includes a calibration circuit for generating calibration codes in response to a reference voltage and a voltage of a calibration terminal connected... Agent: Samsung Electronics Co., Ltd.

20110109345 - Logic circuit: A logic circuit includes two two-terminal switching devices and receives first and second pulses as inputs. Each of the two devices has two different stable resistivity values for each applied voltage that is greater than a first threshold voltage (Vth1) and is smaller than a second threshold voltage (Vth2) that... Agent: Fuji Electric Holdings Co., Ltd.

20110102013 - Parallel scan distributors and collectors and process of testing integrated circuits: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan... Agent: Texas Instruments Incorporated

20110102015 - Electronic circuit device: In the electronic circuit device with stacked plural components of the same function, this invention enables to select an arbitrary component among plural components by a control element, without setting pre-determined identification information in each component. By installing a sequential logic circuit in each component, and changing a state of... Agent: Keio University

20110102014 - Three dimensional integrated circuits: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit... Agent:

20110102016 - Four-terminal reconfigurable devices: Reconfigurable devices and methods for the fabrication thereof are provided. In one aspect, a reconfigurable device is provided. The reconfigurable device comprises a substrate; a first dielectric layer on the substrate; a conductive layer recessed into at least a portion of a side of the first dielectric layer opposite the... Agent: International Business Machines Corporation

20110102017 - Configurable time borrowing flip-flops: Configurable time-borrowing flip-flops are provided for circuits such as programmable logic devices. The flip-flops may be based on a configurable delay circuit and two latches or may be based on a configurable pulse generation circuit and a single latch. In designs based on two latches, a first and a second... Agent:

20110102018 - Logic circuit and semiconductor device: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock... Agent: Semiconductor Energy Laboratory Co., Ltd.

20110102019 - Semiconductor device formed on a soi substrate: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a... Agent: Renesas Electronics Corporation