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Electronic digital logic circuitry November recently filed with US Patent Office 11/10

20100295574 - Runtime loading of configuration data in a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While... Agent: Adeli & Tollen, LLP

20100295576 - Circuit arrangement and method for shifting a voltage level: A circuit arrangement for shifting a voltage level comprises a data-current converter (2) that is connected to a first connection (K1) and that has an input for feeding a digital input data signal (DIN), a first output for providing a current (I), and also a second output for providing a... Agent: Cohen, Pontani, Lieberman & Pavane LLP

20100295575 - Digital level shifter and methods thereof: A digital level shifter is disclosed that receives an input voltage from a first voltage domain, and provides an output voltage to a second voltage domain. The level shifter includes transistors configured in parallel with input transistors of the level shifter in order to place the output of the level... Agent: Larson Newman & Abel, LLP

20100295577 - Advanced repeater with duty cycle adjustment: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal.... Agent: Iv (transmeta) C/o Murabito, Hao & Barnes LLP

20100295578 - Clock tree distributing method: A clock tree distribution method is provided. The method, applied to an I/O interface of an integrated circuit, is for generating a clock tree utilized in the I/O interface. The clock tree distribution method includes determining a conversion rate, converting a two-dimensional interface arrangement to a one-dimensional interface arrangement according... Agent: Wpat, PC Intellectual Property Attorneys

20100295579 - Inverter and logic device comprising the same: The inverter includes a driving transistor and a loading transistor having channel regions with different thicknesses. The channel region of the driving transistor may be thinner than the channel region of the load transistor. A channel layer of the driving transistor may have a recessed region between a source and... Agent: Harness, Dickey & Pierce, P.L.C

20100289520 - Debug network for a configurable ic: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments,... Agent: Adeli & Tollen, LLP

20100289523 - Echo canceling arrangement: In a line driver/receiver circuit where the line driver is connected with its output terminals to a load for supplying a transmit signal thereto and where the receiver is connected with its input terminals to the load for simultaneously receiving a receive signal therefrom, the transmit signal on the input... Agent: Spryip, LLC Lan

20100289522 - Signal transmitting device suited to fast signal transmission: A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission... Agent: Antonelli, Terry, Stout & Kraus, LLP

20100289521 - Termination resistance adjusting circuit: A termination resistance adjusting circuit includes a first termination resistor circuit, a second termination resistor circuit connected in parallel with the first termination resistor circuit, a resistor circuit for adjustment that adjusts resistances of the first and second termination resistor circuits, a first amplifier circuit that receives a first voltage... Agent: Young & Thompson

20100289524 - Method for fabrication of a semiconductor element and structure thereof: Re-programmable antifuses and structures utilizing re-programmable antifuses are presented herein. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed... Agent: Winstead PC

20100289525 - Logic circuit: A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element (1) having characteristics which maintain states, a first switching element (25) one end of which is connected to one terminal of the two-terminal bistable switching element (1), a... Agent: Rossi, Kimms & Mcdowell LLP.

20100289526 - Level shifter: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of... Agent: Mcginn Intellectual Property Law Group, PLLC

20100289527 - Semiconductor device: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching... Agent: Mcdermott Will & Emery LLP

20100289528 - Power reducing logic and non-destructive latch circuits and applications: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to... Agent: Intel Corporation C/o Cpa Global

20100283502 - Asynchronous nano-electronics: Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising... Agent: Milstein Zhang & Wu LLC

20100283503 - Reference voltage circuits and on-die termination circuits, methods for updating the same, and methods for tracking supply, temperature, and/or process variation: Devices and methods for operating devices are provided, such as those that include a memory device having a reference voltage (Vref) circuit that has substantially similar paths and impedances as an on-die termination (ODT) circuit. One such Vref circuit tracks supply variations and temperature changes in a manner substantially similar... Agent: Fletcher Yoder (micron Technology, Inc.)

20100283505 - Logic chip, logic system and method for designing a logic chip: A logic chip has a plurality of individually addressable resource blocks each of the resource blocks having logic circuitry, and a communication bar extending across a plurality of the individually addressable resource blocks. The communication bar has a plurality of communication bar segments associated with the resource slots. The communication... Agent: Glenn Patent Group

20100283504 - Method for fabrication of a semiconductor element and structure thereof: Re-programmable antifuses and structures utilizing re-programmable antifuses are presented. Such structures include a configurable interconnect circuit having at least one re-programmable antifuse, wherein the at least one re-programmable antifuse is configured to be programmed to conduct by applying a first voltage across it and is configured to be re-programmed not... Agent: Winstead PC

20100283506 - Configurable input port of an electronic computer of a motor vehicle: ii) a plurality of pull-down loads (230b), each pull-down load being coupled to a ground line (22) and to the input line (20) and including at least one transistor (231b) forming a current mirror with a second current reference module (232b). Each pull-up load and each pull-down load includes a... Agent: Young & Thompson

20100283507 - Current source applicable to a controllable delay line and design method thereof: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.... Agent: J C Patents

20100283508 - Semiconductor chip and semiconductor device including the same: A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units... Agent: Sughrue Mion, PLLC

20100283509 - Inverter, logic circuit including an inverter and methods of fabricating the same: An inverter, a logic circuit including the inverter and method of fabricating the same are provided. The inverter includes a load transistor of a depletion mode, and a driving transistor of an enhancement mode, which is connected to the load transistor. The load transistor may have a first oxide layer... Agent: Harness, Dickey & Pierce, P.L.C

20100277200 - Self-calibrating writer: In accordance with the invention, a method, system and apparatus are presented that matches the output impedance of a driver to the impedance of a transmission line. A method for matching the impedance between a driver and a transmission line, wherein the transmission line is between the driver and a... Agent: Marvell/finnegan Henderson LLP C/o Finnegan, Henderson, Farabow, Garnett Et. Al.

20100277201 - Embedded digital ip strip chip: An integrated circuit (IC) is provided. The IC includes a first region having an array of programmable logic cells. The IC also includes a second region incorporated into the IC and in communication with the first region. The second region includes standard logic cells and base cells. In one embodiment,... Agent: Martine Penilla & Gencarella, LLP

20100277202 - Circuitry and layouts for xor and xnor logic: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node.... Agent: Martine Penilla & Gencarella, LLP