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Electronic digital logic circuitry March listing by industry category 03/10

20100073023 - Signal lines with internal and external termination: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an... Agent: Pvf -- Rambus, Inc. C/o Park, Vaughan & Fleming, LLP

20100073024 - Architecture and interconnect scheme for programmable logic circuits: An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer... Agent: Daniel E. Ovanezian Blakely, Sokoloff, Taylor & Zafman LLP

20100073026 - Die apparatus having configurable input/output and control method thereof: A metal configurable I/O structure for an integrated circuit is disclosed. The metal configurable I/O structure may be configured for one of any of a plurality of I/O specifications. Preferably a common voltage reference and a common current reference is generated for provision to a plurality of I/O structures.... Agent: Christie, Parker & Hale, LLP

20100073025 - Programmable logic circuit: A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.

20100073027 - Latch structure, frequency divider, and methods for operating same: A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic... Agent: Qualcomm Incorporated

20100073028 - Level-converting flip-flop and pulse generator for clustered voltage scaling: Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high... Agent: Harness, Dickey & Pierce, P.L.C

20100073030 - Adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique: The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at given noise robustness with less overhead in area, power and delay, said adaptive keeper comprising, keeper PMOS transistor (M1), wherein the drain of... Agent: Lathrop & Gage LLP

20100073029 - Complementary energy path adiabatic logic: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors,... Agent: Kamrath & Associates P.A.

20100073031 - Nanotube-based switching elements with multiple controls and logic circuits having said elements: Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and... Agent: Wilmerhale/boston

20100066405 - Line driver with tuned on-chip termination: A line driver includes current sources and resistors that form a bridge circuit in which a bridge resistor is connected between an internal node and ground, and a series resistor connected between the internal node and the driver's output node. The internal node is connected to receive a unit current... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way

20100066404 - Reduced power differential type termination circuit: A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and... Agent: Tracy Parris

20100066406 - Semiconductor device: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first... Agent: Mcginn Intellectual Property Law Group, PLLC

20100066408 - Configuration data feeding device: A configuration data feeding device for feeding configuration data to a plurality of FPGAs includes a memory for storing configuration data that are fed to the plurality of FPGAs, a plurality of interface units for outputting the configuration data read out from the memory, according to their specific configuration layouts,... Agent: Katten Muchin Rosenman LLP

20100066407 - Operational time extension: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at... Agent: Adeli & Tollen, LLP

20100066409 - Bidirectional signal separation module for a bus converter: A bidirectional signal separation module includes a comparator having a first input node communicatively coupled to a bidirectional single-ended bus, a second input node communicatively coupled to a first voltage source, and an output node communicatively coupled to a unidirectional data transmission node; and a resistive network having a first... Agent: Hewlett-packard Company Intellectual Property Administration

20100066410 - Low-loss impedance-matched source-follower for repeating or switching signals on a high speed link: Switching and repeating applications using an impedance matched source follower improve performance of high speed links such as PCI Express, HDMI, DisplayPort and DVI by reducing attenuation and other degradation of high speed signals, including those with transmit pre-emphasis, by avoiding impedance discontinuities over process, voltage and temperature variations and... Agent: Tracy Parris

20100066411 - Logic circuit using metal-insulator transition (mit) device: Provided is a logic circuit comprising a metal-insulator transition (MIT) device, including: an MIT device unit including an MIT thin film, an electrode thin film contacting the MIT thin film, and at least one MIT device undergoing a discontinuous MIT at a transition voltage VT; a power source unit including... Agent: Rabin & Berdo, PC

20100060309 - Multi-row block supporting row level redundancy in a pld: In a Programmable Logic Device (PLD), a multi-row block that has internal logic connections between rows has redundant internal connections between rows to replace the internal logic connections when a fault occurs. The redundant internal logic connections extend through a row, linking the row above a defective row with a... Agent: Weaver Austin Villeneuve & Sampson LLP - Altera Attn: Altera

20100060310 - Systems and methods utilizing redundancy in semiconductor chip interconnects: An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect.... Agent: Qualcomm Incorporated

20100060311 - Circuits and methods for testing fpga routing switches: An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one... Agent: Lewis And Roca LLP

20100060313 - Semiconductor integrated circuit device and test terminal arrangement method: A semiconductor integrated circuit device includes a column of first logic circuit cells arranged along a first side of a chip and a column of second logic circuit cells arranged along a second side orthogonal to the first side. At a corner part where the first side crosses the second... Agent: Mcginn Intellectual Property Law Group, PLLC

20100060312 - Testing circuit split between tiers of through silicon stacking chips: A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create... Agent: Qualcomm Incorporated

20100060316 - Calibration circuit, on die termination device and semiconductor memory device using the same: A calibration circuit includes a gain control device configured to adjust a reference voltage to a predetermined level according to a variable gain; and a calibration device configured to update a calibration code by comparing a voltage generated by resistors and the reference voltage adjusted to the predetermined level by... Agent: Ip & T Law Firm PLC

20100060317 - Data output device and semiconductor memory apparatus including the same: A data output device includes a pre-driver unit configured to control a driving force according to an impedance control signal and to drive output data using the driving force. The data output device includes a main-driver unit configured to control an impedance according to pull-up and pull-down resistance control codes... Agent: Ladas & Parry LLP

20100060315 - High capacitive load and noise tolerant system and method for controlling the drive strength of output drivers in integrated circuit devices: An output driver calibration circuit includes a programmable drive strength output pullup driver including a strongest transistor and a number of other transistors, a programmable drive strength output pulldown driver including a strongest transistor and a number of other transistors, and a calibration circuit for generating a number of control... Agent: Hogan & Hartson LLP

20100060318 - Printed circuit board having a termination of a t-shaped signal line: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.... Agent: O''shea Getz P.C.

20100060314 - Termination resistor scheme: An example embodiment of the present invention relates to a method and corresponding apparatus that terminates circuit connectivity in a bus by determining location of an instrument on the bus, and based on coupling a terminating resistance to the instrument. The example embodiment may couple a terminating resistance with the... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20100060319 - Low leakage and data retention circuitry: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20100060320 - Signal driver circuit having an adjustable output voltage: Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a signal driver configured to generate an output signal at an output node in response to an input signal and a transistor coupled to the signal driver that is... Agent: Dorsey & Whitney LLP Intellectual Property Department

20100060321 - Clock control of state storage circuitry: State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 12 is controlled by a first clock signal nclk and a second clock signal bclk.... Agent: Nixon & Vanderhye P.C.

20100060322 - Adiabatic cmos design: An integrated circuit comprising a plurality of CMOS modules (10) connected in series with each other, each module (10) being connected between first and second reference lines (Vdd, Vss). A first transistor (54) is provided between at least one of the modules (10) and the first reference line (Vdd) and... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20100052728 - Load sense and active noise reduction for i/o circuit: An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device... Agent: Dergosits & Noah LLP Attn: Michael J. Pollock

20100052729 - Digital data inversion flag generator circuit: An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained in a data word to be transmitted from the memory cells is greater than a threshold number. The... Agent: Dicke, Billig & Czaja