|Electronic digital logic circuitry patents - Monitor Patents|
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Electronic digital logic circuitry February patent applications/inventions, industry category 02/10Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 02/25/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100045336 - Method and device for programmable power supply with configurable restrictions: The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device.... Agent: Slater & Matsil LLP
20100045337 - Methods, apparatuses, and products for a secure circuit: e
20100045339 - wireline transmission circuit: A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received... Agent: Xin Wen
20100045340 - Control circuit for controlling on-die termination impedance: The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either... Agent: Ladas & Parry LLP
20100045341 - Method and apparatus for high resolution zq calibration: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device.... Agent: Jones Day
20100045338 - Semiconductor device and data processing system including the same: There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets... Agent: Mcginn Intellectual Property Law Group, PLLC
20100045342 - Level translator circuit: A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.... Agent: Seed Intellectual Property Law Group PLLC
20100045343 - Current limited voltage supply: A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor... Agent: Bever Hoffman & Harms, LLP 901 Campisi Way
20100045344 - Dual rail domino circuit, domino circuit, and logic circuit: In a dual rail domino circuit 3 using a combination of a domino circuit 1 for outputting positive logic and a domino circuit 2 for outputting negative logic, an AND 4 and a NAND 5 as members for simultaneously fixing an output of the domino circuit 1 and an output... Agent: Mr. Jackson Chen02/18/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100039135 - Semiconductor integrated circuit: Semiconductor integrated circuit has a control circuit. The control circuit causes the clock signal generating circuit to control the first clock signal and the second clock signal to make a logic of data held by the first data holding terminal and a logic of data held by the second data... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, L.L.P.
20100039137 - Download sequencing techniques for circuit configuration data: Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different... Agent: Townsend And Townsend And Crew, LLP
20100039136 - Gate level reconfigurable magnetic logic: A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation... Agent: Qualcomm Incorporated
20100039138 - Nonvolatile nanotube programmable logic devices and a nonvolatile nanotube field programmable gate array using same: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.... Agent: Wilmerhale/boston
20100039139 - Reconfigurable sequencer structure: A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory... Agent: Kenyon & Kenyon LLP
20100039140 - Buffer circuit of semiconductor memory apparatus: A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the... Agent: Venable LLP02/11/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100033206 - Method and apparatus for ballistic single flux quantum logic: In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates... Agent: Snell & Wilmer L.L.P. (grumman)
20100033207 - Fault tolerant integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC
20100033208 - Shift register units, display panels utilizing the same, and methods for improving current leakage thereof: A shift register comprising at least one shift register unit. The shift register unit comprises an input unit, at least one first TFT, and at least one second TFT. The input unit receives an input signal from the input terminal and outputs a switching control signal in accordance with a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP
20100033209 - Method and device for generating pseudo-random binary data: A device for generating k-bit parallel pseudo-random data includes “n” registers, from the first through the n-th registers (“n” is an integer not less than 3), and “k” exclusive-OR gates, from the first through the k-th exclusive-OR gates (“k” is an integer not less than 2). An output of the... Agent: Katten Muchin Rosenman LLP
20100033210 - Data output circuit: A data output circuit includes a plurality of drivers configured to drive data output terminals to a logic level corresponding to levels of input data in response to driving control signals, and a control section configured to activate and output driving control signals that supplied to a first group of... Agent: Baker & Mckenzie LLP Patent Department
20100033211 - Link transmitter with reduced power consumption: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.... Agent: Intel Corporation C/o Cpa Global
20100033212 - Multiplexing using product-of-sums and sum-of-products: A method for and the results of implementing a tree of multiplexing are disclosed. At each level of the tree, a sum-of-products or a product-of-sums representation is chosen to maximize inter-level optimizations.... Agent: Eric Mahurin
20100033213 - Field effect transistor and electric circuit: The invention relates to a field effect transistor comprising at least one source electrode layer and at least one drain electrode layer arranged in the same plane, a semiconductor layer, an insulator layer and a gate electrode layer, wherein the gate electrode layer, as seen perpendicular to the plane of... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein02/04/2010 > patent applications in patent subcategories. patent applications/inventions, industry category
20100026336 - False connection for defeating microchip exploitation: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection... Agent: Ibm-rochester C/o Toler Law Group
20100026337 - Interdependent microchip functionality for defeating exploitation attempts: An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon... Agent: Ibm-rochester C/o Toler Law Group
20100026338 - Fault triggerred automatic redundancy scrubber: A redundancy scrubber. The novel scrubber includes fault detection logic for detecting if a circuit has been upset and a mechanism for automatically rewriting data to the circuit when an upset is detected. In an illustrative embodiment, the scrubber corrects for upsets in a circuit comprised of a plurality of... Agent: Pillsbury Winthrop Shaw Pittman LLP (raytheon Sas)
20100026339 - Asics having more features than generally usable at one time and methods of use: More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development probabilities in a host of different... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
20100026340 - User-accessible freeze-logic for dynamic power reduction and associated methods: A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode... Agent: Law Offices Of Maximilian R. Peterson
20100026341 - Macrocell and method for adding: A macrocell including an adder block with a plurality of bit-slice adders, a bypass path and a control unit adapted to receive a carry of a first neighboring macrocell, and to output a carry by generation within the adder block or by passage of the carry of the first neighboring... Agent: Dickstein Shapiro LLP
20100026342 - High voltage input receiver using low voltage transistors: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a... Agent: Christopher P Maiorana, PC Lsi Corporation
20100026343 - Clocked single power supply level shifter: First circuitry is powered by a first power supply domain and provides a data signal referenced to the first power supply domain. Second circuitry is powered by a second power supply domain that differs from the first power supply domain. The data signal becomes referenced to the second power supply... Agent: Freescale Semiconductor, Inc. Law Department
20100026344 - Methods, devices, and systems for a high voltage tolerant buffer: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors.... Agent: Trask Britt, P.C./ Micron Technology
20100026345 - Circuit, system, and method for multiplexing signals with reduced jitter: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal... Agent: Cypress Semiconductor Corporation
20100026346 - High-density logic techniques with reduced-stack multi-gate field effect transistors: Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or “stacked” portions of logic gates. Circuit area can... Agent: Ryan, Mason & Lewis, LLPPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
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