Electronic digital logic circuitry inventions 09/09

20090237106 - Digital programmable phase generator: A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective... Agent: Milde & Hoffberg, LLP

20090237107 - Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a... Agent: Mills & Onello LLP

20090237108 - Semiconductor integrated circuit: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output... Agent: Mcginn Intellectual Property Law Group, PLLC

20090237109 - Efficient method for implementing programmable impedance output drivers and programmable input on die termination on a bi-directional data bus: A combined input and termination circuit comprises a fixed portion of impedance and a programmable portion of impedance. The fixed portion is able to be fixed in a driver mode and a termination mode. The programmable portion is able to be configured to have a desired impedance in a driver... Agent: Haverstock & Owens LLP

20090237112 - Data transfer cable for programmable logic devices: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of... Agent: PCe Industry, Inc. Att. Steven Reiss

20090237111 - Integrated circuits with hybrid planer hierarchical architecture and methods for interconnecting their resources: The present invention relates to methods for interconnecting base, switching and interconnect resources for configurable integrated circuits that include the following steps: interconnecting base and switching resources with interconnect resources to form a hierarchical interconnect structure; physically placing the hierarchical interconnect structure in a two dimensional format; and directly interconnecting... Agent: Venture Pacific Law, PC

20090237110 - Programmable on-chip logic analyzer apparatus, systems, and methods: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset... Agent: Schwegman, Lundberg & Woessner/micron

20090237113 - Semiconductor integrated circuit, program transformation apparatus, and mapping apparatus: A semiconductor integrated circuit (100) according to the present invention includes a plurality of reconfigurable cores (101) arranged separately from each other in a matrix, and a first group of register circuits (102) formed between a first and second reconfigurable cores included in the reconfigurable cores (101). Each of the... Agent: Greenblum & Bernstein, P.L.C

20090237114 - Decoder circuit: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input... Agent: Mcdermott Will & Emery LLP

20090230988 - Electronic device having logic circuitry and method for designing logic circuitry: An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (EC1) for performing logic operations; and at least one second electronic component (EC2) for improving the soft-error sensitivity of the... Agent: Philips Intellectual Property & Standards

20090230989 - Memory control circuit, memory control method, and integrated circuit: Each of a plurality of memories includes a terminating resistor for preventing signal reflection, and a memory control circuit includes an ODT control circuit for driving the terminating resistor of each memory, and a selector for selecting, from memories except for a memory to be accessed, at least one memory... Agent: Fitzpatrick Cella Harper & Scinto

20090230990 - Hardware and software programmable fuses for memory repair: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is... Agent: Mcandrews Held & Malloy, Ltd

20090230992 - Data transmission circuit capable of reducing current consumption: A data transmission circuit includes a first signal transmission unit and a second signal transmission unit. The first signal transmission unit includes a driving unit having a plurality of driving devices used for driving and outputting an output signal at different logic levels according to driving signals. A driving signal... Agent: Ladas & Parry LLP

20090230991 - Level shifter circuit: A level shifter circuit includes a level shifter, an inverter, a first switch circuit and a second switch circuit. The level shifter includes a first transistor, a second transistor, a third transistor and a fourth transistor. The inverter receives an input signal and thus generates an inversion input signal. The... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090230993 - Low power high-speed output driver: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the... Agent: Garlick Harrison & Markison

20090230994 - Domino logic circuit and pipelined domino logic circuit: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase... Agent: Mills & Onello LLP

20090230995 - Semiconductor device: A semiconductor device includes multiple functional blocks, each having a predetermined function, and wiring regions on a substrate where a signal line is provided. The semiconductor device also includes multiple standard cells disposed in the wiring regions along the signal line, each of which operates with a substrate bias potential,... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224797 - Electronic device: An electronic device having a circuit configuration in which a terminating resistor is connected to a data signal line is disclosed, including: a data processing part; one or more data storing parts being main storage units of the data processing part; a termination voltage generating part to apply a termination... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20090224798 - Printed circuit board and differential signaling structure: Provided is a system adopting a differential signaling system including a low frequency signaling line arranged to be adjacent to a pair of differential signaling lines in parallel to each other, for transmitting a signal having a frequency which is smaller than a frequency of a signal to be transmitted... Agent: Fitzpatrick Cella Harper & Scinto

20090224796 - Termination switching based on data rate: Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termination control logic may determine whether the clock frequency is... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Qimonda

20090224799 - Logical circuit device, logical operation varying method, and logical operation system: A logical circuit device comprises a plurality of logical blocks including reconfigurable logical configurations and a network including reconfigurable connections among the plurality of logical blocks, wherein at least one of the plurality of logical blocks comprises a basic logical operation element. The basic logical operation element receives a first... Agent: Fujitsu Patent Center C/o Cpa Global

20090224800 - Pld architecture for flexible placement of ip function blocks: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining... Agent: Ropes & Gray LLP

20090224801 - Pattern matching apparatus: A pattern matching apparatus for matching input data to a reference data string, wherein: it is implemented in electronic hardware and can be implemented using commercially available FPGAs using all digital processing; it is capable of very fast correlation; input data is received by a 1:N demultiplexer which reduces the... Agent: Oliff & Berridge, PLC

20090224802 - Devices and methods for driving a signal off an integrated circuit: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output... Agent: Jennifer M. Lane, Esq. Dorsey & Whitney LLP

20090224803 - Cmos back-gated keeper technique: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when... Agent: Scully, Scott, Murphy & Presser, P.C.

20090219051 - Hybrid nanotube/cmos dynamically reconfigurable architecture and an integrated design optimization method and system therefor: A hybrid nanotube, high-performance, dynamically reconfigurable architecture, NATURE, is provided, and a design optimization flow method and system, NanoMap. A run-time reconfigurable architecture is provided by associating a non-volatile universal memory to each logic element to enable cycle-by-cycle reconfiguration and logic folding, while remaining CMOS compatible. Through logic folding, significant... Agent: Dann, Dorfman, Herrell & Skillman

20090219052 - Transmitter swing control circuit and method: Disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.... Agent: Intel Corporation C/o Cpa Global

20090219053 - Power efficient multiplexer: A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20090219054 - Current mode logic digital circuits: A digital circuit comprises: a first arm including a first metal oxide semiconductor field effect transistor (M3) configured to act as a load device; a second arm including a second metal oxide semiconductor field effect transistor (M4) configured to act as a load device; and a switch (M1, M2) for... Agent: Patterson & Sheridan L.L.P. Nj Office