Electronic digital logic circuitry inventions 08/09

20090212814 - Deliberate destruction of integrated circuits: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated... Agent: Snell & Wilmer L.l.p. (main)

20090212813 - Electronic device board level security: A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier... Agent: Brake Hughes Bellermann LLP C/o Cpa Global

20090212815 - Triple latch flip flop system and method: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node.... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20090212816 - Impedance adjustment circuit: Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment... Agent: Mcginn Intellectual Property Law Group, Pllc

20090212817 - Configuration information writing apparatus, configuration information writing method and computer program product: A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extracting unit that acquires plural pieces of configuration information and extracts differences between each of the... Agent: Foley And Lardner LLP Suite 500

20090212818 - Integrated circuit design method for improved testability: An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro... Agent: Mcginn Intellectual Property Law Group, Pllc

20090212819 - Method and system for changing circuits in an integrated circuit: A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090212820 - Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument: A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals... Agent: Oliff & Berridge, Plc

20090212821 - Bulk input current switch logic circuit: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed bit a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal... Agent: Jianq Chyun Intellectual Property Office

20090212822 - Bulk input current switch logic circuit: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal... Agent: Jianq Chyun Intellectual Property Office

20090212823 - Low jitter cmos to cml converter: The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input terminal, an output terminal and a connection terminal. With the current compensation... Agent: Squire, Sanders & Dempsey L.l.p.

20090206871 - Arbitrary quantum operations with a common coupled resonator: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of... Agent: Snell & Wilmer L.L.P. (grumman)

20090206872 - System, method and apparatus for enhancing reliability on scan-initialized latches affecting functionality: A system, method, and apparatus for enhancing reliability on scan-initialized latches that affect functionality in a digital design are provided. The system includes a group of latches that affect functionality in the digital design based on state values of the latches, where the latches are scan initialized. The system also... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20090206873 - Data output driver: A data output driver device includes a noise detecting unit configured to output a noise detection signal to detect variations of power supply voltage due to noise, and a driver circuit unit configured to drive and output data with the variable driving capability in response to the noise detection signal.... Agent: Baker & Mckenzie LLP Patent Department

20090206875 - Programmable io architecture: A buffer device coupled to at least one input/output port of an integrated circuit has a plurality of control inputs configured to receive configuration programming information. The at least one input/output circuit is capable of: (a) being configured in a directional sense of communication by the configuration programming information, (b)... Agent: Townsend And Townsend And Crew, LLP

20090206874 - Semiconductor device: A first operation unit stores first code information having a bit length shorter than a first set bit, receives dictionary information expressing each set bit corresponding to each code information, reads the set bit corresponding to the first code information from the dictionary information to obtain the first set bit,... Agent: Charles N.j. Ruggiero, Esq. Ohlandt, Greeley, Ruggiero & Perle, L.L.P.

20090206876 - Programmable core for implementing logic change: An apparatus comprising a plurality of fixed logic circuits, wherein each of the fixed logic circuits is configured to receive a plurality of input signals, perform combinational logic operations using the input signals, and produce at least one output signal, and wherein the combinational logic operations are substantially fixed; and... Agent: Brake Hughes Bellermann LLP C/o Cpa Global

20090206877 - Quad state logic design methods, circuits and systems: Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs.... Agent: Texas Instruments Incorporated

20090206878 - Level shift circuit for a driving circuit: Provided is a level shift circuit for a driving circuit. The level shift circuit includes: a cross-coupled transistor pair, for receiving a first input signal and a second input signal and for providing a first output signal and a second output signal; a first transistor, coupled to a first power... Agent: J C Patents, Inc.

20090206879 - Signal transmission circuit and signal transmission system using the same: A signal transmission circuit includes first and second power source wirings, and a plurality of differential circuits connected in series between the first and second power source wirings. A signal transmission system includes a plurality of pairs of signal wirings, an output circuit supplying a differential signal to each of... Agent: Mcginn Intellectual Property Law Group, PLLC

20090206880 - Semiconductor integrated circuit: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal... Agent: Mcdermott Will & Emery LLP

20090206881 - Semiconductor integrated circuit: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different... Agent: Mcdermott Will & Emery LLP

20090206883 - Thermal electric nand gate: A thermal electric (TE) binary NAND gate logic circuit is provided with a method for NAND logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage... Agent: Law Office Of Gerald Maliszewski

20090206882 - Thermal electric nor gate: A thermal electric (TE) binary NOR gate logic circuit is provided with a method for NOR logic gating. The method accepts a first input voltage representing an input binary logic state and generates a first thermal electric (TE) temperature in response to the first input voltage. A second input voltage... Agent: Gerald W. Maliszewski

20090201044 - logic performance in cyclic structures: Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements... Agent: Schwegman, Lundberg & Woessner, P.A.

20090201045 - Input circuit and semiconductor integrated circuit comprising the input circuit: A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously... Agent: Sughrue Mion, PLLC

20090201046 - Output buffer and method having a supply voltage insensitive slew rate: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090201047 - Output impedance calibration circuit with multiple output driver models: A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20090201048 - Reducing errors in data by dynamically calibrating trigger point thresholds: Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts... Agent: Ropes & Gray LLP

20090201049 - Integrated circuit with input and/or output bolton pads with integrated logic: An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB1, IB2) and/or an output buffer (OB) and arranged to be connected... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090201044 - logic performance in cyclic structures: Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements... Agent: Schwegman, Lundberg & Woessner, P.A.

20090201045 - Input circuit and semiconductor integrated circuit comprising the input circuit: A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously... Agent: Sughrue Mion, PLLC

20090201046 - Output buffer and method having a supply voltage insensitive slew rate: An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090201047 - Output impedance calibration circuit with multiple output driver models: A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20090201048 - Reducing errors in data by dynamically calibrating trigger point thresholds: Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts... Agent: Ropes & Gray LLP

20090201049 - Integrated circuit with input and/or output bolton pads with integrated logic: An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB1, IB2) and/or an output buffer (OB) and arranged to be connected... Agent: Nxp, B.v. Nxp Intellectual Property & Licensing

20090195266 - High voltage stress test circuit: A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data... Agent: Cantor Colburn, LLP

20090195267 - High-voltage tolerant output driver: A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output driver is fabricated. Unregulated supply voltages can vary over a wide... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20090195268 - Level shifting circuit and method: In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level... Agent: Qualcomm Incorporated

20090195269 - Input stage for mixed-voltage-tolerant buffer with reduced leakage: A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20090195270 - Output buffer device: A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor... Agent: Volpe And Koenig, P.C.