|Electronic digital logic circuitry patents - Monitor Patents|
USPTO Class 326 | Browse by Industry: Previous - Next | All
06/2009 | Recent | 13: May | Apr | Mar | Feb | Jan | 12: Dec | Nov | Oct | Sep | Aug | July | June | May | April | Mar | Feb | Jan | 11: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | 10: Dec | Nov | Oct | Sep | Aug | Jul | Jun | May | Apr | Mar | Feb | Jan | | 09: Dec | Nov | Oct | Sep | Aug | Jl | Jn | May | Apr | Mar | Fb | Jn | | 2008 | 2007 |
Electronic digital logic circuitry June invention type 06/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 06/25/2009 > patent applications in patent subcategories. invention type
20090160480 - Termination circuit: In order to prevent malfunction due to fluctuations in signal level, a terminating resistor circuit includes terminating resistors the connections whereof to an input/output terminal are capable of being turned on and off, whereby a Thevenin termination is formed. A control circuit exercises control so as to temporally stagger on/off... Agent: Mcginn Intellectual Property Law Group, PLLC
20090160479 - Transceiver having an adjustable terminating network for a control device: In a transceiver for a control unit having a transceiver core for adapting the level of messages received or to be sent, an adjustable terminating network is situated in the transceiver that makes it possible to adjust at least two connection resistance values, the terminating network and the transceiver core... Agent: Kenyon & Kenyon LLP
20090160483 - Field programmable application specific integrated circuit with programmable logic array and method of designing and programming the programmable logic array: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
20090160482 - Formation of a hybrid integrated circuit device: Formation of a hybrid integrated circuit device (400) is described. A design for the integrated circuit (100) is obtained and separated into at least two portions responsive to component sizes. A first die (200) is formed for a first portion of the hybrid integrated circuit device (400) using at least... Agent: Xilinx, Inc Attn: Legal Department
20090160484 - Input buffer: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained... Agent: Law Office Of Charles W. Bethards, LLP
20090160485 - Providing higher-swing output signals when components of an integrated circuit are fabricated using a lower-voltage process: An output block fabricated using a lower-voltage process provides output signals with a higher voltage swing. The output block contains a differential amplifier portion and a hold circuit portion. The differential amplifier portion is activated only when the logic level of an output signal needs to be switched. Once the... Agent: Texas Instruments Incorporated
20090160486 - High speed electronic data transmission system: A high-speed electrical data transmission system (10) includes a signal mixer (13) for receiving high-speed data from external network transceiver (12). The signal mixer (13) converts the data into an electrical current-fluctuating data signal. A signal processor (17) is located remotely of the signal mixer (13) and is connected electrically... Agent: Jackson Walker, L.L.P.
20090160481 - Configurable circuits, ic's and systems: Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection schemes for communicatively coupling the input terminal set to the output terminal... Agent: Adeli & Tollen, LLP06/18/2009 > patent applications in patent subcategories. invention type
20090153180 - Single flux quantum circuits: Superconducting single flux quantum circuits are disclosed herein, each having at least one Josephson junction which will flip when the current through it exceeds a critical current. Bias current for the Josephson junction is provided by a biasing transformer instead of a resistor. The lack of any bias resistors ensures... Agent: Snell & Wilmer L.L.P. (grumman)
20090153181 - Data retention kill function: Various data protection techniques are provided. In one embodiment, a method includes manufacturing a memory component of an electronic system. Manufacturing the memory component may include disposing a memory array on a substrate and coupling a control circuit to the memory array. The control circuit may be configured to selectively... Agent: Fletcher Yoder (micron Technology, Inc.)
20090153182 - Semiconductor device: A speed performance measurement circuit that may perform speed performance measurement is provided between a first logic circuit and a second logic circuit. The speed performance measurement circuit includes a first flip flop that stores first data, a first delay circuit that delays the first data and generates second data,... Agent: Miles & Stockbridge PC
20090153183 - Noise filter circuit, dead time circuit, delay circuit, noise filter method, dead time method, delay method, thermal head driver, and electronic instrument: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a... Agent: Oliff & Berridge, PLC
20090153184 - Output driver circuit with output preset circuit and controlling method thereof having lower power consumption: The configurations of an output preset circuit for an output driver circuit and the controlling methods thereof are provided. The proposed output preset circuit includes a latch generating an latch output signal and a pull-up circuit receiving an preset enable signal and the latch output signal, in which the pull-up... Agent: Volpe And Koenig, P.C.
20090153185 - On-die-termination control circuit and method: On-die-termination control circuit includes a mode detecting unit for detecting a power-down mode and a power-down delay configured to delay an on/off control signal in the power-down mode. On-die-termination control circuit provided a shift register configured to delay an on/off control signal in synchronization with shift clocks in a non-power-down... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090153186 - On-die-termination control circuit and method: On-die-termination control circuit includes a clock generator configured to generate shift clocks in response to an on/off control signal; and a shift register configured to delay the on/off control signal in synchronization with the shift clocks to control on/off timing of an ODT operation.... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090153187 - Monolithically integrated interface circuit: The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises... Agent: O''shea Getz P.C.
20090153188 - Process for automatic dynamic reloading of data flow processors (dfps) and units with two- or three-dimensional programmable cell architectures (fpgas, dpgas and the like): In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements,... Agent: Kenyon & Kenyon LLP
20090153189 - Universal serial bus wakeup circuit: A circuit is attached in parallel to a universal serial bus interface of a data processing system. A capacitor in the circuit is charged by receiving power from a power pin of the universal serial bus interface while the data processing system is not in a reduced power state. A... Agent: Duke W. Yee Yee & Associates, P.C.
20090153190 - Voltage control: A circuit for converting a lower voltage logical signal to a higher voltage. The circuit comprises a current mirror structure having first and second branches, each comprising at least a first transistor of a first kind, an input transistor of a second kind, and a second transistor of the first... Agent: Ryan, Mason & Lewis, LLP
20090153191 - Pre-driver logic: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor... Agent: Leffert Jay & Polglaze, P.A.
20090153192 - Bi-directional buffer for open-drain or open-collector bus: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When... Agent: Fliesler Meyer LLP
20090153193 - Bi-directional buffer with level shifting: A bi-directional buffer is connected between a first node and a second node, wherein the first node is connected by a first pull-up resistor to a first voltage supply rail, and the second node is connected by a second pull-up resistor to a second voltage supply rail. In an embodiment,... Agent: Fliesler Meyer LLP
20090153194 - Clock circuitry: A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative frequency of the first and second clock signals. Synchronisation logic generates pulses which indicate when to transfer data... Agent: Mcdermott Will & Emery LLP06/11/2009 > patent applications in patent subcategories. invention type
20090146681 - Method and apparatus for estimating resistance and capacitance of metal interconnects: Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect... Agent: Qualcomm Incorporated
20090146682 - Data output driving circuit and method for controlling slew rate thereof: A data output driving circuit capable of optimizing a slew rate of data according to the variation of operational conditions and a method for controlling a slew rate thereof includes a slew rate control signal generating unit configured to generate slew rate control signals by using a code signal, and... Agent: Baker & Mckenzie LLP Patent Department
20090146683 - Calibration circuit of on-die termination device: A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node and a reference voltage, to generate calibration codes. The calibration unit also includes a calibration resistor unit having parallel resistors which are turned on/off in response to each... Agent: Mannava & Kang, P.C.
20090146684 - Circuit for controlling driver of semiconductor memory apparatus and method of controlling the same: A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a... Agent: Venable LLP
20090146685 - Calibration circuit of on-die termination device: A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node connected to an external resistor and a reference voltage to generate pull-up calibration codes. The calibration circuit also includes a pull-up calibration resistor unit configured to pull up... Agent: Mannava & Kang, P.C.
20090146686 - Configuration context switcher with a latch: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration... Agent: Adeli & Tollen, LLP
20090146687 - Integrated circuit feature definition using one-time-programmable (otp) memory: In one embodiment, a integrated circuit (IC) configurable to have any one of a plurality of different feature sets, the IC including (a) one or more feature blocks adapted to be independently enabled or disabled, (b) a one-time-programmable (OTP) memory cell for each feature block, the OTP memory cell storing... Agent: Mendelsohn & Associates, P.C.
20090146689 - Configuration context switcher with a clocked storage element: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration... Agent: Adeli & Tollen, LLP
20090146691 - Logic cell array and bus system: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate... Agent: Kenyon & Kenyon LLP
20090146688 - Methods of reducing power in programmable devices using low voltage swing for routing signals: Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.... Agent: Ropes & Gray LLP
20090146690 - Runtime configurable arithmetic and logic cell: A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of configuration data is... Agent: Kenyon & Kenyon LLP
20090146692 - Structure for apparatus for reduced loading of signal transmission elements: A design structure for a signal-handing apparatus or communication apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. A signal-handling... Agent: International Business Machines Corporation Dept. 18g
20090146693 - Semiconductor integrated circuit: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along... Agent: Miles & Stockbridge PC06/04/2009 > patent applications in patent subcategories. invention type
20090140764 - Latch circuit: A latch circuit includes a feedback circuit having inverter circuits and at least two input terminals and an input circuit for inputting input signals or signals having the same phase as the input signals to the input terminals of the feedback circuit in synchronization with a clock signal. In the... Agent: Arent Fox LLP
20090140765 - On-die terminators formed of coarse and fine resistors: An integrated circuit includes a semiconductor substrate; a first node; a second node; and a first plurality of resistors, each in a first plurality of resistor units. Each of the first plurality of resistor units includes a first end connected to the first node, and a second end connected to... Agent: Slater & Matsil, L.L.P.
20090140766 - Signal transmission circuit and characteristic adjustment method thereof, memory module, and manufacturing method of circuit board: A signal transmission circuit comprising: first and second transmission lines connected to each other; a first impedance storage circuit storing an impedance of the first transmission line; and a control circuit that outputs match information between an impedance of the second transmission line and the impedance stored in the first... Agent: Mcginn Intellectual Property Law Group, PLLC
20090140767 - Universal circuit for secure function evaluation: An exemplary method enables implementation of a universal circuit capable of emulating each gate of a circuit designed to calculate a function. A first selection module receives inputs associated with the function. It generates outputs that are an ordered series of the inputs. A universal module receives these outputs and... Agent: Patti , Hewitt & Arezina LLC
20090140768 - Low-noise pecl output driver: An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, the integrated circuit output driver is fabricated in a process having thin-gate MOS transistors and thick-gate MOS transistors and includes a predriver circuit, a level shifter circuit, and a driver circuit. The predriver... Agent: Michael J. Ure
20090140769 - System-in-package: A System-in-Package includes a first chip to be mounted in common for a plurality of product types, a second chip having different specifications for each product type, and a wiring substrate being common to a plurality of product types, on which the first chip and the second chip are to... Agent: Mcginn Intellectual Property Law Group, PLLC
20090140770 - Input/output circuit: An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor;... Agent: Arent Fox LLP
20090140771 - Current-controlled cmos circuits with inductive broadbanding: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional... Agent: Garlick Harrison & Markison
20090140772 - Architecture for vbus pulsing in udsm processes: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might... Agent: Texas Instruments IncorporatedPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
RSS FEED for 20130516:
Integrate FreshPatents.com into your RSS reader/aggregator or website to track weekly updates.
For more info, read this article.
Thank you for viewing Electronic digital logic circuitry patents on the FreshPatents.com website. These are patent applications which have been filed in the United States. There are a variety ways to browse Electronic digital logic circuitry patent applications on our website including browsing by date, agent, inventor, and industry. If you are interested in receiving occasional emails regarding Electronic digital logic circuitry patents we recommend signing up for free keyword monitoring by email.
FreshPatents.com Support - Terms & Conditions
Results in 0.28533 seconds