Electronic digital logic circuitry inventions 05/09

20090134907 - Fault tolerant integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20090134906 - Resilient integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which... Agent: Gamburd Law Group LLC

20090134908 - Multi-functional logic gate device and programmable integrated circuit device using the same: Provided is a logic gate device capable of performing multiple logic operations by using a single logic gate circuit. The multi-functional logic gate device includes a pull-up switching unit having input switches of a first group being respectively connected to multiple input terminals and selection switches of the first group... Agent: Myers Bigel Sibley & Sajovec

20090134909 - Programmable structured arrays: A programmable semiconductor device includes a user programmable switch comprising a configurable element is positioned above a transistor material layer deposited on a substrate layer.... Agent: Raminda U. Madurawe

20090134910 - Reconfigurable logic structures: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements... Agent: Patent Law Professionals

20090134911 - Drive method for driving element having capacity impedance, drive device, and imaging device: Three devices such as electric charge-coupled devices are each included in one of three phase impedance circuits composing a 3-phase LC resonance circuit as a device having a capacitive impedance. A driver circuit applies either of a logic level of 0, a high-impedance level or a logic level of 1... Agent: Robert J. Depke Lewis T. Steadman

20090134912 - Adjustable hold flip flop and method for adjusting hold requirements: A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit... Agent: David Smith Lsi Corporation

20090128185 - On-die termination circuit and driving method thereof: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090128186 - Programmable system on a chip for power-supply voltage and current monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring,... Agent: Lewis And Roca LLP

20090128188 - Pad invariant fpga and asic devices: A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering... Agent: Raminda U. Madurawe

20090128187 - Pre-processing data samples from parallelized data converters: An apparatus for pre-processing data samples from parallelized analog-to-digital converters (ADC). An ADC converts an analog signal into N parallel digital data samples that are output on N ADC links x0 through xN−1. A parallel computation block in communication with the ADC processes the data samples in parallel prior to... Agent: Agilent Technologies Inc.

20090128189 - Three dimensional programmable devices: In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein:... Agent: Raminda U. Madurawe

20090128190 - Implementing logic functions with non-magnitude based physical phenomena: An n-valued switch with n≧2, with an input enabled to receive a signal in one of n states, an output enabled to provide a signal in one of at least 2 states, under control of a control signal having one of at least 2 states is disclosed. Signals are instances... Agent: Diehl Servilla LLC

20090128191 - Ultra-low-power level shifter, voltage transform circuit and rfid tag including the same: A level shifter increase a voltage level of an output signal with relatively lower power consumption by adopting current-starved configuration. The level shifter includes an input unit and a driving unit. The input unit includes a current-starved inverter configured to generate a control signal in response to an input signal... Agent: Sughrue Mion, PLLC

20090121742 - Apparatus and method of calibrating on-die termination for semiconductor integrated circuit: An apparatus for calibrating on-die termination for a semiconductor integrated circuit includes a comparing unit that compares a code conversion voltage, which is obtained by converting an internal code into an analog voltage, with a reference voltage, and outputs a comparison result signal, a code control unit that compares a... Agent: Baker & Mckenzie LLP Patent Department

20090121740 - Audio/video router: Technique for Routing digital audio and digital video signals commences by routing a digital video signal, devoid of embedded digital audio, to at least one output, typically by way of a video cross-point switch. At least one digital audio signal undergoes buffering to obtain a prescribed amount of data prior... Agent: Robert D. Shedd Thomson Licensing LLC

20090121743 - Digital method and device for transmission with reduced crosstalk: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four... Agent: Mcdonnell Boehnen Hulbert & Berghoff LLP

20090121741 - Semiconductor apparatus, on-die termination circuit, and control method of the same: An on-die termination circuit of a semiconductor apparatus can include: a code converting unit configured to change a code value of a termination code in response to a termination control signal; and a plurality of on-die termination blocks configured to commonly receive the termination code, and perform a termination operation.... Agent: Baker & Mckenzie LLP Patent Department

20090121744 - Glitch free 2-way clock switch: The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A... Agent: Texas Instruments Incorporated

20090121745 - Dflop circuit for an externally asynchronous-internally clocked system: A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to... Agent: Baker & Mckenzie LLP Patent Department

20090115447 - Design structure for an integrated circuit having state-saving input-output circuitry and a method of testing such an integrated circuit: A design structure for an integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the... Agent: Downs Rachlin Martin PLLC

20090115450 - Circuit and method for controlling termination impedance: A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a... Agent: Blakely Sokoloff Taylor & Zafman LLP

20090115448 - Design structure for an automatic driver/transmission line/receiver impedance matching circuitry: A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive... Agent: Downs Rachlin Martin PLLC

20090115449 - On die termination device and semiconductor memory device including the same: On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate... Agent: Mannava & Kang, P.C.

20090115451 - Configurable and reusable nand system: A configurable and reusable hardware-software NAND system adaptive to various NAND devices independent of the NAND device manufacturer and NAND device characteristics. A device identification signature is decoded from a NAND device in a NAND system; the device identification signature signal is analyzed to obtain a control phase sequence value... Agent: Evergreen Valley Law Group

20090115453 - Ic output signal path with switch, bus holder, and buffer: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).... Agent: Texas Instruments Incorporated

20090115452 - Logic block control system and logic block control method: The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can... Agent: Wenderoth, Lind & Ponack L.L.P.

20090115454 - Method and system for reducing power consumption with configurable latches and registers: Reducing power consumption in latches and similar electronic devices. In one aspect, an apparatus for configuring power consumption of sequential logic includes a sequential logic device including a first latch, a second latch, and first and second enable inputs. The first enable input enables and disables the first and second... Agent: Ibm Rp-rps Sawyer Law Group LLP

20090115456 - Level shift circuit and method for the same: The present invention discloses a level shift circuit which comprises: a basic level shift circuit for receiving inputs of first high and low operational voltage levels and generating outputs of second low and high operational voltage levels at a first node; and an output circuit for outputting a signal of... Agent: Tung & Associates

20090115455 - Voltage level translation: A virtual zero delay unidirectional high voltage logic to low voltage CMOS logic voltage level translator can be achieved using a capacitive voltage divider coupled with the standard protection diodes commonly incorporated in low side logic (e.g. Xilinx Spartan-3E FPGA's). The complete voltage level translator will work equally well on... Agent: Barnes & Thornburg LLP

20090115457 - Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply... Agent: Advanced Micro Devices, Inc. C/o Vedder Price P.C.

20090115458 - Cmos comparator with hysteresis: A complementary metal oxide semiconductor (CMOS) comparator circuit includes a plurality of p-type metal-oxide-semiconductor (PMOS) transistors receiving an input voltage signal, a plurality of n-type metal-oxide-semiconductor (NMOS) transistors operatively connected to the PMOS transistors and adapted to receive the input voltage signal, and an inverter adapted to invert the input... Agent: Rahman LLC