Electronic digital logic circuitry inventions 04/09

20090108866 - Radiation hardened logic circuits: A radiation hardened inverter includes first and second electrical paths between an input terminal and an output terminal. A first PFET is disposed in the first electrical path, and a bipolar junction transistor (BJT) is disposed in the second electrical path. The first PFET is configured to convert a low... Agent: Ratnerprestia

20090108867 - Method for operating an electronic device with reduced pin capacitance: A method of operating an electronic device having an output driver with on die termination legs ODT, and non-ODT legs, includes the step of selectively tri-stating tuning transistors (ZQ trim devices) in the legs as a function of the operational state of the output driver. The tri-stating step is performed... Agent: Stephen A Gratton The Law Office Of Steve Gratton

20090108869 - Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path: A design structure for a multimode circuit that is configured to operate in one of multiple operating modes is disclosed. In particular, an exemplary multimode circuit may be configured to operating in one of a full-swing mode, a limited-swing mode, a full-swing to limited-swing converter mode, and a limited-swing to... Agent: Downs Rachlin Martin PLLC

20090108868 - Method and circuit for matching semiconductor device behavior: A design structure and method. The design structure comprises a selection circuit comprising a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array.... Agent: Schmeiser, Olsen & Watts

20090108870 - I/o buffer circuit: An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090108871 - Methods, devices, and systems for a high voltage tolerant buffer: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor, a... Agent: Trask Britt, P.C./ Micron Technology

20090108872 - interface circuit that can switch between single-ended transmission and differential transmission: An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a... Agent: Wenderoth, Lind & Ponack L.L.P.

20090108873 - Quantum-dot cellular automata methods and devices: A Quantum-dot Cellular Automata (QCA) device having normal QCA cells laid out in a planar structure such that there are a set of input lines, that may be columns, and a set of orthogonal, output lines, that may be rows. The device has clocking regions that control the flow of... Agent: Mccracken & Frank

20090108874 - Limited switch dynamic logic cell based register: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090108875 - Structure for a limited switch dynamic logic cell based register: A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090108876 - Decoder circuit: The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a... Agent: Mcdermott Will & Emery LLP

20090108877 - Logic gate and semiconductor integrated circuit device using the logic gate: A disclosed logic gate including a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor and also includes a resistance device connected in series with a source or a drain of at least one of the p-channel MOS transistor and the n-channel MOS transistor, a switching device... Agent: Ipusa, P.l.l.c

20090102505 - Remotely configurable chip and associated method: A chip is provided that includes a plurality of on-chip configurable features having a disabled and an enabled state. The on-chip configurable features are each operable to change from the disabled state to the enabled state upon receipt of a valid enablement configuration from an enabling entity. A method for... Agent: Wood, Herron & Evans, LLP (ibm-bur)

20090102506 - Adapter: An exemplary adapter comprises an input port for connecting to a first hardware device; an output port for connecting to a second hardware device; a standby output port for connecting to the second hardware device; a programmable logic device (PLD) having at least one input terminal connected to the input... Agent: PCe Industry, Inc. Att. Steven Reiss

20090102507 - Design structure for shutting off data capture across asynchronous clock domains during at-speed testing: A design structure embodied in a machine readable medium used in a design process includes an apparatus for testing logic devices configured across asynchronous clock domains, including a deactivation mechanism for deactivating, during at-speed fault testing, a local clock signal for each of a first plurality of latches having at... Agent: Cantor Colburn LLP-ibm Burlington

20090102508 - Pulsed dynamic logic environment metric measurement circuit: A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the... Agent: Ibm Corporation (mh) C/o Mitch Harris, Attorney At Law, L.L.C.

20090102509 - Reduced area active above-ground and below-supply noise suppression circuits: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20090102510 - Control circuit for controlling on-die termination impedance: The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either... Agent: Ladas & Parry LLP

20090102511 - Semiconductor device and driver control method: A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected.... Agent: Mcginn Intellectual Property Law Group, PLLC

20090102512 - Edit structure that allows the input of a logic gate to be changed by modifying any one of the metal or via masks used to form the metal interconnect structure: An edit structure is disclosed that allows the input of a logic gate to be changed by modifying any one of the metal and via masks that are used to form the metal interconnect structure. As a result, a first permanent logic state provided by a tie-in circuit can be... Agent: Law Offices Of Mark C. Pickering

20090102513 - Low power output driver: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver... Agent: Panitch Schwarze Belisario & Nadel LLP

20090096480 - Io driver with slew rate boost circuit: An IO driver utilizes a slew rate boost circuit coupled to an IO driver circuit to improve the slew rate of the driver during transitions on the output of the driver. One or more additional output stages are coupled in parallel with a primary output stage of the driver, and... Agent: Wood, Herron & Evans, L.L.P. (ibm)

20090096482 - Integrated circuit having a configurable logic gate: In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a... Agent: Brake Hughes Bellermann LLP C/o Cpa Global

20090096481 - Scheduler design to optimize system performance using configurable acceleration engines: A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data... Agent: Cantor Colburn LLP - IBM Rochester Division

20090096483 - Asynchronous clock gate with glitch protection: A tristate buffer circuit includes a tristate buffer switchable into a high impedance state in response to configuration signal, a delay stage delays the an input signal to the tristate buffer and a gating stage having inputs for the input signal, a delayed input signal and an asynchronous tristate control... Agent: Texas Instruments Incorporated

20090096484 - Level shifters: Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090096485 - Systems and methods for dynamic logic keeper optimization: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is... Agent: Texas Instruments Incorporated

20090096486 - Structure for transmission gate multiplexer: A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.... Agent: Dillon & Yudell LLP

20090091349 - High speed multiple memory interface i/o cell: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.... Agent: Christopher P Maiorana, PC Lsi Corporation

20090091350 - Method and circuit for off chip driver control, and memory device using same: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word.... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090091351 - Chip identification system and method: Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e.,... Agent: Frederick W. Gibb, Iii Gibb Intellectual Property Law Firm, LLC

20090091352 - Nanotube-based switching elements with multiple controls: Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform... Agent: Wilmerhale/boston

20090085602 - Deliberate destruction of integrated circuits: A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated... Agent: Snell & Wilmer L.L.P. (main)

20090085603 - Fpga configuration protection and control using hardware watchdog timer: An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured... Agent: Bingham Mccutchen LLP

20090085601 - Set dominant latch with soft error resiliency: A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an... Agent: Ked & Associates, LLP Intel Corporation

20090085604 - Multiple address outputs for programming the memory register set differently for different dram devices: A method, device, and system are disclosed. In one embodiment, the method includes programming a first On Die Termination (ODT) value into a first plurality of dynamic random access memory (DRAM) devices. The first plurality of DRAM devices are located on a dual inline memory module (DIMM). Additionally, the method... Agent: Intel/bstz Blakely Sokoloff Taylor & Zafman LLP

20090085605 - System and method for parallel burning using multiplex technology: A system and method for parallel burning using multiplex technology is used for burning chips of different bus types on the same transmission bus at the same time in parallel. A main control unit divides bandwidth of the transmission bus into different frequency bands, sends a control command including a... Agent: Workman Nydegger 1000 Eagle Gate Tower

20090085606 - Electronic device and integrated circuit: An electronic device with a CMOS circuit (CC) comprises a first driver circuit (10) having a first and second PMOS transistor (P1, P2) and a first and second NMOS transistor (N1, N2). The electronic device furthermore comprise a second driver circuit (20) with a third and fourth PMOS transistor (P3,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090085607 - Embedded power gating: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.... Agent: Intel Corporation C/o Intellevate, LLC

20090085608 - Systems, methods and devices for arbitrating die stack position in a multi-bit stack device: Embodiments are described for arbitrating stacked dies in multi-die semiconductor packages. In one embodiment, die identification data for at least two stacked dies are arbitrated to select one of the dies as the primary die and the other as secondary. Each die includes an input/output buffer that drives an output... Agent: Dorsey & Whitney LLP Intellectual Property Department

20090085609 - Multiplexor with leakage power regulator: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits... Agent: Ibm Corporation