Electronic digital logic circuitry inventions 02/09

20090051384 - Complementary logic circuit: A quantum device comprises first conductive members and second conductive members confining carriers in the z direction and having two dimensional electron gas on the xy plane. Third conductive members generating an electric field having an effect on the first conductive members. An insulating member easily passing a tunnel current... Agent: Law Office Of Ido Tuchman (yor)

20090051385 - Cell with fixed output voltage for integrated circuit: The invention relates to a testable integrated circuit. In order to replace ground and VDD in certain points of such a circuit, the circuit comprises a cell (34) which comprises a flipflop (11) and means (31) able to set the output voltage of the cell when the circuit is in... Agent: Nxp, B.v. Nxp Intellectual Property Department

20090051386 - integrate circuit chip with magnetic devices: A logic gate array is provided. The logic gate comprises a silicon substrate, a first logic gate layer on top of the silicon substrate, a second logic gate layer on top of the first logic gate layer, and a routing layer between the first and second logic gate layers for... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20090051387 - Field programmable gate array with integrated application specific integrated circuit fabric: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.”... Agent: Ropes & Gray LLP

20090051388 - Reducing leakage power in low power mode: Sequential circuitry comprising a data input, a data output, a clock signal input and a clamp signal input is disclosed. The sequential circuitry is arranged to clock a data signal received at said data input into said sequential circuitry in response to a clock signal received at said clock signal... Agent: Nixon & Vanderhye, PC

20090051389 - Configurable on-die termination: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels... Agent: Silicon Edge Law Group, LLP

20090051390 - Glitch reduced compensated circuits and methods for using such: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The... Agent: Texas Instruments Incorporated

20090045834 - Digital circuits with adaptive resistance to single event upset: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a... Agent: Raytheon Company, Intellectual Property

20090045835 - Signal output circuit, optical pickup and optical device: Disclosed herein is a signal output circuit for outputting a signal onto a transmission line having a given transmission characteristic, the signal output circuit including a drive circuit adapted to drive an input signal by a current; and an output resistor which is connected to an output stage of the... Agent: Robert J. Depke Lewis T. Steadman

20090045837 - Apparatus for dynamic deployment of pin functions on a chip: An apparatus for dynamic deployment of pin functions on a chip is disclosed in the present invention. The apparatus comprises: an input pin receiving unit, capable of integrating a plurality of pins and selecting pin functions according to a program; an output pin control unit, capable of issuing a control... Agent: Wpat, PC

20090045836 - Asic logic library of flexible logic blocks and method to enable engineering change: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in... Agent: Greenblum & Bernstein, P.L.C

20090045838 - Integrated circuit apparatus: An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device... Agent: Hanify & King Professional Corporation

20090045839 - Asic logic library of flexible logic blocks and method to enable engineering change: A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in... Agent: Greenblum & Bernstein, P.L.C

20090045841 - Method for radiation tolerance by implant well notching: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type... Agent: Ibm Corporation (jvm)

20090045840 - Method for radiation tolerance by logic book folding: A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be... Agent: Ibm Corporation (jvm)

20090045842 - Low-delay complimentary metal-oxide semiconductor (cmos) to emitter-coupled logic (ecl) converters, methods and apparatus: Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a... Agent: Texas Instruments Incorporated

20090045843 - Level shifter circuit with pre-charge/pre-discharge: A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel (amd)

20090045844 - Level shifter and semiconductor device having off-chip driver: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second... Agent: Volentine & Whitt PLLC

20090045845 - Adjusting output buffer timing based on drive strength: This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive... Agent: Texas Instruments Incorporated

20090045846 - Advanced repeater with duty cycle adjustment: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal.... Agent: Transmeta C/o Murabito, Hao & Barnes LLP

20090045847 - Generic flexible timer design: One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned... Agent: Patterson & Sheridan, L.L.P.

20090039913 - Semiconductor integrated circuit: A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at... Agent: Amin, Turocy & Calvin, LLP

20090039914 - System for transmission line termination by signal cancellation: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20090039915 - Integrated circuit, chip stack and data processing system: An integrated circuit includes a first connection and a memory circuit. The integrated circuit is switchable between a master mode of operation, in which a buffer between the first connection and the memory circuit is activated, and a slave mode of operation, in which the buffer between the first connection... Agent: Slater & Matsil, L.L.P.

20090039917 - Programmable interconnect structures: A method of forming a programmable interconnect structure for an integrated circuit comprises: fabricating one or more pass-gates on a substrate layer to electrically connect two points; and selectively fabricating either a memory circuit or a conductive pattern substantially above said pass-gates to control a portion of said pass-gates; and... Agent: Raminda U. Madurawe

20090039916 - Systems and apparatus for providing a multi-mode memory interface: An integrated circuit for a memory input/output (I/O) pin has five different modes of operation. The memory chip is enabled to operate with unbuffered (or registered) dual inline memory modules (DIMMs) as well as fully buffered DIMMs. A T-coil circuit equalizes the capacitive loading of the high-speed functions. An exemplary... Agent: Cantor Colburn LLP-ibm Yorktown

20090039918 - Three dimensional integrated circuits: A programmable integrated circuit (IC), comprising: a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and a first plurality of read only memory (ROM) elements capable of coupling to the first control signal, wherein a said first... Agent: Raminda U. Madurawe

20090039919 - Dynamic and differential cmos logic with signal-independent power consumption to withstand differential power analysis: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic... Agent: Knobbe Martens Olson & Bear LLP

20090033358 - Programmable via devices in back end of line level: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a... Agent: Michael J. Chang, LLC

20090033359 - Programmable logic device with millimeter wave interface and method for use therewith: A programmable logic device includes at least one input port, at least one output port, a plurality of configurable blocks and a program interface module coupled to configure the plurality of configurable blocks, the input ports and the output port in accordance with a configuration file. One or more millimeter... Agent: Garlick Harrison & Markison

20090033360 - Programmable via devices with air gap isolation: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first... Agent: Michael J. Chang, LLC

20090033361 - Switching circuits and methods for programmable logic devices: A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include... Agent: Haverstock & Owens, LLP

20090033362 - Method for forming a structure on a substrate and device: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified... Agent: Slater & Matsil, L.L.P.

20090033363 - Multi-function input terminal: A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3)... Agent: Imperium Patent Works

20090033364 - Integrated circuit device for receiving differential and single-ended signals: An integrated circuit device includes a receiver that is capable of receiving and converting either differential input signals or two unrelated single-ended input signals.... Agent: Dicke, Billig & Czaja

20090033365 - Transmitting apparatus: To provide a transmitting apparatus capable of suppressing the fluctuation of a common mode potential and performing high-speed, long-distance signal transmission. The transmitting apparatus has a main buffer circuit and a pre-emphasis buffer circuit 20. The pre-emphasis buffer circuit 20, which has a switch circuit 21, a first current source... Agent: Sughrue Mion, PLLC

20090033366 - Data transmission system and cable: A data transmission system capable of transmitting data at high speed without being bound by a counterpart's power supply voltage can be realized. The data transmission system comprises multiple electronic equipment having individual power supplies, a cable for connecting between the multiple electronic equipment so as to transmit signals therebetween,... Agent: Sughrue Mion, PLLC

20090033367 - Transmission device: A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.... Agent: Arent Fox LLP

20090033368 - Logic block, a multi-track standard cell library, a method of designing a logic block and an asic employing the logic block: A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of... Agent: Texas Instruments Incorporated

20090033369 - Arbitrary quantum operations with a common coupled resonator: A quantum logic gate is formed from multiple qubits coupled to a common resonator, wherein quantum states in the qubits are transferred to the resonator by transitioning a classical control parameter between control points at a selected one of slow and fast transition speeds, relative to the characteristic energy of... Agent: Snell & Wilmer L.L.P. (grumman)