|Electronic digital logic circuitry patents - Monitor Patents|
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Electronic digital logic circuitry January recently filed with US Patent Office 01/09Below are recently published patent applications awaiting approval from the USPTO. Recent week's RSS XML file available below.
Listing for abstract view: USPTO application #, Title, Abstract excerpt,Patent Agent. Listing format for list view: USPTO National Class full category number, title of the patent application. 01/29/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090027078 - Fault tolerant asynchronous circuits: New and improved methods and circuit designs for asynchronous circuits that are tolerant to transient faults, for example of the type introduced through radiation or, more broadly, single-event effects. SEE-tolerant configurations are shown and described for combinational logic circuits, state-holding logic circuits and SRAM memory circuits.... Agent: Schwegman, Lundberg & Woessner, P.A.
20090027080 - Low leakage and data retention circuitry: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal... Agent: Hamilton, Brook, Smith & Reynolds, P.C.
20090027079 - Method and apparatus for implementing complex logic within a memory array: A logic gate is described that implements complex logic within a memory array. The logic gate receives at least three of a first storage cell signal, a second storage cell signal, a first external signal, or a second external signal at a first input circuitry and second input circuitry. The... Agent: Ibm Corp (ya) C/o Yee & Associates PC
20090027081 - Eight transistor tri-state driver implementing cascade structures to reduce peak current consumption, layout area and slew rate: An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected. Each cascade structure may include a p-conductivity type transistor serially connected to a n-conductivity type transistor. By implementing cascade structures in a tri-state driver, there... Agent: Robert A. Voigt, Jr. Winstead Sechrest & Minick PC
20090027082 - Level shifter: A level shifter is operated at high speed. An input unit 2 generates a first one-shot pulse signal at the rise of an input signal and a second one-shot pulse signal having the same polarity as the first one-shot pulse signal at the fall of the input signal, and eliminates... Agent: Mcginn Intellectual Property Law Group, PLLC
20090027083 - Semiconductor device and electronic apparatus having the same: With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of... Agent: Fish & Richardson P.C.
20090027084 - Rapid response push-up pull-down buffer circuit: A rapid response push-up pull-down buffer circuit configuration is used as an output buffer of a semiconductor memory device. The buffer circuit includes a pre-driver outputting a driving signal in response to an input data. The buffer circuit also includes an output driver driving an output signal in response to... Agent: Ladas & Parry LLP
20090027085 - Resonant clock and interconnect architecture for digital devices with multiple clock networks: A clock and data distribution network is proposed that distributes clock and data signals without buffers, thus achieving very low jitter, skew, loose timing requirements, and energy consumption. Such network uses resonant drivers and is generally applicable to architectures for programmable logic devices (PLDs) such as field programmable gate arrays... Agent: Perkins Coie LLP01/22/2009 > patent applications in patent subcategories. recently filed with US Patent Office
01/15/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090015290 - On-die termination device to compensate for a change in an external voltage: An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared values are sent to a controller that controls an on-die termination... Agent: Ladas & Parry LLP
20090015289 - Signal transmitting device suited to fast signal transmission: A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission... Agent: Antonelli, Terry, Stout & Kraus, LLP
20090015291 - Semiconductor memory device and method of generating chip enable signal thereof: Provided are a semiconductor memory device and a method of generating a chip enable signal thereof. The device includes a plurality of memory chips and an interface chip that are stacked. Each of the memory chips includes a control signal setting unit, which sets input signals applied to first and... Agent: Volentine & Whitt PLLC
20090015292 - Semiconductor device having transfer gate between pre-buffer and main buffer: A semiconductor device includes a pre-buffer for transferring a data signal on the basis of a first power supply voltage, a main buffer for amplifying and outputting the data signal transferred by the pre-buffer on the basis of a second power supply voltage different from the first power supply voltage,... Agent: Mcginn Intellectual Property Law Group, PLLC
20090015293 - Semiconductor integrated circuit, semiconductor integrated circuit control method, and signal transmission circuit: A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks... Agent: Greenblum & Bernstein, P.L.C
20090015294 - Leakage dependent online process variation tolerant technique for internal static storage node: A device is disclosed for providing compensation current continuously to compensate for leakage current at the node of an electrical circuit, such as a chip. The device includes a dummy storage cell, a single staged current mirror circuit and a non reconfigurable keeper circuit. The keeper can be used to... Agent: Ibm Corporation01/08/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090009211 - Microcomputer and functional evaluation chip: A microcomputer for functioning according to operation modes includes: a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal, which represents one operation... Agent: Posz Law Group, PLC
20090009210 - Scan-testable logic circuit: Logic circuit comprising—at least a first combinational logic circuit 42—a first data latch 44 having a data input d and a data output q, said data output q being connected to an input of said first combinational logic circuit 42,—a second scannable data latch 43 having an output q connected... Agent: Philips Intellectual Property & Standards
20090009213 - Calibration circuit, semiconductor device including the same, and data processing system: A calibration circuit includes: replica buffers; an up-down counter that changes impedance codes of the replica buffers; latch circuits each holding the impedance codes; an end-determining circuit that activates the latch circuits in response to a completion of impedance adjustments of the replica buffers; and a 32 tCK cycle counter... Agent: Mcginn Intellectual Property Law Group, PLLC
20090009212 - Calibration system and method: A system and method to calibrate an output driver impedance of an output driver based on a termination device of a controller.... Agent: Qimonda North America Corp.
20090009214 - Semiconductor device reducing power consumption in standby mode: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is... Agent: Buchanan, Ingersoll & Rooney PC
20090009215 - Integrated circuit with multidimensional switch topology: An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes... Agent: Harness, Dickey & Pierce, P.L.C
20090009216 - Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements: An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number... Agent: Schwabe, Williamson & Wyatt, P.C.
20090009217 - Transformation of an input signal into a logical output voltage level with a hysteresis behavior: It is described a circuit and a method for transforming an input signal into a logical output. The circuit (100) comprises an inverter stage (120), connected in between the first conductor (101) and the second conductor (102). The inverter stage (120) includes a MOS switch (MP0), which comprises a first... Agent: Nxp, B.v. Nxp Intellectual Property Department
20090009218 - Literal gate using resonant tunneling diodes:01/01/2009 > patent applications in patent subcategories. recently filed with US Patent Office
20090002014 - Ultra fast differential transimpedance digital amplifier for superconducting circuits: Supercooled electronics often use Rapid Single Flux Quantum (RSFQ) digital circuits. The output voltages from RSFQ devices are too low to be directly interfaced with semiconductor electronics, even if the semiconductor electronics are cooled. Techniques for directly interfacing RSFQ digital circuits with semiconductor electronics are disclosed using a novel inverting... Agent: Milde & Hoffberg, LLP
20090002015 - Error correcting logic system: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the... Agent: Hoffman Warnick LLC
20090002016 - Retrieving data from a configurable ic: Some embodiments provide a configurable integrated circuit (IC). The IC has configurable logic circuits for performing logical operations, configurable routing circuits for routing signals between the configurable logic circuits, and a network for monitoring data. In some embodiments a method uses at least a subset of the configurable logic circuits... Agent: Adeli & Tollen, LLP
20090002017 - Multiple-mode compensated buffer circuit: A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of... Agent: Ryan, Mason & Lewis, LLP
20090002019 - Apparatus for adjusting resistance value of a driver in a semiconductor integrated circuit: An apparatus for adjusting a resistance value of a driver of a semiconductor integrated circuit in which the resistance value of the driver is adjusted according to a code signal. The apparatus includes a control means that generates a plurality of counting mode signals such that the unit of counting... Agent: Baker & Mckenzie LLP Patent Department
20090002018 - Impedance adjusting circuit and semiconductor memory device having the same: An impedance adjusting circuit includes: a first calibration resistor circuit configured to be calibrated with an external resistor and generate a first calibration code; a second calibration resistor circuit configured to be calibrated with the first calibration resistor circuit and generate a second calibration code, the second calibration resistor circuit... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090002020 - Dynamically tracking data values in a configurable ic: In some embodiments, the method, in dynamically configuring the configurable IC, dynamically configures a debug network of the configurable IC. In some such embodiments, the method, in dynamically configuring the configurable IC, further dynamically configures a set of configurable routing circuits of the configurable IC. In some embodiments the configuration... Agent: Adeli & Tollen, LLP
20090002021 - Restructuring data from a trace buffer of a configurable ic: Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data... Agent: Adeli & Tollen, LLP
20090002022 - Configurable ic with deskewing circuits: In some embodiments the configurable IC is a subcycle reconfigurable IC. In some such embodiments each of the deskew circuits further includes a space-time load control circuit for commanding the stepwise delay circuit to load during a selected subcycle. In some embodiments the multiple deskew circuits send data to trigger... Agent: Adeli & Tollen, LLP
20090002023 - Modular asic with crosspoint switch: Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch... Agent: Lathrop & Gage Lc
20090002024 - Transport network for a configurable ic: In some embodiments the configurable IC is on a single chip. In some embodiments the configurable IC further includes trigger circuits for triggering the trace buffer to stop recording a set of data. In some such embodiments the configurable IC further includes deskew circuits for temporally aligning a subset of... Agent: Adeli & Tollen, LLP
20090002025 - Memory utilizing oxide nanolaminates: Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge... Agent: Schwegman, Lundberg & Woessner/micron
20090002026 - Level conversion circuit for converting voltage amplitude of signal: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent... Agent: Buchanan, Ingersoll & Rooney PC
20090002027 - Level shifter having low duty cycle distortion: A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a... Agent: Qualcomm Incorporated
20090002028 - Mixed-voltage i/o buffer to limit hot-carrier degradation: A Mixed-voltage input and output (I/O) buffer including a pre-driver unit, a bulk-voltage generating unit, a first to a third transistors and an input stage unit is provided. The pre-driver unit outputs a first source/drain and a second signal. The bulk-voltage generating unit determines whether a first voltage or a... Agent: Jianq Chyun Intellectual Property Office
20090002029 - Test control circuit and reference voltage generating circuit having the same: A test control circuit according to an embodiment of the invention includes a test mode control unit that outputs a control signal according to a voltage trimming test signal, a decoding portion that receives the control signal and outputs a decoding signal, and a trimming signal adjusting portion that receives... Agent: Baker & Mckenzie LLP Patent Department
20090002030 - High speed signaling system with adaptive transmit pre-emphasis: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first... Agent: Shemwell Gregory & Courtney LLP
20090002031 - Slew rate controlled output driver for use in semiconductor device: An output driver for use in a semiconductor is capable of maintaining its slew rate constantly regardless of PVT (Process/Voltage/Temperature) variation. The output driver includes a pre-driving unit for pre-driving a data signal; a main driving unit for driving an output pad in response to the output signal of the... Agent: Blakely Sokoloff Taylor & Zafman LLP
20090002032 - Data synchronizer: A data synchronizer is to avoid the pulse width constraint on the data while synchronizing the data between two devices operating at different clock rates. The data synchronizer may comprise one or more storage units such as the flip-flops and a clock gating logic associated with each storage unit. The... Agent: Blakely Sokoloff Taylor & Zafman LLPPrevious industry: Electricity: measuring and testing
Next industry: Miscellaneous active electrical nonlinear devices, circuits, and systems
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