Electronic digital logic circuitry inventions 12/08

20080315911 - Receiver circuit: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a... Agent: Mcdermott Will & Emery LLP

20080315912 - Logic circuit including a plurality of master-slave flip-flop circuits: According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data,... Agent: Staas & Halsey LLP

20080315913 - Apparatus for measuring on-die termination (odt) resistance and semiconductor memory device having the same: An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The... Agent: Cooper & Dunham, LLP

20080315916 - Controlling memory devices that have on-die termination: A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The... Agent: Shemwell Mahamedi LLP

20080315914 - Data transmission device and method thereof: A data transmission device may include a transmission chip, a plurality of reception chips and/or a pair of transmission lines. The transmission chip may transmit data and the reception chips may receive the data from the transmission chip. One of the plurality of reception chips may provide a corresponding terminal... Agent: Harness, Dickey & Pierce, P.L.C

20080315915 - Semiconductor device: When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of... Agent: Mcginn Intellectual Property Law Group, PLLC

20080315917 - Programmable computing array: Methods, devices, and systems for programmable computing arrays have been described. One or more embodiments include programming both a first and a second floating gate of a combined memory and logic element to one of at least two states, wherein programming the floating gates to one of the at least... Agent: Brooks, Cameron & Huebsch , PLLC

20080315918 - Thin film transistor logic: A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full... Agent: Hewlett Packard Company

20080315919 - Logic state catching circuits: A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of... Agent: Qualcomm Incorporated

20080315920 - Signal encoder and signal decoder: A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code... Agent: Workman Nydegger 1000 Eagle Gate Tower

20080309367 - Semiconductor integrated device: A semiconductor integrated device includes an internal oscillation circuit that oscillates to output a clock signal, a logic circuit, and a control circuit. In a normal operation mode, the logic circuit loads a target data signal in synchronization with the clock signal, and in a test mode, the logic circuit... Agent: Volentine & Whitt PLLC

20080309368 - Circuit for generating on-die termination control signal: A circuit for generating an on-die termination control signal can include a first signal generation block configured to generate a first signal to prevent a first on-die terminal control from being performed in a frequency/voltage switching period, a second signal generation block configured to generate a second signal to perform... Agent: Baker & Mckenzie LLP Patent Department

20080309369 - Semiconductor integrated circuits with power reduction mechanism: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit... Agent: Antonelli, Terry, Stout & Kraus, LLP

20080309370 - Reprogrammable integrated circuit: A reprogrammable integrated circuit, including one or more logic dies including circuit components; and one or more reprogrammable interconnect dies including reprogrammable interconnect components electrically connected to the circuit components to define signal routing paths between the circuit components to allow a user to develop an integrated circuit.... Agent: Nixon & Vanderhye, PC

20080309371 - Face-to-face bonded i/o circuit die and functional logic circuit die system: An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets... Agent: Lewis And Roca LLP

20080309372 - Semiconductor memory device: The object of the present invention is to appropriately constitute such a semiconductor integrated circuit that mounts a plurality of semiconductor chips thereon so as to increase storage capacity. A semiconductor chip, including: a chip enable buffer circuit which outputs a chip enable signal in response to an output command... Agent: Foley And Lardner LLP Suite 500

20080309373 - Integrated circuit device and electronic instrument: An integrated circuit device includes a clock signal supply control circuit that controls a timing when a master clock signal output from an oscillation circuit is supplied to an internal circuit of the integrated circuit device. The clock signal supply control circuit stops supplying the master clock signal to an... Agent: Harness, Dickey & Pierce, P.L.C

20080309374 - Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same: A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the... Agent: Mcginn Intellectual Property Law Group, PLLC

20080303544 - Delay measuring device and semiconductor device: A delay measuring device according to the present invention comprises a memory cell, a delay element and a selector. The memory cell is provided with a non-inversion output terminal and an inversion output terminal, and the memory cell fetches a data value inputted from outside in synchronization with a clock,... Agent: Mcdermott Will & Emery LLP

20080303545 - Low power and low noise differential input circuit: A differential input circuit with lower power consumption and noise is disclosed. Rather than completely discharging output nodes differential circuits, the present invention equalizes the output nodes to conserver power and to reduce noise. Specifically, an equalization circuit is coupled between the output nodes of the low power and low... Agent: Silicon Valley Patent Group LLP

20080303546 - Dynamic impedance control for input/output buffers: A system and method of performing off chip drive (OCD) and on-die termination (ODT) are provided. A common pull-up network composed of transistors and a common pull-down network composed of transistors are employed to implement both of these functions. In drive mode, the pull-up network is configured to produce a... Agent: Smart & Biggar P.o. Box 2999, Station D

20080303547 - Programmable system on a chip for temperature monitoring and control: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with... Agent: Lewis And Roca LLP

20080303548 - Semiconductor device: An I/O buffer section is provided with a status setting circuit. The status setting circuit arbitrarily sets a signal state of an I/O terminal according to a combination of control signals stored in a setting register. Thus, the I/O buffer section is temporarily set to a Hi-Z state by the... Agent: Miles & Stockbridge PC

20080303549 - Data transmitting method and electronic device using the same: A data transmitting method for transmitting a software version data from a power IC to a controlling IC is provided. Firstly, a request signal is transmitted to a second pin of the power IC from a data pin of the controlling IC. Next, an acknowledge signal is transmitted to the... Agent: Bacon & Thomas, PLLC

20080303550 - Integrated circuit with plural level shifters: An integrated circuit is provided. The integrated circuit includes N level shifting devices. Each level shifting device receives a first digital signal and a second digital signal, and includes a first level shifter converting a first voltage of the first digital signal into a third voltage and converting a second... Agent: Volpe And Koenig, P.C.

20080303551 - Semiconductor device: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second... Agent: Foley And Lardner LLP Suite 500

20080303552 - Clock distribution network architecture for resonant-clocked systems: Disclosed herein is a digital system that includes a distribution network to carry a reference clock and a plurality of circuit domains coupled to the distribution network to receive the reference clock for synchronous operation in accordance with the reference clock. Each circuit domain of the plurality of circuit domains... Agent: Lempia Braidwood LLC

20080303553 - Method and apparatus for a configurable low power high fan-in multiplexer: A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal... Agent: Dillon & Yudell LLP

20080303554 - Structure for a configurable low power high fan-in multiplexer: A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal.... Agent: Dillon & Yudell LLP

20080297191 - Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array: The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects... Agent: Lewis And Roca LLP

20080297192 - Techniques for optimizing design of a hard intellectual property block for data transmission: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel... Agent: Townsend And Townsend And Crew LLP/ 015114

20080297193 - Techniques for providing calibrated on-chip termination impedance: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to... Agent: Steven J. Cahill/ Altera Corp.

20080297194 - Reconfigurable network component layers: A method for configuring an electronics device having reconfigurable network component layers is disclosed. The method selects a first group of pixels from at least one of the reconfigurable network component layers to form a network component on a substrate of the electronics device and activates the network component in... Agent: Honeywell International Inc.

20080297196 - Element controller for a resilient integrated circuit architecture: The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element... Agent: Gamburd Law Group LLC

20080297195 - Programmable rom: A programmable ROM includes first and second field effect transistors serially connected between first and second power source terminals, a third field effect transistor having a gate connected to a word line and used for data transfer between a first bit line and the drains of the first and second... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080297197 - Efficient xor calculation: In one embodiment, an exclusive-OR (XOR) calculation circuit configured to XOR a plurality of N input signals ranging from a first signal to an Nth signal is provided. The calculation circuit includes: a plurality of logic circuits arranged from a first logic circuit to a last logic circuit, wherein each... Agent: Macpherson Kwok Chen & Heid LLP

20080297198 - Two-wire transmitter: A two-wire transmitter for receiving power supply from an external circuit through two transmission lines and also transmitting a current signal based on the measurement value of a sensor includes a current control section to which a voltage is supplied from an external circuit, for controlling the current value of... Agent: Edwards Angell Palmer & Dodge LLP

20080297199 - Adjustable drive strength apparatus, systems, and methods: Apparatus, methods, and systems are disclosed, such as those involving a multi-die device having a common bus to indicate a state of each of a die of a multi-die device and that provides the state of all of the dice at a common output. Such a multi-die device can comprise... Agent: Schwegman, Lundberg & Woessner, P.A.